Abstract: An FM demodulator demodulating an FM modulated input signal through a PLL circuit, which includes a phase comparator a loop filter, a DC amplifier, a BB amplifier, and a VCO, and outputting the demodulated signal further includes a feedback circuit connected in parallel to DC amplifier and having a resistance which is a function of an external control voltage. The feedback circuit may be connected in parallel to both DC amplifier and BB amplifier. A PIN diode is typically used as a resistance variable element in the feedback circuit.

Abstract: Each of primary and secondary random-walk filters has longer and shorter time constants. A multi-valued phase comparator generates a start signal if a phase error generated when an abrupt frequency change occurs exceeds a given value. In response to the start signal, the primary and secondary random-walk filters are set to the shorter time constants. A timer is started by the start signal, and upon elapse of a predetermined period of time, sets the primary and secondary random-walk filters to the longer time constants.

Abstract: Adaptive self-calibration of a radio tuner quickly compensates for temperature changes and other errors. The tuner includes a modified PLL with a reference signal generator to provide a reference signal with a desired frequency. A phase detector measures the phase difference between the reference signal and a feedback signal. An integrator integrates the phase detector's output signal over time and a summer sums the integrator's output signal along with an analog steering signal. The summer provides the summed output signal to an ICO that provides an output signal proportionate in frequency to the summed output signal. An amplifier uses the ICO's output signal to amplify an electromagnetic signal detected by an antenna. The amplifier provides its amplified signal to a demodulator and other circuitry of the tuner. The tuner additionally includes a divider connected between the ICO and the phase detector, to provide the feedback signal by dividing ICO's output signal by a predetermined number.

Abstract: A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The phase-and-frequency detector generates UP and DOWN signals representative of a difference in phase between a pair of digital input signals. The charge pump varies an amount of charge carried within the capacitor in accordance with the UP and DOWN signals. The voltage controlled oscillator generates an output signal having a frequency controlled by both a voltage provided by the capacitor and by the UP and DOWN signals directly received from the phase-and-frequency detector. No analog damping resistor is required. Rather, the damping circuit is an digital circuit which generates adequate phase and frequency damping without a damping resistor. Damping is achieved which is substantially unaffected by process parameters and operating and ambient parameters. Method embodiments of the invention are also described.

Abstract: A method and a device for changing the phase of a generated signal by a predetermined value in a device for frequency generation. In the device for frequency generation, the generated signal is phase-locked to a reference signal where non-integer multiples of the frequency of the generated signal may be phase-locked to the reference signal by changing the phase of each of the periods of the reference signal by a value which determines the frequency of the generated signal. The phase is changed by a phase-shifter. The change of the phase of the generated signal is made by controlling the phase-shifter so that no change of the phase of the reference signal is made during at least one period of the reference signal.

Abstract: A phase-lock loop (PLL) circuit can be locked on to a synthesizer frequency without decreasing the available range of the frequency differences which the PLL circuit can accommodate during a data receive mode. An analog-to-digital conveyer (ADC) receives an analog input signal and responds to a periodic clock signal by providing a corresponding digital output signal. A phase comparator is coupled to receive the ADC digital output signal and to provide a phase error signal which is representative of a phase error in the digital output signal. A filter accumulates the value of the phase error signal into a filter first register to generate a primary frequency error value. The filter further includes a filter second register for holding a secondary frequency error value (e.g., a value which corrects for an offset between a synthesizer frequency and the PLL free-running frequency).

Abstract: To ensure error-free transmission of digital information, very stringent requirements are placed on the accuracy and stability of the clock generators. It is known to use microprocessor-controlled digital phase-locked loops for this purpose, which contain costly high-stability crystal oscillators. An accurate system clock signal is to be provided even if the reference clock signal fails. Contradictory requirements are placed on the phase-locked loops, namely, on the one hand, a wide bandwidth to achieve a small time interval error, and, on the other hand, a narrow bandwidth to minimize the effect of jitter and wander on clock accuracy if the reference clock signal should fail. The invention provides a circuit arrangement for a low-cost clock generator which generates a highly accurate clock frequency even in the event of a failure of the reference clock signal.

Abstract: A frequency synthesizer (107) utilizes a variable oscillator (114) the output of which is used as the frequency synthesizer output (115) and is fed to a digital divider (108). The output of the digital divider (108) feeds one input of a phase comparator (109). The other input of the phase comparator (109) is fed from a reference oscillator (116). A phase comparator (109) output controls the variable oscillator (114). The digital divider (108) has a division ratio that is varied with time by a multi accumulator fractional-N division system (112) such that the effective division ratio may be varied by non-integer steps. Due to the time varying division sequence applied to the digital divider (108) there is a residual spurious level on the output signal (115). A second digital sequence from the multiple accumulator fractional. N-division system (112) is generated to reduce this spurious level and is applied to the output of the phase comparator (109).

Abstract: A phase-locked signal generator which performs phase-locked control of the output of a triangular-wave VCO when a trigger signal is not inputted, and which performs, when the trigger signal is inputted, short interval suspension of oscillation of the triangular-wave VCO, and detection of a phase difference between the trigger signal and the reference clock signal by a successive phase measuring portion after the short interval by using the triangular-wave signal, thereby obtaining phase data. The measured phase data is held until the next trigger signal, and the phase of the triangular-wave VCO is controlled in accordance with the phase data so that the triangular-wave signal has a fixed phase with respect to the reference clock signal. A square-wave signal outputted from the triangular-wave VCO is used as the phase-locked clock signal.

Abstract: A digital phase lock loop (DPLL) (10) includes a first comparator (12), a second comparator (14), a third comparator (16), and adjuster (18), feedback divider (20), a threshold unit (21), a digital oscillator (23), and a loop filter (24). The first comparator (12), loop filter (24), digital oscillator (23), and feedback divider (20) of the DPLL (10) operate to produce a controlled oscillation. The second comparator (14), third comparator (16), and adjuster (18) provide a divisor to the feedback divider (20) that allows the DPLL (10) to operate with a variety of unknown system clock (22) frequencies.

Abstract: A frequency synthesizer 10 having a digital to analog converter (DAC) 40 and a feedback system which detects the deviation of a frequency modulated signal and aligns the detected deviation. DAC 40 provides a presteering stimulus for alignment purposes. After presteering alignment, the gain of DAC 40 is accurately set for frequency deviation because modulation is sourced from the same digital to analog converter that performs presteering.

Abstract: An automatic frequency control circuit which can set a local oscillator synthesizer to a small frequency division number, without requesting the exact required frequency. The automatic frequency control circuit includes a voltage source for producing a desired voltage to offset the oscillation frequency of a voltage controlled oscillator, and an adder for adding the output from the voltage source to a frequency control signal of the voltage controlled oscillator. The automatic frequency control circuit is applicable to the receiver for a satellite telecommunications apparatus.

Abstract: A current source suitable for use as a loop filter in a phase-locked loop having two aspects of automatic gain control one for prohibiting the voltage controlled oscillator from stopping as the input voltage approaches the limits of the oscillator and another to compensate for current limiting drain to source voltage drops.

Abstract: The present invention relates to a PLL frequency synthesizer including an A-D converter for receiving a frequency control voltage for a voltage-controlled oscillator for outputting a desired frequency in a frequency stable state, and converting the frequency control voltage into a corresponding digital signal and outputting the digital signal, a storage unit for storing a signal value of the digital signal, a D-A converter for converting the signal value into a corresponding analog signal and outputting the analog signal, a control unit for controlling input of the frequency control voltage to the A-D converter, reading of the signal value from the storage unit, and output of the analog signal from the D-A converter, and a loop filter for applying an output voltage of the analog signal to the voltage-controlled oscillator by the control unit before the synthesizer is started, and a high-speed frequency lock method using this synthesizer.

Abstract: An oscillator unit for a base station or the like in a digital cellular radio network. The oscillator unit includes an adjustable oven stabilized crystal oscillator (21). The oscillator unit additionally includes a non-volatile memory (27), in which is stored a control information defining the frequency of the oven stabilized crystal oscillator (21) at the start of the oscillator unit, apparatus (30, 31, 32) for deriving a reference frequency from a fixed digital transmission connection, such as a PCM connection, between the base station and the remaining cellular radio network, a frequency control loop (21, 22, 23, 24) for maintaining a long-term stability for the oven stabilized crystal oscillator (21) on the basis of a long-term average of the difference between the frequency of the oven stabilized crystal oscillator and the reference frequency.

Abstract: A voltage controlled oscillator (VCO) 16 generates a periodic clock signal without the use any resistors. Therefore, the described VCO may be advantageously incorporated into devices fabricated with semiconductor processes without special resistor-base design constraints.

Abstract: A phase lock loop (PLL) frequency synthesizer is used in a radiotelephone to provide a reference frequency to a transmitter or a receiver. This particular PLL frequency synthesizer has a wide bandwidth control loop having a high current charge pump (417) and a narrow bandwidth control loop having a low current charge pump (411). A deadzone circuit (413) is used at an output of a phase detector (405) to control the application of an error signal to the high current charge pump (417). Additionally, the PLL frequency synthesizer utilizes a loop filter (419). The loop filter (419) receives two correction signals (409', 415') and provides a single control signal for the VCO (voltage controlled oscillator) (423). The loop filter contains two time constants formed from resistive and capacitive elements. The two time constants control the bandwidth of the two control loops.

Abstract: A frequency synthesizer, which controls the fluctuation of frequency not only of a long period but also a short period, ensures a wide frequency control range and can be realized at a low cost, can be obtained.

Abstract: A method of starting up a system clock that has been generated by a phase-locked loop and correcting edge placement errors during coasting periods of the phase locked loop, and circuitry for accomplishing those methods. A low frequency master clock signal is distributed to circuits that generate high frequency local clock signals. These circuits generate the high frequency local clock signals using phase-locked loops in a frequency multiplier configuration. Lock indicator circuitry determines when the phase-locked loop has locked onto the master clock signal and then enables output buffers that then provide the high frequency clock signals to components in the system which need those local clocks. An intermediate frequency signal is fed back to the input of the voltage controlled oscillator in the phase locked loop to correct edge placement errors. A slightly earlier or leading version of the signal is used to correct cycle length variations without inducing duty cycle variations.

Abstract: A frequency synthesizer, including a phase-locked loop. The phase locked loop effects phase comparison between a comparison signal based on an output from a voltage-controlled oscillator and a reference signal based on an output from a reference oscillator. The resultant phase difference signal is submitted to a loop filter whose output serves as a control signal of the voltage-controlled oscillator. The frequency synthesizer includes a preset circuit for switching the output of the voltage-controlled oscillator by quickly charging or discharging a capacitor of the loop filter and a modifying circuit for modifying the time constant of the loop filter. The phase-locked loop is brought to phase lock at a high speed by decreasing the time constant of the loop filter when switching the output frequency.

Abstract: An apparatus and method for improving the capture performance of frequency and phase locked loops. The invention permits improved capture performance while, at the same time, maintaining the signal-to-noise ratio performance of the loop while the loop is tracking. The invention estimates the transient response of an automatic control loop. This estimate is used to control elements added to a PLL to accelerate acquisition, and eliminate the noise contribution of those added elements while the loop is tracking. The system uses the variation in the gradient of the loop transient response to derive an estimate of the loop's distance from lock. The system then uses this estimate to control loop parameters which affect the loop's acquisition.

Abstract: A broadband low-gain system for automatically frequency-locking a signal where the system uses digital and analog devices and techniques. The system includes a comparator, an up/down counter, a digital-to-analog converter, a decoder, a ring oscillator and a downcounter. The digital control signal is provided by the decoder and actuates one of a plurality of ring oscillator stages. The analog control signal is provided by the digital-to analog-converter and controls a fine-tune mechanism in the actuated stage. The system includes a master reset for clearing the counters.

Abstract: A control voltage coarse adjustment circuit including a D/A converter voltage generator is provided on a load side of a capacitor in a loop filter included in a phase locked loop. For this structure, a coarsely adjusted voltage is generated to be added to a voltage which is generated by the capacitor of the loop filter for the switch-over of channels during a communication frame. The added voltages are applied to a voltage controlled oscillator to change a frequency for the switch-over of channels. Consequently, the charge and discharge of the capacitor is carried out in a short time to suppress the influence of dielectric absorption current. Thus, the intermittent operation of the phase locked loop in which the phase locked loop is closed and opened intermittently is carried out for the saving of electric power consumption, and a carrier frequency is stabilized in the open phase locked loop by an electric charge voltage of the capacitor in the loop filter.

Abstract: A bias voltage for a VCO is generated by monitoring UP and DOWN control signals from a charge pump and generating first and second output signals upon detecting a predetermined number of consecutive UP pulses or DOWN pulses. The first output signal causes a shift register pre-loaded with a data pattern having one odd logic state to shift one bit location to left, while the second output signal moves the odd logic state one bit location to the right. The bias voltage to the VCO is selected based on the odd logic state bit location. Any variation in VCO output frequency due to intermittent ground bounce is eliminated by requiring a consecutive number of UP pulses or DOWN pulses before moving the VCO bias point.

Abstract: A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The phase-and-frequency detector generates UP and DOWN signals representative of a difference in phase between a pair of digital input signals. The charge pump varies an amount of charge carried within the capacitor in accordance with the UP and DOWN signals. The voltage controlled oscillator generates an output signal having a frequency controlled by both a voltage provided by the capacitor and by the UP and DOWN signals directly received from the phase-and-frequency detector. No analog damping resistor is required. Rather, the digital damping circuit is a digital circuit which generates adequate phase and frequency damping without a damping resistor. In this manner damping is achieved which is substantially unaffected by process parameters and operating and ambient parameters. Method embodiments of the invention are also described.

Abstract: In a clock generating apparatus or clock generator employing PLL (phase-locked loop) by controlling a VCO (voltage controlled oscillator) in response to an output obtained by phase-comparing a clock signal based on an output signal of the VCO with an externally applied timing signal, a range of an oscillating frequency of VCO is varied in accordance with a frequency variation in the timing signal. A clock generating apparatus is provided for each of plural information processing sections, so as to surely synchronize operations of data processings including data transfers between the respective sections. When a clock signal is distributed to each of the information processing sections, the clock signal outputted from the distributing circuit is phase-compared in order to control the VCO.

Abstract: A phase lock loop (PLL) is configured as a frequency synthesizer with a first programmable frequency divider placed in the input signal path and a second programmable frequency divider located between the output of an current controlled oscillator (ICO) and the second input of a phase detector. A charge pump receives control pulses from the phase detector to generate first and second currents to control the ICO. The control currents are low-pass filtered and summed before application to the ICO. To improve loop stability, the summation current to the ICO is duplicated and used to control the bias on the charge pump. With proper biasing, first and second control currents become dependent on the second programmable divider ratio and maintain the unity gain bandwidth of the loop constant at a value much less than the digital sampling rate.

Abstract: A phase locked loop including a switch between a phase detector output and a VCO input to open the PLL during a frequency change is provided. While the PLL is open, an analog error correction signal is generated by sampling any residual error coming from the phase detector, and generating the analog error correction signal to counter the residual error. Once analog error correction signal is available, the switch is closed and the error correction signal is added to the phase detector output and the PLL is allowed to settle to an optimized frequency.

Abstract: A phase control circuit for controlling the relative phase of periodic components of two logic signals having the same frequency, and one of which periodic components has a pulse-duty factor different from 50:50, said circuit includes a signal source which provides a control signal for regulating the relative phase of the periodic components of said logic signals. The control signal has a first value for phase relationships in a predetermined range of values and a second value for phase relationships outside said range of values. A phase lock detector detects the lock status of the periodic components of the logic signals. Another signal source provides a third logic signal having a periodic component having the same frequency as the periodic component of each of the two logic signals and a pulse width substantially wider than that of the two logic signals.

Abstract: Disclosed is an apparatus and method for high speed tuning to a commanded frequency using a low noise high speed frequency synthesizer employing a learning sequence. A phase-locked loop (PLL) generates the commanded frequency. High speed tuning circuitry high speed tunes the PLL to the commanded frequency. Thereafter, the high speed tuning circuitry is substantially isolated from the PLL, while learning circuitry is employed to learn a correction signal which will enable subsequent more accurate high speed tuning to the commanded frequency.

Abstract: A fundamental or subharmonic optically injection locked oscillator is coupled to a phase locked loop circuit. The injection locked oscillator has two single stage HEMT amplifiers with parallel feedback from the drain of a second transistor to a gate of a first transistor. A feedback resonant network controls the oscillator frequency. A microwave/millimeter wave source modulates a laser diode and the signal from the laser diode is then transmitted via an optical fiber to a PIN photodetector diode. The signal from the photodetector diode is injected into the oscillator at an nth subharmonic of the oscillator frequency. The feedback network may consist of a microstrip gap resonator with two tuning varactors at the ends of the resonator. The phase locked loop includes a balanced mixer used as a phase detector to compare the nth harmonic of the signal from the photodetector diode to the sampled output of the oscillator.

Abstract: A clock changeover apparatus including a reference frequency divider for dividing a reference clock by a first frequency division number; a comparative frequency divider for dividing by a second frequency division number an output clock obtained by the clock changeover apparatus; a phase comparator for comparing phase of a signal of the reference frequency divider with that of the comparative frequency divider; a clock controller for changing the output clock so as to make the phase of the signal of the reference frequency divider coincident with that of the comparative frequency divider; a clock determining member which gives an initial value of the output clock to the clock controller and is capable of selecting the initial value of the output clock arbitrarily; a changeover member for effecting changeover between the first and second frequency division numbers; and a phase lock detector for monitoring whether or not the phase of the signal of the reference frequency divider coincides with that of the compa

Abstract: The fractional division frequency synthesizer comprises a digital ramp generator producing a digital correction ramp controlled by a frequency control programmer; a divide by N divider coupled to an output of a voltage controlled oscillator with the divider being controlled by the program, where N is a selected one of an integer and a fraction one or greater; a digital phase detector coupled to a reference clock and the output of the divider to provide a digital phase error signal; a digital adder coupled to an output of the ramp generator and the phase detector to produce a ramp corrected digital phase error signal; and circuit arrangement coupled to an output of the adder and a control input of the controlled oscillator to convert the ramp corrected digital phase error signal to a ramp corrected analog phase error signal to control the controlled oscillator and thereby provide a controlled frequency signal at the output thereof.

Abstract: Biomedical information is directly digitally telemetered from the patient through a frequency modulated transmitter to a remote receiver and computer station. A phase-lock-loop circuit in the digital transmitter compensates for DC data bias by averaging and generating a scaled measure of the DC content of the digital data fed into the phase-lock-loop circuit. The average signal is then provided as a control signal to a first voltage controlled crystal oscillator, the output of which is then used as a reference frequency for the phase-lock-loop circuit. Frequency modulation of the digital data is provided by coupling the digital data directly into the voltage control input of the voltage controlled oscillator which generates the output frequency. Further control of the phase-lock-loop circuit in the transmitter is achieved by prepositioning the operating frequency of the voltage controlled oscillator by means of a microcontroller.

Abstract: A variable speed phase locked loop includes a phase detector and a voltage controlled oscillator, the output of which is provided through a divider circuit to the phase detector. A plurality of delay elements and a decoder divide the period of the phase detector input signal into discrete portions for enabling a plurality of weighted current sources. The current sources are coupled to the phase detector and change its gain. In the locked condition with minimum phase error, the gain of the phase detector is at a minimum and is progressively increased to a maximum when the phase error is maximum.

Abstract: A scanner system includes a light source for producing a light beam and a scanner for directing the light beam to a spot on a surface to a be scanned and for moving the spot across the surface along a scan line of predetermined length in a series of scan cycles. A reference clock produces a train of M reference pulses during each of the scan cycles such that each of the reference pulses represents the occurrence of a respective one of M segments of the scan cycle. An oscillator produces a train of clock pulses for use in controlling the light beam at a predetermined number of desired pixel positions along the scan line while a frequency control circuit responsive to the reference pulses varies the frequency of the oscillator during the occurrence of each of the M segments of the scan cycle in order to approximate an ideal frequency variation curve the entire scan cycle.

Abstract: An adaptive oscillator control system for use in television receivers or monitors includes a phase locked loop together with a static phase error correction system which responds to long term error signals of significant magnitude within the phase locked loop to adjust the free-running frequency of the oscillator. An oscillator range control includes a processor having a plurality of established oscillator frequency ranges which are identified by oscillator range code numbers. A measuring counter and clock circuit cooperate to count the number of clock signals occurring during the horizontal sync reference signal period to establish a frequency reference number. A first frequency approximation is provided based upon the oscillator range code number or a known standard scan frequency. A frequency detector examines the oscillator output and provides a second frequency approximation to adjust the oscillator frequency until it falls within the appropriate frequency range.

Abstract: A multiple frequency scan oscillator control system includes a phase locked loop operative upon a scan oscillator to provide phase and frequency synchronization thereof to a periodic reference signal. A static phase error correction is operative to provide adjustment of the free-running or static frequency of the scan oscillator. An error amplifier includes a pair of intercoupled differential amplifier configurations one having a constant current source and the other having a frequency dependent current source which responds to a frequency dependent bias current to alter amplifier gain. A threshold detection circuit includes a differential amplifier pair coupled to a pair of switching circuits for establishing a threshold action in response to system error voltage to indicate large magnitude error voltages and signal the need for free-running frequency adjustment of the oscillator.

Abstract: A phase locked loop is augmented by an additional mechanism which permits the closed loop cancellation of the frequency perturbing effects on the oscillator by repetitive signals well beyond the bandwidth of the phase locked loop. Successful implementation requires that the perturbations be repetitive and that the perturbing signal be available as a reference, conditions which are commonly the case. This compound loop can effectively cancel perturbations whose dynamics change only slowly compared to the speed of the added synchronous loop.

Abstract: The frequency of a local oscillator is maintained within a small frequency window around any one of a number of reference frequencies so that it can lock onto the frequency of an incoming color burst (CHRM). The oscillator (10) may be a current-controlled oscillator. Its control input is switched via a fet (32) to a capacitor (20) charged to a voltage level which will, when connected to the oscillator control input, result in the correct oscillator frequency (Fo). The connection to this capacitor (20) is made when the charge on either one of two control capacitors (22,24) exceeds a threshold value. The threshold values are exceeded when the local oscillator frequency (Fo) is respectively greater than or less than the reference frequency (Fr) by a predetermined frequency difference.

Abstract: A phase-lock loop for a swept synthesized source in which hysteresis, tuning nonlinearity, and drift over time and temperature of an oscillator incorporated into the swept synthesized source are compensated. The tuning current to the oscillator is initialized to zero to eliminate hysteresis effects. Then, the pretune current is set to produce the minimum operating frequency of the oscillator. Next, the main phase-lock loop is closed, and a low-frequency synthesizer is swept to in turn sweep the oscillator over a selected frequency span. If the selected frequency span extends over other frequency bands, the oscillator is swept to the maximum frequency of the present band and held at this frequency by a track and hold circuit. The main phase-lock loop is opened, the low-frequency synthesizer is re-initialized, the main phase-lock loop is again closed, and the low-frequency synthesizer is swept again. Each frequency band is crossed in a similar manner until the selected frequency span is swept.

Abstract: A digitally compensated modulation system for frequency synthesizers has a single modulation input line with flat frequency response to zero hertz. The above is accomplished while eliminating circuit components and adjustments by integrating reference oscillator temperature compensation, modulation compensation for changes in the voltage controlled oscillator modulation sensitivity and modulation compensation for changes in the reference oscillator modulation sensitivity. Signals requiring modulation enter a microprocessor and are summed together with a microprocessor generated signal and a temperature compensation input to create a composite modulation signal. The composite modulation signal is then multiplied by appropriate constants and sent to the synthesizer.

Abstract: An adaptive oscillator control system for use in television receivers or monitors includes a phase locked loop together with a static phase error correction system which responds to long term error signals of significant magnitude within the phase locked loop. An oscillator range control includes a processor establishing a plurality of oscillator frequency ranges identified by oscillator range code numbers. First and second frequency approximations are provided using the oscillator range code number. A confidence circuit examines the consistency of oscillator frequency maintenance within the appropriate frequency range and upon establishing the desired confidence level enables the phase locked loop to provide synchronization. Thereafter, a lock detector responds to the occurrence of frequency and phase lock by the phase lock loop to enable the static phase error corrector and deactivate the oscillator range control system.

Abstract: A fractional-N synthesizer including a phase locked loop comprising: a voltage controlled oscillator (4) providing a loop output signal, the output signal being coupled via an N variable divider (6) to a first input of a phase or frequency detector (8); a reference frequency source coupled to a second input of the phase or frequency detector (8), the detector providing at an output a control signal, in dependence upon a comparision between the signals applied to the first and second inputs, for application to a control input of the voltage controlled oscillator (4); and means for setting the division ratio (N) of the variable divider (6) in response to a frequency data word, including interpolator means (50) for periodically varying at least the LSB of the frequency data word, the interpolator means (50) comprising an input for receiving said LSB, a combiner means (70, 80) for comparing the LSB with a feedback signal, and a quantizer circuit (72, 84) and a filter circuit (74, 82) providing a predetermined del

Abstract: Separate charge pumps (58, 60 and 74, 76) drive integral and proportional control paths for a voltage-controlled oscillator (52) in a phase-locked loop (50). A control circuit (74) varies the loop gain of the phase-locked loop by varying the current supplied by the integral-path charge pump (58,60) through a range that is the square of the range through which the current supplied by the proportional-path charge pump (74, 76) is varied. As a consequence, the damping factor of the loop response changes very little as the loop gain is varied through a large range.

Abstract: A fast locking phase locked loop includes a first integrator that provides a signal representing a function of the mathematical or ideal integral of the phase difference between an input signal and a feedback signal. A voltage controlled oscillator is coupled to the first integrator and provides a signal to a phase shifter that provides the phase shifted signal that represents a function of the phase of the signal from the VCO, and a function of the integral of the phase difference between the integrated signals.

Abstract: A variable frequency signal generator includes a phase locked loop having a variable frequency oscillator which has a control port to which a frequency determining signal is applied, the output of the oscillator being fed via a frequency divider to a phase sensitive detector where it is compared with a reference frequency signal, the result of said comparison being arranged to generate a comparison signal which is fed to a loop filter which is coupled to said control port; and the signal generator having a frequency control signal applied thereto and comprising a first path being arranged to adjust the division ratio of the frequency divider, and a second path including a combiner for combining said frequency control signal and said comparison signal to produce said frequency determining signal; and a calibrator for adjusting the relative characteristics of said first and second paths to compensate for effects arising from tuning sensitivity dependence on frequency of said variable frequency generator.

Abstract: A phase locked loop circuit, which is arranged for receiving a first signal having a given frequency and producing a second signal which has the same frequency and is synchronous with the first signal, comprises control voltage generating means for generating a control voltage responding to a phase difference and a frequency difference between the first and second signals, a voltage controlled oscillator containing a ring oscillator having a multiplicity of the rows of inverters for producing a frequency output which is primarily determined by the control voltage, and a quantity-of-rows changing means for automatically changing the quantity of the inverters rows in the ring oscillator according to the control voltage.

Abstract: A phase loop demodulator, in particular for space telecommunications, comprises a primary phase loop, a locking detector circuit responsive to acquisition by the primary loop, and a secondary phase loop controlled by said detector circuit.

Abstract: A PLL circuit for use in a disk playing apparatus is constructed such that an oscillation output of a VCO is frequency divided at a frequency dividing ratio corresponding to a designated linear velocity in the disk playing apparatus. The frequency divided signal is derived as a reproduction clock signal and a gain of a variable gain amplifier which amplifies a phase error signal and uses the amplified signal as a control voltage of the VCO is changed in accordance with the designated linear velocity, so that a stable loop characteristic is always obtained.