Abstract: In a typical phase-locked loop oscillator circuit including a voltage controlled oscillator and a reference frequency source, from each of which a signal is derived and the phases of these two signals are compared in a phase detector, the output of which is applied through a loop filter to a frequency modulation input of the voltage controlled oscillator, so that the frequency of the voltage controlled oscillator is precisely controlled by the reference frequency; an improvement which comprises a maximum permitted phase error between the two inputs to the phase detector, and a phase error corrector circuit which, in response to the presence of a maximum permitted phase error, will shift the phase of one of the two signals applied to the phase detector relative to the source of that signal, such as to hold the phase error into the phase detector within the permitted maximum.

Abstract: Disclosed is a variable frequency oscillator system having a very stable center frequency and adjustable over a wide range of frequency excursions. A pair of variable frequency oscillators (VFO) are fabricated on the same integrated circuit chip so that corresponding components have substantially identical characteristics. The first VFO and a highly stable crystal oscillator provide comparable frequency output signals to a phase locked loop which provides as its output a correction signal (voltage or current) to lock the first VFO to the crystal oscillator frequency. The frequency of the second VFO in turn will be essentially the same as that of the first because of similarities in components and operating conditions as well as sharing of the correction signal between the two VFO's. The output of the second VFO provides the local clock signal and can be varied further by a second correction signal. In one embodiment, the second correction signal is provided by a second phase locked loop.

Abstract: A circuit for receiving an incoming RF signal incurring frequency drift and producing a local signal for tracking the incoming signal includes a phase-locked loop and means incorporated in the loop which compensate or correct for the frequency drift so as to maintain the loop locked on the incoming signal. The loop is defined by a phase detector, a DC amplifier and a voltage controlled oscillator connected in series. The correction means is coupled in parallel with the loop amplifier between the loop detector and amplifier at its one end and between the amplifier and a DC bias voltage supply terminal for the amplifier at its opposite end.

Abstract: A frequency synthesizer including a phase-locked loop (PLL) is provided which does not use any variable frequency divider. The output of a reference frequency oscillator is applied to a phase comparator in the PLL through a monostable multivibrator. The oscillating frequency of a voltage controlled oscillator (VCO) in the PLL can be selected by controlling a bias DC voltage applied to a control element in the VCO. The output waves from said VCO are counted at a counter during a period of the reference frequency from the reference frequency oscillator of the PLL. The count operation is repeated at a predetermined time interval. After completion of each count operation, the number in the counter corresponding to the least digit column of the decimal number is discriminated to determine whether it is within a predetermined range or not. The range is determined correspondingly to a locking range of the PLL.

Abstract: A variable oscillator controlled by a phase-locked loop to lock on to a received pulse of radio frequency waves, sample and hold circuitry sampling the control signal in the loop and storing the signal, and a timed switch disconnecting the oscillator from the loop and connecting it to the sample and hold circuit after a predetermined period of time so that the oscillator is locked on to the radio frequency after the single pulse ceases.

Abstract: A sample-and-hold circuit has an input terminal connected to a source of analog voltages to be stored, this terminal being connected during a sampling phase via a first switch to an output terminal and to an input of a first amplifier working into a storage capacitor by way of a second switch also closed during that phase. The capacitor is tied to one of two differential inputs of a second amplifier, the other differential input being connected to the output of the first amplifier upon closure of a third switch during a holding phase in which the first and second switches are open.

Abstract: A frequency synthesizer in which the frequency of a variable frequency oscillator is controlled by means of a control signal and wherein means are provided for determining whether any frequency variation results from a drift in the frequency of the variable frequency oscillator means being provided for generating and maintaining an additional drift control signal to compensate for such drift. The drift control signal is inhibited from change either when it is detected that the control signal is in excess of that which would result solely from drift or the control signal is representative only of a quantisation error.

Abstract: A high power, pulsed microwave frequency converter for a microwave communications system including a phase locked loop with a voltage controlled microwave oscillator that provides at least five watts of pulsed RF output power, the components of the loop being designed to lock on the desired RF output frequency within approximately 20 nanoseconds or during the initial portion of each pulse so that the converter coherently converts two low level signals, one or both of which may be pulsed, into a higher level narrow pulse signal at the sum or difference of the frequencies of the two low level signals.

Abstract: In a typical phase-locked loop oscillator circuit including a voltage controlled oscillator and a reference frequency source, from each of which a signal is derived and the phases of these two signals are compared in a phase detector, the output of which is applied through a loop filter to a frequency modulation input of the voltage controlled oscillator, so that the frequency of the voltage controlled oscillator is precisely controlled by the reference frequency; an improvement which comprises a maximum phase error detector which determines a maximum permitted phase error between the two inputs to the phase detector, and a phase error corrector circuit which, in response to the presence of a maximum permitted phase error, will shift the phase of one of the two signals applied to the phase detector relative to the source of that signal, such as to hold the phase error into the phase detector within the permitted maximum.

Abstract: A frequency synthesizer of the phase lock loop type including a reference frequency source, a voltage-controlled oscillator and a frequency divider connected to the oscillator output to divide the output frequency by a selectively-variable integer N. The outputs of the frequency divider and the reference frequency source are applied to a phase comparator which has an output connected to a filter. The filter output is applied through a multiplier, having a multiplication factor n proportional to N, to the input of the voltage controlled oscillator. The frequency divider and the multiplier are controlled by the same control means in order to keep the loop gain constant, irrespective of the amount of change in N.

Abstract: In a phase locked oscillator (PLO), the frequency of a voltage controlled oscillator (VCO) is changed in response to error signals indicating the phase error between the individual pulses of a stream of input pulses and the output pulses of the PLO. The running of the PLO is temporarily interrupted whenever the phase error exceeds a predetermined amount, and is restarted in phase with the next input pulse from the stream of pulses. A residual part of the error signal causing the interruption is accumulated so that after each interruption the frequency of the oscillator is closer to the frequency of the input stream of pulses. The process is repeated as required until phase lock is achieved.