Semiconductor Mounts Patents (Class 333/247)
  • Publication number: 20100045407
    Abstract: An electromagnetic interconnect method and apparatus effects contactless, proximity connections between elements in an electronics system. Data to be communicated between elements in an electronic system are modulated into a carrier signal and transmitted contactlessly by electromagnetic coupling. The electromagnetic coupling may be directly between elements in the system or through an intermediary transmission medium.
    Type: Application
    Filed: November 3, 2009
    Publication date: February 25, 2010
    Inventor: Charles A. Miller
  • Patent number: 7663455
    Abstract: A high frequency module incorporates a layered substrate, a plurality of elements mounted on a top surface of the layered substrate, and a metallic casing that covers these elements. The plurality of elements mounted on the top surface of the layered substrate include a band-pass filter element. The band-pass filter element includes a plurality of conductor layers for band-pass filter and a plurality of dielectric layers for band-pass filter that implement a function of a band-pass filter, but does not include any conductor layer that functions as an electromagnetic shield. A conductor layer for grounding that the layered substrate includes and the casing are each opposed to the band-pass filter element, and thereby function as an electromagnetic shield for the band-pass filter element.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: February 16, 2010
    Assignee: TDK Corporation
    Inventors: Tomoyuki Goi, Hideaki Fujioka, Masami Itakura, Hideya Matsubara
  • Patent number: 7612630
    Abstract: An electromagnetic interconnect method and apparatus effects contactless, proximity connections between elements in an electronics system. Data to be communicated between elements in an electronic system are modulated into a carrier signal and transmitted contactlessly by electromagnetic coupling. The electromagnetic coupling may be directly between elements in the system or through an intermediary transmission medium.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: November 3, 2009
    Assignee: FormFactor, Inc.
    Inventor: Charles A. Miller
  • Publication number: 20090267201
    Abstract: A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core.
    Type: Application
    Filed: August 22, 2008
    Publication date: October 29, 2009
    Applicant: National Chiao Tung University
    Inventors: Edward Yi Chang, Wei-Cheng Wu, Ruey-Bing Hwang, Li-Han Hsu
  • Patent number: 7609128
    Abstract: A branch path having a transmission line and a distributed constant line includes a resonant circuit. The resonant circuit resonates at a predetermined operating frequency when the branch path is in OFF state. At this time, the distributed constant line has a predetermined impedance. Further, an impedance of a node between the resonant circuit and distributed constant line can be set on a circle of a reflection coefficient 1 near short on the Smith chart.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: October 27, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hiroshi Mizutani
  • Patent number: 7609130
    Abstract: In a high-frequency module, mounting lands arranged to mount at least one filter device having at least one set of an unbalanced terminal and two balanced terminals are provided at one side of a substrate top surface, and mounting lands arranged to mount at least one element electrically connected to the filter device are arranged at the opposite side. At least two of a plurality of connection terminals provided on a substrate bottom surface are respectively connected to conductor patterns connected to via-hole conductors penetrating the substrate within a mounting area for mounting the filter device via connection lines and are arranged at a pitch which is less than the pitch of the via-hole conductors.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: October 27, 2009
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Taturo Nagai
  • Publication number: 20090206959
    Abstract: In a radio-frequency wave module including a transmission path based on a distributed parameter element, the transmission path being part of an input/output terminal, a plurality of cavity-structured concave portions for containing semiconductor-including mounted components therein, grounding-use metallic electrodes, dielectric substrates of at least two or more layers, and semiconductors, electrical separation is established between the grounding-use metallic electrodes which form the transmission paths based on the distributed parameter element and at least one of the grounding-use metallic electrodes which are formed on bottom surfaces of the plurality of cavity-structured concave portions for containing the semiconductor-including mounted components therein.
    Type: Application
    Filed: February 6, 2009
    Publication date: August 20, 2009
    Inventor: Eiichi HASE
  • Publication number: 20090206958
    Abstract: According to one embodiment, there is provided a semiconductor digital communication device comprising communication drive and sense electrodes formed in a single plane, where the electrodes have relatively high sidewalls. The relatively high sidewalls permit low electrical field densities to be obtained in the sense and drive electrodes during operation, and further permit very high breakdown voltages to be obtained between the electrodes, and between the drive electrode and an underlying ground plane substrate. The device effects communications between drive and receive circuits through the drive and sense electrodes by capacitive means, and in a preferred embodiment is capable of effecting relatively high-speed digital communications. The device may be formed in a small package using, by way of example, CMOS or other semiconductor fabrication and packaging processes.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 20, 2009
    Applicant: Avago Technologies ECBU (Singapore) Pte. Ltd.
    Inventors: Fun Kok Chow, Gek-Yong Ng, Kah Wang Lee
  • Publication number: 20090206960
    Abstract: According to one embodiment, there is provided a high voltage isolation dual capacitor communication system comprising communication drive and sense electrodes and corresponding first and second capacitors that are formed in two separate devices. The two devices are electrically connected in series to provide a single galvanicly-isolated communication system that exhibits high breakdown voltage performance in combination with good signal coupling. The system effects communications between drive and receive circuits through the first and second capacitors, and in a preferred embodiment is capable of effecting relatively high-speed digital communications. The system may be formed in a small package using, by way of example, CMOS or other semiconductor fabrication and packaging processes.
    Type: Application
    Filed: March 3, 2009
    Publication date: August 20, 2009
    Applicant: Avago Technologies ECBU (Singapore) Pte Ltd.
    Inventors: Gek Yong Ng, Fun Kok Chow, Kah Weng Lee
  • Patent number: 7576629
    Abstract: A semiconductor device according to the one embodiment of the present invention comprises a signal line; and a reference potential plane which is separated from the signal line and opposed to the signal line, the reference potential plane being provided with a discontinuous region in a portion intersecting with the signal line, as a delay element to be added to the signal line.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: August 18, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsu Nagamatsu, Yuuichi Hotta
  • Patent number: 7573359
    Abstract: An electronic device may be formed of a printed circuit board having integrated circuits mounted thereon. A backing plate may compress an insulating layer against a microstrip line formed on one surface of said circuit board opposite to the surface that includes integrated circuits. By compressing said backing plate against said insulating layer, less crosstalk may result from the formation of a microstrip on the bottom surface of the printed circuit board. The backing plate may also be used to secure a cooling device, such as a heat sink, on the opposite side of the circuit board.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: August 11, 2009
    Assignee: Intel Corporation
    Inventors: Richard K. Kunze, Olufemi B. Oluwafemi, Chung-Chi Huang, Xiaoning Ye
  • Publication number: 20090184784
    Abstract: Reference plane voids with a strip segment for improving transmission line integrity over vias permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.
    Type: Application
    Filed: January 17, 2008
    Publication date: July 23, 2009
    Inventors: Sungjun Chun, Anand Haridass, Roger D. Weekly
  • Patent number: 7565116
    Abstract: A high frequency module comprises a layered substrate. Inside the layered substrate, a reception diplexer for processing reception signals and a transmission diplexer for processing transmission signals are provided. The reception diplexer and the transmission diplexer are located in two different regions inside the layered substrate. A conductor portion that is connected to the ground and that electromagnetically separates the reception diplexer and the transmission diplexer from each other is provided between the two regions inside the layered substrate. The conductor portion is formed by using a plurality of through holes.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: July 21, 2009
    Assignee: TDK Corporation
    Inventors: Yuichiro Okuyama, Hideya Matsubara, Shinya Nakai, Masashi Iwata
  • Publication number: 20090160583
    Abstract: In one example, a hybrid surface mountable package includes a housing at least partially defining a sealed cavity, two microwave integrated circuits (MIC) chips positioned inside the sealed cavity, and a very-high-speed interconnect connecting the two MIC chips to each other. The very-high-speed interconnect includes strong coupling co-planar waveguide (CPWG) transmission lines.
    Type: Application
    Filed: December 19, 2008
    Publication date: June 25, 2009
    Applicant: Finisar Corporation
    Inventors: Jianying Zhou, Yuheng Lee
  • Patent number: 7542006
    Abstract: An inverse F type antenna is provided and includes first wiring portions provided on an upper face of a board, second wiring portions provided on a lower face of the board, connecting portions electrically connecting the first wiring portions and the second wiring portions, in which the connecting portions are provided at a side face of the board.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: June 2, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Tomoharu Fujii
  • Patent number: 7528792
    Abstract: According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing sides of the integrated circuit are substantially parallel to the sidewalls of the pocket. An interconnect electrically couples the integrated circuit to a bond pad disposed on the outer surface of the dielectric layer. The interconnect has a length that is minimized to result in reduced inductance of the semiconductor device.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: May 5, 2009
    Assignee: Raytheon Company
    Inventors: James S. Mason, John Michael Bedinger, Raj Rajendran
  • Publication number: 20090065954
    Abstract: Embodiments of the invention relate to a package design incorporating an ultra-low characteristic impedance transmission line (T-line) bundle. The T-line bundle can extend from inside the package to outside the package in order to provide power delivery and power interconnect for a chip. In one embodiment, the T-line bundle can be attached at the die. In another embodiment, the T-line bundle can be attached to the package substrate. The T-line bundle can be a stack of parallel planar transmission line strips in a periodic pattern where the dielectric material of the strips can be a high-k dielectric and can be flexible, semi-rigid, or precision rigid.
    Type: Application
    Filed: September 7, 2007
    Publication date: March 12, 2009
    Inventor: Attma Sharma
  • Publication number: 20090058570
    Abstract: According to one embodiment, a wiring board includes a transmission line provided to perform communications between a first semiconductor chip and a second semiconductor chip, the transmission line is formed of a distributed constant wiring portion having a characteristic impedance matched to one of an output impedance of the first semiconductor chip and an output impedance of the second semiconductor chip, and a lumped constant wiring portion which is narrower than the distributed constant wiring portion and shorter than a length which can be regarded as a lumped constant circuit.
    Type: Application
    Filed: August 19, 2008
    Publication date: March 5, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshihiro TSUJIMURA
  • Patent number: 7498907
    Abstract: A transmission line substrate includes a spurious-wave suppression circuit in which a divider divides a signal line of a driving control signal connected to a semiconductor device into two signal lines of the same phase. A delay unit is connected to one of the two signal lines, and includes a signal line with a length of substantially one half of an in-substrate effective wavelength of a spurious wave. Two parallel lines that include two parallel signal lines, on which spurious waves are in opposite phases, are connected to the delay unit and the other one of the two signal lines, respectively. A resistor is arranged on the two parallel lines, and connects between the two parallel signal lines. A combiner includes a signal line that combines the two parallel signal lines, and outputs a combined signal to the outside.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: March 3, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Suzuki, Teruo Furuya
  • Publication number: 20090051469
    Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.
    Type: Application
    Filed: October 29, 2008
    Publication date: February 26, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Uei-Ming Jow, Chang-Sheng Chen, Chin-Sun Shyu, Min-Lin Lee, Shinn-Juh Lay, Ying-Jiunn Lai
  • Publication number: 20090033443
    Abstract: A circuit board is provided, and a method for manufacturing the same, suitable for use in high frequency circuits, and comprising a planar pattern of transmission line conductors for linking components formed on or within the circuit board, the transmission line conductors being formed within a corresponding pattern of trenches arranged so that the conductors lie beneath a finished surface of the circuit board which is polished flat to permit one or more cover boards to be bonded thereto.
    Type: Application
    Filed: June 14, 2006
    Publication date: February 5, 2009
    Applicant: BAE Systems plc
    Inventor: Robert Brian Greed
  • Patent number: 7479857
    Abstract: Systems and methods are taught for blocking the propagation of electromagnetic waves in parallel-plate waveguide (PPW) structures. Periodic arrays of resonant vias are used to create broadband high frequency stop bands in the PPW, while permitting DC and low frequency waves to propagate. Particular embodiments include clusters of small vias that effectively function as one large via, thereby increasing stop band bandwidth and maximizing parallel plate capacitance. Cluster vias can be configured to additionally provide a shielded and impedance matched route within the interior area of the cluster through which signal vias can connect transmission lines disposed in planes lying above and below the PPW. Important applications include electromagnetic noise reduction in layered electronic devices such as circuit boards, ceramic modules, and semiconductor chips.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: January 20, 2009
    Assignee: WEMTEC, Inc.
    Inventor: William E. McKinzie, III
  • Publication number: 20090015354
    Abstract: An electromagnetic bandgap structure and a printed circuit board including it as well as a method of manufacturing thereof that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. The electromagnetic bandgap structure in accordance with an embodiment of the present invention can include: a first metal layer; a first dielectric layer, stacked on the first metal layer; a metal plate, stacked on the first dielectric layer; a second dielectric layer, stacked on the metal plate and the first dielectric layer; a second metal layer, stacked on the second dielectric layer; and a via, directed from the metal plate to the first metal layer and the second metal layer. The via can be connected to the first metal layer and is not connected the second metal layer.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 15, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Han Kim, Dae-Hyun Park
  • Patent number: 7477197
    Abstract: Electronic devices and methods for their formation are described. One device relates to an electronic assembly including a substrate having a first surface and a second surface opposite the first surface. The electronic assembly also includes at least one RF front-end module coupled to the first surface of the substrate, and a ground plane layer positioned on the second surface of the substrate. The electronic assembly also includes an insulating layer on the ground plane layer, with the ground plane layer positioned between the second surface and the insulating layer. In addition, the electronic assembly also includes an antenna layer on the insulating layer, with the insulating layer positioned between the antenna layer and the ground plane layer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: January 13, 2009
    Assignee: Intel Corporation
    Inventors: Xiang Yin Zeng, Jiangqi He, Guizhen Zheng
  • Patent number: 7471175
    Abstract: A mixed-signal circuit board can provide a flexible arrangement of multiple RF transmission mediums in a single lightweight and compact structure as well as support embedding electronic devices within RF transmission paths. The transmission mediums may include a voided waveguide, a dielectric waveguide, a microstrip, a suspended microstrip, a traditional stripline, and a suspended stripline. The center conductors in each transmission medium may be constructed on the same plane or the same PCB layer in order to simplify coplanar design. A distribution board can be provided to deliver the power supply and control signals to the active electronic devices placed in the signal path of the RF board for signal processing and within covered cavities provided within the RF board.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: December 30, 2008
    Assignee: EMS Technologies, Inc.
    Inventor: John D. Voss
  • Patent number: 7449982
    Abstract: Systems and methods are taught for blocking the propagation of electromagnetic waves in parallel-plate waveguide (PPW) structures. Periodic arrays of resonant vias are used to create broadband high frequency stop bands in the PPW, while permitting DC and low frequency waves to propagate. Some embodiments of resonant via arrays are mechanically balanced, which promotes improved manufacturability. Important applications include electromagnetic noise reduction in layered electronic devices such as circuit boards, ceramic modules, and semiconductor chips.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: November 11, 2008
    Assignee: WEMTEC, Inc.
    Inventor: William E. McKinzie, III
  • Publication number: 20080272863
    Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.
    Type: Application
    Filed: July 16, 2008
    Publication date: November 6, 2008
    Applicant: LSI LOGIC CORPORATION
    Inventors: LEAH MILLER, IVOR BARBER, ARITHARAN THURAIRAJARATNAM
  • Publication number: 20080272862
    Abstract: An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.
    Type: Application
    Filed: July 11, 2008
    Publication date: November 6, 2008
    Applicant: International Business Machines Corporation
    Inventors: Paul M. Harvey, Kazushige Kawasaki, Gen Yamada
  • Publication number: 20080266031
    Abstract: A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 ?m therebetween.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 30, 2008
    Inventors: Yutaka UEMATSU, Hideki Osaka, Yoji Nishio, Eiichi Suzuki
  • Patent number: 7436270
    Abstract: A duplexer assembly is provided and includes a circuit board and a duplexer connected to the circuit board by a joint material, wherein the joint material provides a joint thickness of at least about 10 mils.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: October 14, 2008
    Assignee: Delphi Technologies, Inc.
    Inventors: Joseph M. Ratell, Jr., Michael T. Dolce
  • Patent number: 7432778
    Abstract: An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node (204a) for receiving an output current to be impedance matched; a second node (212, 214) for receiving output current from the first node; a first current conductor (202c) for carrying current from the first node to the second node; a third node (204b) for receiving output current from the second node; and a second current conductor (202d) for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: October 7, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Philippe Riondet, Gilles Montoriol, Jacques Trichet
  • Publication number: 20080238585
    Abstract: An apparatus includes a substrate which includes an electronic component mounted on the substrate, the electronic component for processing a pair of signals, the substrate including a first wire for transmitting one of the signals, the first wire being formed on a first layer of the substrate, and a second wire for transmitting another one of the signals, the second wire being formed on a second layer of the substrate in a first region under the electronic component and being formed on a third layer in a second region of an other part of the first region.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 2, 2008
    Applicant: NEC CORPORATION
    Inventor: Tomokazu Tokoro
  • Publication number: 20080238584
    Abstract: An electronic device may be formed of a printed circuit board having integrated circuits mounted thereon. A backing plate may compress an insulating layer against a microstrip line formed on one surface of said circuit board opposite to the surface that includes integrated circuits. By compressing said backing plate against said insulating layer, less crosstalk may result from the formation of a microstrip on the bottom surface of the printed circuit board. The backing plate may also be used to secure a cooling device, such as a heat sink, on the opposite side of the circuit board.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Inventors: Richard K. Kunze, Olufemi B. Oluwafemi, Chung-Chi Huang, Xiaoning Ye
  • Publication number: 20080191818
    Abstract: In one example embodiment, a high-speed transponder includes a printed circuit board having a set of coplanar high-speed traces, and a high-speed circuit and a package mounted to the printed circuit board. The package includes an outside housing and a second high-speed circuit positioned inside the housing. The high-speed transponder also includes a high-speed feed thru which includes an inside coplanar structure positioned inside the housing, a strip line structure positioned through the housing, and an outside coplanar structure positioned outside the housing. The second high-speed circuit is operably coupled to the inside coplanar structure, which is operably coupled to the strip line structure, which is operably coupled to the outside coplanar structure, which is operably coupled to the first high-speed circuit via the set of coplanar high-speed traces. The signal plane of the outside coplanar structure is flipped with respect to a signal plane of the inside coplanar structure.
    Type: Application
    Filed: February 12, 2008
    Publication date: August 14, 2008
    Applicant: FINISAR CORPORATION
    Inventors: Yuheng Lee, Jianying Zhou, Yan Yang Zhao, Christopher R. Cole, Bernd Huebner
  • Patent number: 7411279
    Abstract: An example of a circuit structure may include a first dielectric layer having first and second surfaces, and a channel extending at least partially between the first and second surfaces and along a length of the first dielectric layer. First and second conductive layers may be disposed on respective portions of the first and second surfaces. A first conductor, having an end, may be disposed on a surface of the first dielectric layer, including at least a first portion extending around at least a portion of the conductor end. The second conductive layer may line the channel extending around a portion of the conductor end. Some examples may include a stripline having a second conductor connected to the first conductor. Some examples may include a cover having a wall positioned on the first dielectric over the second conductor.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 12, 2008
    Assignee: Endwave Corporation
    Inventors: Edward B. Stoneham, Thomas M. Gaudette
  • Publication number: 20080186112
    Abstract: A package structure having a recessed portion for accommodating an electronic component for inputting and outputting high-frequency signals such as a semiconductor device while preventing unwanted resonance and increases in loss of the high-frequency signals. Transmission lines for inputting and outputting high-frequency signals to and from the electronic component are formed on a dielectric substrate. Electrode lines for grounding are formed over the dielectric substrate adjacently to the transmission lines. The front ends of the electrode lines for grounding which face the recessed portion are connected with a metal enclosure for grounding via conductors in through-holes.
    Type: Application
    Filed: December 20, 2007
    Publication date: August 7, 2008
    Inventor: Eiichi HASE
  • Patent number: 7400222
    Abstract: Disclosed herein are a transmission line of coaxial type and a manufacturing method thereof, capable of preventing a radiative signal loss of signal lines during transmission of an RF signal and removing signal interference between adjacent signal lines, thus allowing signal lines to be compactly arrayed during a manufacture of IC, and reducing a dimension of the IC. The transmission line of coaxial type includes grooves provided on a semiconductor substrate, a first ground layer, an electrically conductive epoxy coated on a flat part of the first ground layer except the grooves, second ground layers provided on the electrically conductive epoxy, a dielectric film provided at a position above the grooves and the second ground layers, a third ground layer provided on an upper surface of the dielectric film, and signal lines placed in spaces defined by the grooves and a lower surface of the dielectric film.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: July 15, 2008
    Assignee: Korea Advanced Institute of Science & Technology
    Inventors: Young Se Kwon, Ju Hyun Ko, Seong Ho Shin
  • Patent number: 7388451
    Abstract: A technique for interconnecting monolithic microwave integrated circuits (MMICS) on a substrate, and a method for fabricating substrate sections that facilitate such interconnection. A MMIC is positioned in a gap in the substrate, on which are formed conventional microwave transmission lines for purposes of MMIC interconnection. On each side of the gap, the substrate is tapered in thickness between the normal substrate thickness and the much smaller thickness of the MMIC. The transmission lines in this transition region are tapered in width as the substrate is tapered in thickness, thereby maintaining uniform transmission line characteristics, particularly the characteristic impedance of the transmission line. Small connector ribbons provide electrical connection between the tapered transmission lines and the MMIC. A method is also disclosed for fabricating multiple substrate sections for use in the structure of the invention.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: June 17, 2008
    Assignee: Northrop Grumman Corporation
    Inventors: David J. Brunone, Mark Kintis
  • Publication number: 20080122560
    Abstract: An integrated passive device (20) includes a first wafer (22), a first integrated device (28) formed on a first surface (24) of the wafer (22), and a second integrated device (30) formed on a second surface (26) of the wafer (22), the second surface (26) opposing the first surface (24). A microelectromechanical (MEMS) device (72) includes a second wafer (74) having a MEMS component (76) formed thereon. The integrated passive device (20) and the MEMS device (72) are coupled to form an IPD/MEMS stacked device (70) in accordance with a fabrication process (90). The fabrication process (90) calls for forming (94) the second integrated device (30) on the second surface (26) of the wafer (22), constructing (100) the MEMS component (76) on the wafer (74), coupling (104) the wafers (22, 74), then creating the first integrated device (28) on the first surface (24) of the first wafer (22).
    Type: Application
    Filed: November 7, 2006
    Publication date: May 29, 2008
    Inventor: Lianjun Liu
  • Patent number: 7342471
    Abstract: Systems and methods are taught for blocking the propagation of electromagnetic waves in parallel-plate waveguide (PPW) structures. Periodic arrays of resonant vias are used to create broadband high frequency stop bands in the PPW, while permitting DC and low frequency waves to propagate. Some embodiments of resonant via arrays are mechanically balanced, which promotes improved manufacturability. Important applications include electromagnetic noise reduction in layered electronic devices such as circuit boards, ceramic modules, and semiconductor chips.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: March 11, 2008
    Assignee: Wemtec, Inc.
    Inventor: William E. McKinzie, III
  • Patent number: 7312671
    Abstract: The present invention has a configuration such that in a multiplier crystal oscillator wherein a multilayer board having earthing metal films on both principal planes of an intermediate board, and mount boards laminated on both sides thereof, and at least one multiplier LC filter is arranged on one principal plane of the laminated board, an opening is provided in the earthing metal film that is provided on one principal plane of the intermediate board opposed to an arrangement region of the LC filter, and a ground of the intermediate board is exposed. An object of the present invention is to provide a multiplier oscillator wherein particularly the displacement and irregularity of the multiple frequencies serving as the output frequency is prevented, and furthermore spurious oscillations are suppressed.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: December 25, 2007
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventor: Takashi Matsumoto
  • Patent number: 7301243
    Abstract: The present invention relates to a high-reliable semiconductor device in which electrodes formed on substrates are prevented from deteriorating by sealing the electrodes with a frame member rather than a sealing material. The frame member in the present invention surrounds electrodes formed on the substrates. The inside of the frame member is vacuous or filled with a gas which does not react with the electrodes such as an inert gas and, thereby, the electrodes are prevented from deteriorating by attacks of oxygen or moisture.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: November 27, 2007
    Assignees: Sharp Kabushiki Kaisha, Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Fujitsu Limited, Matsushita Electric Industrial Co., Ltd., Renesas Technology Corp., Rohm Co., Ltd.
    Inventors: Tadatomo Suga, Toshihiro Itoh
  • Patent number: 7298235
    Abstract: An antenna array is assembled by direct attaching a flip chip transmit/receive (T/R) module to an antenna circuit board. A fillet bond is applied to the circuit board and the flip chip T/R module around at least a portion of the periphery of the flip chip T/R module.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: November 20, 2007
    Assignee: Raytheon Company
    Inventors: Mark S. Hauhe, Kevin C. Rolston, Clifton Quan, Harold S. Fenger, Tse E. Wong
  • Patent number: 7259644
    Abstract: A substrate having a microstrip line structure is provided comprising a trench provided at least in one main surface of a base body constituting the substrate having an inner surface geometry of an unbent curved surface and corresponding to the pattern of the microstrip line; a laminate film having a ground conductive layer and an insulating layer formed along the inner surface geometry of the trench; and a signal line layer constituting the microstrip line formed on the laminate film; where the signal line layer has a configuration separated for each trench.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: August 21, 2007
    Assignee: Sony Corporation
    Inventor: Naoto Sasaki
  • Patent number: 7248222
    Abstract: A high-frequency module includes a stiffener (a support substrate), a resin base member of which one surface is fixed to the stiffener, a first conductive pattern formed on said one surface of the resin base member, a second conductive pattern formed on the other surface of the resin base member for constituting a waveguide in combination with the first conductive pattern to pass a high-frequency signal through the resin base member and including a window for allowing the high-frequency signal to pass therethrough, a cap for covering a semiconductor element and for absorbing or reflecting the high-frequency signal, an adopter (a waveguide tube) fixed onto the second conductive pattern such that one open end thereof surrounds the window, and an antenna fixed to the other open end of the adaptor.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: July 24, 2007
    Assignee: Fujitsu Limited
    Inventors: Shinya Iijima, Tomoyuki Abe, Nobuyuki Hayashi, Yoji Ohashi, Toshihiro Shimura
  • Patent number: 7239222
    Abstract: A high frequency circuit module for use in an automotive radar or the like, in which RF circuit parts are mounted on both sides of a hard multilayer dielectric substrate, and a transmission line connecting the RF circuit parts provided on both sides is constructed by a via group including a periodical structure or a via having a coaxial structure perpendicular to faces of the multilayer dielectric substrate. As the multilayer dielectric substrate, a hard multilayer substrate using metallic layers as a microstrip line wiring layer, a DC/IF signal line layer, and grounding metal layers for shielding which are disposed on and under the DC/IF signal line is employed. By using the transmission line achieved by a through via having the periodical structure or the through via having the coaxial structure, an electromagnetic wave propagating in parallel between the grounding conductors is confined.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: July 3, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Hideyuki Nagaishi, Hiroshi Kondoh
  • Patent number: 7236070
    Abstract: An electronic component module has a device-side module A and an antenna-side module B. The device-side module A is equipped with a first dielectric substrate 11 that is formed with a first transmission line 11a and a high-frequency device 13 that is mounted on the first dielectric substrate 11 and is connected to the first transmission line 11a. The antenna-side module B is equipped with a second dielectric substrate 12 that is laid on the first dielectric substrate 11 in such a manner that they are arranged in a lamination direction and that is formed with a second transmission line 12a that is electrically connected to the first transmission line 11, and an antenna element 14 that is provided on the second dielectric substrate 12 and electrically connected to the high-frequency device 13 via the second transmission line 12a and the first transmission line 11a.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: June 26, 2007
    Assignee: TDK Corporation
    Inventors: Eriko Ajioka, Hitoyoshi Kurata, Hideaki Shimoda, Shigeru Asami
  • Patent number: 7221244
    Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: May 22, 2007
    Assignee: Motorola, Inc.
    Inventors: John C. Estes, Rodolfo Lucero, Anthony M. Pavio
  • Patent number: 7187559
    Abstract: This invention is a circuit board device having a filter element. It has a base board (4), a circuit part (2) mounted on the base board (4), a filter element (5) arranged between the circuit part (2) and the base board (4), and a semiconductor component (3) mounted on the same plate as the circuit part (2) on the base board (4). The semiconductor component (3) is mounted on a thin plate region (17) that is thinner than a thick plate region (16) having its thickness increased by mounting the circuit part (2) on the base board (4). Thus, the thickness of the whole circuit board device is reduced and the filter element (5) is covered with a sufficiently thick dielectric insulating material so as to prevent deterioration in filter characteristic.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: March 6, 2007
    Assignee: Sony Corporation
    Inventors: Takayuki Hirabayashi, Akihiko Okubora
  • Patent number: 7187256
    Abstract: A novel package includes a substrate including an upper surface ground plane connected to a lower surface ground plane by vias through the substrate, a die located on the upper ground plane and including a die pad, a transmission path including, on the upper surface of the substrate, a bonding pad connected to a first transmission line itself connected to a transition pad, and on the lower surface of the substrate, a second transmission line connected to the transition pad by a via through the substrate. A wire bond extends from the bonding pad to the die pad. A portion of the upper surface ground plane and the lower surface ground plane are connected by vias defining opposing walls on either side of the transmission path for signal isolation.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: March 6, 2007
    Assignee: Hittite Microwave Corporation
    Inventor: Ekrem Oran