Abstract: An interface of a memory sub-system can receive a write command addressed to a first address and a read command addressed to a second address and can receive data corresponding to the write command. The interface can determine whether the first address matches the second address responsive to determining that the first address matches the second address, can drop the read command and the second address, and can provide the data to a host.

Abstract: A computer comprising one or more processors offering vector instructions may implement a direct convolution on a source data set. The source data set may be one-dimensional or multi-dimensional. For a given vector width, w, of the vector instructions, w consecutive data elements of the output data set are computed in parallel using vector instructions. For multi-dimensional data sets, multiple vectors of the output data set are computed for a single load of a set of vectors from the source data set. New vector instructions are disclosed to improve the performance of the convolution and to enable full utilization of the arithmetic logic units within the one or more processors.

Abstract: Techniques and systems for creating and performing analysis on three-dimensional computer models are described. The model creation and analysis may be specified using an un-compiled script that includes a set of instructions. The set of instructions may implement a computer-aided design (CAD) kernel using a bridge layer that includes compiled bridge code. The instructions may be used to create a job set having a group of tasks. Using the job set, a processing queue may be constructed, the processing queue having a subset of common tasks prioritized within the processing queue. Subsets or groups of tasks or instructions may also be executed in parallel using multiple distinct processors or a multi-threaded processor.

Abstract: A pixel driving chip and a driving method therefor, and a display apparatus. The pixel driving chip includes a data input circuit, a time selection circuit, and a current control circuit; the data input circuit is configured to receive display data, and partition the display data to obtain a data partition to which the display data belongs in M data partitions that are obtained on the basis of a display data range; the time selection circuit is configured to determine, according to the data partition to which the display data belongs, an output time length corresponding to the display data, and within the output time length, output the display data to the current control circuit; the current control circuit is configured to determine, according to the display data, a driving current flowing through a light emitting element corresponding to the display data.

Abstract: Example techniques are described for generating graphics content by obtaining texture operation instructions corresponding to a texture operation, in response to determining at least one of insufficient general purpose register space is available for the texture operation or insufficient wave slots are available for the texture operation, generating an indication that the texture operation corresponds to a deferred wave, executing the texture operation, sending, to a texture processor, initial texture sample instructions corresponding to the texture operation that was executed, and receiving texture mapped data corresponding to the initial texture sample instructions.

Abstract: In one example, an apparatus for capturing an image includes a pixel array and a row jump register. The row jump register exposes a plurality of rows of the pixel array to the image. The rows are exposed in a non-sequential, patterned order based on a jump distance. The rows of the pixel array are read into a frame buffer memory in the non-sequential, patterned order based on the jump distance.

Abstract: The present disclosure relates to a shift register unit and driving method thereof, a gate electrode driving circuit and a display apparatus, in the field of display technology. The shift register unit comprises an input circuit, an output circuit, a control circuit, a reset circuit, and a switch circuit. The switch circuit may control the second and third nodes to be disconnected when the electric potential of the input signal is the first electric potential (i.e., the effective electric potential). Thus, the following case can be avoided: when the second clock signal and the input signal have the first electric potential respectively, the second power source signal written into the third node by the second power source signal end is transmitted to the second node. As a result, the stability of the electric potential of the second node can be ensured.

Abstract: A display device is provided which is capable of preventing a malfunction and carrying out a common reverse drive without increasing electric power consumption. The display driver (a) supplies a voltage of a common electrode, whose a polarity is determined in accordance with (i) an oscillation circuit output signal (OCOUT) which is transmitted via a first wire different from a second wire used during a serial transmission and (ii) a SCS signal and (b) controls a reverse timing of the polarity of the voltage of the common electrode in accordance with the oscillation circuit output signal (OCOUT) and the SCS signal.

Abstract: One embodiment of the present invention sets forth a technique for image rendering with per-frame buffer scene segmentation. A user specifies how geometric objects, light sources, and various types of rendering operations in a graphics scene are associated. A segmentation API translates scene data into specific instructions used by a rendering engine that cause the rendering engine to generate a set of scene segments within a set of user specified frame buffers. The scene segments may be composited together using a variable contribution value for each scene segment to generate a final image.

Abstract: A shift register includes a plurality of shift register circuits. Each of the shift register circuits includes a first switch, an input circuit, a pull-down circuit and a ripple reduction circuit. The first switch is used to output a scanning signal of the shift register circuit according to voltage levels of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a scanning signal of a previous shift register circuit. The pull-down circuit is used to pull down the voltage levels of the node and the scanning signal of the shift register circuit according to a scanning signal of a following shift register circuit. The ripple reduction circuit is used to suppress ripples on the voltage levels of the node and the scanning signal caused by the coupling effect of the clock signal.

Abstract: In general overview, the present disclosure is directed to a system and method for selectively displaying a frame of an application user interface on a mobile computing device. A user interface analyzer on a mobile computing device analyzes a user interface for an application executing on a remote server. The user interface analyzer identifies frames in the user interface, the positions of the frames, relationships between frames, and horizontal and vertical panning offsets to move between adjacent frames. The mobile computing device receives a user input requesting the display of an adjacent frame. Based on the information the user interface analyzer obtained, the mobile computing device displays an adjacent frame of the user interface.

Abstract: A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus.

Abstract: A system and method for configuring graphics register data and a recording medium are applied in a mobile device to store graphics operation data for displaying a picture. The system includes a plurality of register modules and an operation module. The operation module obtains unstored data from the graphics operation data, judges whether a register module already stored with data and having a configuration space sufficient for configuring the unstored data exists among all the plurality of register modules, so as to determine whether to store the unstored data into the register module already stored with data or a register module without storing-data, and when no register module without storing data exists and the configuration space of each register module already stored with data is insufficient for storing the unstored data, divides and stores the unstored data into a part of the plurality of register modules already stored with data.

Abstract: A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.

Abstract: A state display device capable of reducing a processing load applied to a microcomputer by performing part of a GUI process by hardware and a display method of the state display device are obtained. A rendering processing device starts a process in response to a rendering request stored in a rendering request region when a starting command is stored in a start/end instruction register. When a rendering request specified by an instruction address is a rendering termination request, the rendering processing means terminates the process performed in response to the rendering request, stores a termination factor in an interruption factor register, and issues an interruption to a central processing device.

Abstract: Techniques are disclosed relating to arbitration of requests to access a register file. In one embodiment, an apparatus includes a write queue and a register file that includes multiple entries. In one embodiment, the apparatus is configured to select a request from a plurality of requests based on a plurality of request characteristics, and write data from the accepted request into a write queue. In one embodiment, the request characteristics include: whether a request is a last request from an agent for a given register file entry and whether the request finishes a previous request. In one embodiment, a final arbiter is configured to select among requests from the write queue, a read queue, and multiple execution pipelines to access banks of the register file in a given cycle.

Abstract: A device for processing graphics data includes a plurality of graphics processing units. Each graphics processing unit may correspond to a virtualized operating system. Each graphics processing unit may include a configuration register indicating a 3D class code and a command register indicating that I/O cycle decoding is disabled. The device may be configured to transmit a configuration register value to a virtualized operating system indicating a VGA-compatible class code. The device may be configured to transmit a command register value to the virtualized operating system that indicates that I/O cycle decoding is enabled. In this manner, legacy bus architecture of the device may not limit the number of graphics processing units deployed in the device.

Abstract: A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or more clock signals each having a different phase, and a setting signal which determines shift direction; and a selection circuit (switch array) which can select at least one clock signal from the three or more clock signals in accordance with the setting signal; wherein the unit registers are put in a reset state by one clock signal selected by the selection circuit, corresponding to each of the unit registers

Abstract: In general, aspects of this disclosure describe a compiler for allocation of physical registers for storing constituent scalar values of a non-scalar value. In some example, the compiler, executing on a processor, may receive an instruction for operation on a non-scalar value. The compiler may divide the instruction into a plurality of instructions for operation on constituent scalar values of the non-scalar value. The compiler may allocate a plurality of physical registers to store the constituent scalar values.

Abstract: One embodiment of the present invention sets forth a technique for storing only the enabled components for each enabled vector and writing only enabled components to one or more specified render targets. A shader program header (SPH) file provides per-component mask bits for each render target. Each enabled mask bit indicates that the pixel shader generates the corresponding component as an output to the raster operations unit. In the hardware, the per-component mask bits are combined with the applications programming interface (API)-level per-component write masks to determine the components that are updated by the shader program. The combined mask is used as the write enable bits for components in one or more render targets. One advantage of the combined mask is that the components that are not updated are not forwarded from the pixel shader to the ROP, thereby saving bandwidth between those processing units.

Abstract: A bi-directional shift register circuit includes multiple stages of shift registers for generating multiple gate driving signals. At least one shift register includes an input stage circuit, an output stage circuit, a first and a second transistor. The input stage circuit is coupled to a first and a second signal input terminal. The output stage circuit receives a first clock signal and generating a corresponding gate driving signal. The first transistor includes a first terminal coupled to a first node, a second terminal coupled to a second node and a third terminal coupled to a high operation voltage. The second transistor includes a first terminal coupled to the second node, a second terminal coupled to the first node and a third terminal coupled to the high operation voltage. The first transistor charges the first node and the second transistor discharges the second node.

Abstract: A control method for bi-stable displaying is provided, using queues for storing coordinates to achieve pipeline parallel processing on display data, thereby increasing display speed. In a preceding stage of the display process, because a plurality of queues may be used for temporarily storing part of the display data which is then reconstructed into complete display data to update a current frame buffer, comparing pixel data and generating driving data can be simultaneously preformed upon a plurality of line segments. Moreover, in a succeeding stage of the display process, a similar process may be performed to update a previous frame buffer, so access time can be reduced and errors caused by overlapping image blocks can also be avoided. Furthermore, the method may be also applied to a timing controller and a bi-stable display device.

Abstract: Frequently accessed state data used in a multithreaded graphics processing architecture is cached within a vector register file of a processing unit to optimize accesses to the state data and minimize memory bus utilization associated therewith. A processing unit may include a fixed point execution unit as well as a vector floating point execution unit, and a vector register file utilized by the vector floating point execution unit may be used to cache state data used by the fixed point execution unit and transferred as needed into the general purpose registers accessible by the fixed point execution unit, thereby reducing the need to repeatedly retrieve and write back the state data from and to an L1 or lower level cache accessed by the fixed point execution unit.

Abstract: A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A ?th stage of unit register circuit (38) has two set terminals connected to respective outputs of (??1)th and (?+1)th stages and two reset terminals connected to respective outputs of (?+2)th and (??2)th stages. The unit register circuit (38) sets, when a pulse is input to any one of the set terminals, a reference point N1 to an H level, and, when a pulse is input to any one of the reset terminals, N1 to an L level. The order of phase change of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched.

Abstract: A plurality of cascaded unit register circuits which comprises a bidirectional shift register include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse Pk in synchronization with a clock signal with a reference point N1 being at H level. The main stages include terminals NSF and NSB for setting N1 to H to which Pk?1 and Pk+1 are input, respectively, and terminals NRB and NRF for setting N1 to L level to which Pk?2 and Pk+2 are input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.

Abstract: An example of a controller circuit may include a policy module to generate a power reduction policy output based on a processor power state input. The power reduction policy output may also be generated based on a graphics render engine idleness input. The circuit can also include a clock masking cell to apply a clock masking configuration to a graphics render clock trunk based on the power reduction policy output.

Abstract: A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.

Abstract: A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A plurality of hardware accelerators are coupled to a selection unit. A register is coupled to the selection unit and the plurality of processing elements. In one embodiment, the register includes a plurality of general purpose registers (GPR), which are accessible by the plurality of processing elements, as well as the plurality of hardware accelerators. In one embodiment, at least one of the GPRs includes a bit to enable a processing element to enable access a selected hardware accelerator via the selection unit.

Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.

Abstract: Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.

Abstract: An image display apparatus is coupled to a nonvolatile memory section, and includes an image processing part configured to display an image on a display device, an initial setting circuit, and a control register configured to control respective parts in the image display apparatus. At power-on or start-up of the image display apparatus, the initial setting circuit reads initialization data from the nonvolatile memory section and sets communication mode for communicating with the nonvolatile memory section to the control register. The communication mode is specified by the initialization data. After the initial setting circuit sets the communication mode to the control register, the image processing part reads image data from the nonvolatile memory section by using the communication mode set in the control register and displays an initial image relating to the image data on the display device.

Abstract: An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.

Abstract: In a shift register and an LCD having the same, the shift register includes plural stages having odd stages for receiving a first clock signal and a first control signal and even stages for receiving a second clock signal and a second control signal. Each of the plural stages includes a pull-up section for providing one of first and second clock signals to an output terminal, a pull-down section for providing a first power voltage to the output terminal, a pull-up driving section for turning on/off the pull-up section in response to an output signal of a front stage and turning off the pull-up section in response to the first and second control signals, a first pull-down driving section for outputting a third control signal, and a second pull-down driving section for turning off the pull-down section in response to the input signal and turning on the pull-down section in response to the third control signal.

Abstract: A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register configuration value and address information, and selects a transmission destination to which the register configuration value information is to be sent, from FIFOs 108 and 109 based on the address information and sends the register configuration value information to the selected destination. The FIFO 108 or 109 temporarily stores the register configuration value information sent from the FIFO selector 103, and reads-out and outputs the register configuration value information in predetermined timing.

Abstract: A system and method for configuring graphics register data and a recording medium are applied in a mobile device to store graphics operation data for displaying a picture. The system includes a plurality of register modules and an operation module. The operation module obtains unstored data from the graphics operation data, judges whether a register module already configured with data and having a configuration space sufficient for configuring the unstored data exists among all the register modules, so as to determine whether to store the unstored data into the register module already configured with data or a register module not configured with data, and when no register module not configured with data exists and the configuration space of each register module already configured with data is insufficient for storing the unstored data, divides and stores the unstored data into a part of the register modules already configured with data.

Abstract: A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.

Abstract: The present disclosure includes system and method of mapping shader variables into physical registers. In an embodiment, a graphics processing unit (GPU) and a memory coupled to the GPU are disclosed. The memory includes a processor readable data file that has a register file portion. The register file portion has a rectangular structure including a plurality of data items. At least two of the plurality of data items corresponding to data elements of a shader program. The data elements have different data storage types.

Abstract: Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.

Abstract: A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.

Abstract: An image forming apparatus including: a video memory; a load management unit that loads page data on a print image into the video memory page by page; a print engine that performs printing using the page data stored in the video memory; and a main management unit that, when printing of a page is completed as part of an electronic sort process, causes the video memory to retain the page data if there is a subsequent page to be printed using the same page data as that on the page, and deletes the page data from the video memory if there is no subsequent page to be printed using the same page data as that on the page.

Abstract: A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.

Abstract: An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.

Abstract: An electronic device including an array of addressable registers storing data. An input register connected to the array stores an input command parameter (e.g an opcode of a command) and its associated operands in one or more input registers connected to the addressable register array. A single instance of a command accesses the at least one register of the array. Based on the input command parameter, the command for all of the address operands: reads a datum of the data previously stored in at least one register, updates the datum thereby producing an updated datum, and writes the updated datum into at least one register. The command has multiple address operands referencing the one or more registers and supports two or more of the address operands being identical. The device includes logic circuitry which provides a logical output signal to the processing circuitry indicating which, if any, of the address operands are identical.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: Message sends may be implemented in a graphics pipeline using biased graph coloring. Registers may be allocated by shaders for message sends using biased graph coloring.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by the program instructions are allocated for processing in the shader program. The registers may be remapped for more efficient use of the register storage space.

Abstract: A display device includes: a display unit in which pixels including memories are arranged; a memory unit holding data; and a control unit rewriting the contents held by memories concerning pixels belonging to a partial area of the display unit based on data held by the memory unit in accordance with instructions given from the outside.

Abstract: A graphics engine and related method of operation are disclosed in which a pixel distributor distributes pixel data across a plurality of pixel shaders using a first approach when the presence of one or more rendering features is indicated, else using a second approach different from the first approach.