Abstract: A bit block transfer (Bitblt) circuit includes a read register, a write register, a bit shifting circuit and an overflowing register. The read register stores decomposition data including original data. The bit shifting circuit shifts the decomposition data in the read register to the write register and shifts bits of the decomposition data in the write register such that an initial bit of the original data of the decomposition data is situated apart from an initial address of the write register by a bit-shifting amount. The overflowing register coupled to the write register stores overflowing data of the original data overflowing from a memory length of the write register when the bits of the decomposition data in the write register are being shifted. The write register outputs and writes the decomposition data therein to a memory cell of a first memory.

Abstract: A system and method are described that manage incremental state updates in such a way that multiple threads within a processor can each operate, in effect, on their own set of state data. The system and method are applicable to any processor in which multiple threads require access to sets of state information which differ from one another by a relatively small number of state changes.

Abstract: A digital display with image data storage memory that minimizes the impact of defective memory cells by remapping stored image data. Memory defects may be detected by automatic or visual testing. The digital display may perform a mapping process such that image data placed in the location of the defective storage cells is based on the significance of the data, both by bit and by color. The mapping process may operate on addressed rows of memory cells of the digital display.

Abstract: A Video Card with standard video output and a Network Ethernet port output of compressed digital video output that represents the image seen by a monitored computer user. A custom video card software driver is used to set up the dual display video controller configurations that assist with the functioning of the digital video compression that is a hardware combination of Run-Length, Huffman encoding and MPEG located on the same monitored user video card. One of the video controller's I2C ports is used to control the compression video circuits and as the pathway for the custom Ethernet communications, thus avoiding an additional costly connection to the user's main computer bus. The first video stream from the dual head video controller chip is used for regular viewing by the local PC (personal computer) user.

Abstract: A system and method for representing multiple prefetchable memory resources, such as frame buffers coupled to graphics devices, as a unified prefetchable memory space for access by a software application. A graphics surface may be processed by multiple graphics devices, with portions of the surface residing in separate frame buffers, each frame buffer coupled to one of the multiple graphics devices. One or more redirection regions may be specified within the unified prefetchable memory space. Accesses within a redirection region are transmitted to a prefetchable memory of a single graphics device. Accesses within the unified prefetchable memory space, but outside of any redirection region may be broadcast to all of the prefetchable memories of the multiple graphics devices.

Abstract: Methods and systems for mosaic mode display of video are disclosed. Aspects of one method may include generating video data for a plurality of video windows using a single video feeder module comprising a single video scaler and a single video capture module. The video data for the video windows may be generated in a single frame time. Register DMA may be used to transfer register update data (RUD) to a plurality of registers to configure video processing for generating video data for a video window. The plurality of RUDs may be generated in response to a single interrupt to a processor, and may be configured as a linked list or stored sequentially in memory. The configuring may occur prior to generating video data for the corresponding video window. Video processing for a subsequent video window may be configured automatically after generating video data for the present video window.

Abstract: A display controller unit for controlling a display on a display panel comprises a first set of registers to hold data to be displayed and a second set of registers loadable from the first set of registers. A set of multiplexers has first data inputs coupled to the first set of registers, second data inputs coupled to the second set of registers, and select inputs. Logic circuitry is coupled to the output of the set of multiplexers and to the control inputs of the multiplexers, the control circuitry providing select information to the set of multiplexers and providing waveforms to the display panel to selectively display data from the first set of registers and the second set of registers in accordance with the select information.

Abstract: A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A plurality of hardware accelerators are coupled to a selection unit. A register is coupled to the selection unit and the plurality of processing elements. In one embodiment, the register includes a plurality of general purpose registers (GPR), which are accessible by the plurality of processing elements, as well as the plurality of hardware accelerators. In one embodiment, at least one of the GPRs includes a bit to enable a processing element to enable access a selected hardware accelerator via the selection unit.

Abstract: A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register configuration value and address information, and selects a transmission destination to which the register configuration value information is to be sent, from FIFOs 108 and 109 based on the address information and sends the register configuration value information to the selected destination. The FIFO 108 or 109 temporarily stores the register configuration value information sent from the FIFO selector 103, and reads-out and outputs the register configuration value information in predetermined timing.

Abstract: An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by the program instructions are allocated for processing in the shader program. The registers may be remapped for more efficient use of the register storage space.

Abstract: Stochastic dithering may be used to reduce the size of the frame buffer and the complexity of the D/A Converters (DACs) in the drive circuitry that are used in a video display system. Hardware for stochastic dithering can be simplified when pixel data is presented in raster order. The hardware adds algebraic noise to the image to be dithered, and thresholds the result.

Abstract: Techniques are described for processing computerized images with a graphics processing unit (GPU) using a unified vertex cache and shader register file. The techniques include creating a shared shader coupled to the GPU pipeline and a unified vertex cache and shader register file coupled to the shared shader to substantially eliminate data movement within the GPU pipeline. The GPU pipeline sends image geometry information based on an image geometry for an image to the shared shader. The shared shader performs vertex shading to generate vertex coordinates and attributes of vertices in the image. The shared shader then stores the vertex attributes in the unified vertex cache and shader register file, and sends only the vertex coordinates of the vertices back to the GPU pipeline. The GPU pipeline processes the image based on the vertex coordinates, and the shared shader processes the image based on the vertex attributes.

Abstract: A graphic data processing module includes a system interface for receiving image data streams, a shift register connected to the system interface, a timing generator connected to the system interface and the shift register, and a graphic display data random access memory (GDDRAM) connected to the shift register. The timing generator generates a clock signal and inputs the clock signal to the shift register, the shift register is controlled by the clock signal to receive image data streams in a first format from the system interface and convert the data of each pixel in the image data streams into data in a second format using fewer bits than the first format, and the data in the second format is transmitted to the GDDRAM.

Abstract: A correction circuit includes a memory that stores a mobility correction value or a threshold voltage correction value for correcting luminance non-uniformity for every pixel, a memory read-out unit that reads out the mobility correction value or the threshold voltage correction value from the memory, a correlation table that produces a threshold voltage correction value or a mobility correction value from the other one of the mobility correction value and the threshold voltage correction value on the basis of a correlation between mobility and a threshold voltage, a mobility correction unit correcting an input signal for every pixel by using the mobility correction value supplied from the memory read-out unit or the correlation table, and a threshold voltage correction unit correcting the input signal that is corrected at the mobility correction unit, by using the threshold voltage correction value supplied from the memory read-out unit or the correlation table.

Abstract: A memory calibration method and a display apparatus using the memory calibration method are provided. The memory calibration method includes displaying an automatic calibration item, determining whether an automatic calibration command is input through the automatic calibration item, and automatically setting register setting values of the memory if it is determined that the automatic calibration command is input.

Abstract: A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

Abstract: Message sends may be implemented in a graphics pipeline using biased graph coloring. Registers may be allocated by shaders for message sends using biased graph coloring.

Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.

Abstract: The present invention provides for programmable interleaved graphics processing. The invention provides an execution pipeline and a number of registers. Each register holds instructions from a separate program. Instructions from the registers are interleaved in the execution pipeline such that the average latency is one instruction per cycle. This is accomplished even when there is conditional branching and execution latency. When one instruction has a dependency based on execution of a previous instruction, that second instruction is not provided to the execution pipeline until completion of the first instruction. However, in the meantime interleaved instructions from other programs are still being executed while the first instruction of the first program is executing. Thus the pipeline is always full and the processor is always working at peak capacity. The automatic interleaving of instructions permits simplified graphics software routines to be written.

Abstract: An integrated circuit apparatus includes data-line drive circuits, an offset register that stores offset set values corresponding to a plurality of pixels, and correction circuits that perform processing of correcting the offsets on the basis of the offset set values. The offset register stores offset set values for the positive polarity and offset set values for the negative polarity. The data-line drive circuits supply data signals resulting from correction based on the offset set values for the positive polarity in a positive drive period and supply data signals resulting from correction based on the offset set values for the negative polarity in a negative drive period.

Abstract: A new, useful, and non-obvious shader processor architecture having a shader register file that acts both as an internal storage register file for temporarily storing data within the shader processor and as a First-In First-Out (FIFO) buffer for a subsequent module. Some embodiments include automatic, programmable hardware conversion between numeric formats, for example, between floating point data and fixed point data.

Abstract: A memory for a graphics processor is provided. The memory includes a write first-in-first-out (FIFO) region of the memory for receiving pixel data, and a read FIFO region for accessing the pixel data received into the memory through the write FIFO. The memory has a memory controller having write assembly logic for rearranging the pixel data received by the write FIFO for storage in the memory. The write assembly logic is configured to write data representing a first pixel and a second pixel across a plurality of data segments in the memory, where corresponding bit locations for the data representing the first pixel and the data representing the second pixel are contiguous. A graphics controller having the memory and a method for preventing data corruption from being displayed during an underflow are included.

Abstract: Disclosed is as system for reducing memory and computational requirements of graphics operations. The system provides techniques for combining otherwise individual operations to apply filters to images. The combined filter emerging from the combination spares the processor time and the creation of an entire intermediary image. The system further provides for application of these techniques in many contexts including where the operations are fragment programs in for a programmable GPU.

Abstract: A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a branching operation is performed to a second operation. The first operation and the second operation are associated with instructions selected from a predetermined instruction set.

Abstract: An apparatus comprising a buffer circuit, a rotation circuit and a memory. The buffer may be configured to store original image data in one or more sub-matrices. The rotation circuit may be configured to (i) produce rotated data and (ii) store the rotated data in a transposed matrix. The memory may be configured to position the rotated data in the transposed matrix. The transposed matrix comprises final image data rotated by a predetermined angle from the original image data.

Abstract: A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.

Abstract: A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A plurality of hardware accelerators are coupled to a selection unit. A register is coupled to the selection unit and the plurality of processing elements. In one embodiment, the register includes a plurality of general purpose registers (GPR), which are accessible by the plurality of processing elements, as well as the plurality of hardware accelerators. In one embodiment, at least one of the GPRs includes a bit to enable a processing element to enable access a selected hardware accelerator via the selection unit.

Abstract: For detecting line short defects in a display panel, a driving circuit has a plurality of shift registers, a plurality of diode modules, and at least one power supply. Each shift register has an output port for outputting a driving signal sequentially. The diode modules are coupled to the output ports of the shift registers accordingly. The power supply is coupled to the diode modules and forward biases the diode modules to bypass the shift registers during at least a part of a period of detecting line short defects.

Abstract: An integrated circuit (IC) within an IC package, where the IC includes a memory control module and a timing module. The memory control module is configured to control read/write operations of a memory IC via N pins of the IC package, where N is an integer greater than 1. The memory IC is external to the IC package. The timing module is configured to control on/off timing of (N*M) light emitting diodes (LEDs) arranged in N columns and M rows connected to the N pins and M pins of the IC, respectively, where M is an integer greater than 1. The read/write operations utilize the N pins during a first period. The N*M LEDs receive data from the M pins and refresh signals from the N pins during a second period that is different than the first period.

Abstract: A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instruction set may then be loaded into texture processing cores to process texture data consistent with the program.

Abstract: Circuits, methods, and apparatus for registers to store information that may be used by devices in a display system. One example provides control and data registers in a display to store information pertaining to a display system that includes the display. The registers can store attributes of the display, a host device, and a branch device. The information may include an organizationally unique identifier, chip identification, major and minor chip revision information, and firmware major and minor revision information.

Abstract: An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register is coupled to the circuitry. The temporary register can receive a result of the operation. The temporary register allows a result generated using one set of pixel data to be used with a subsequent set of pixel data in the same ALU. The result of the operation can thus be used in a second operation with a second set of pixel data that resides in the pipeline register after the first set of pixel data.

Abstract: The values of each possible component output R, G, and B may be pre-computed for all values of each possible component input Y, U, and V. Each contribution of Y, U, and V input may then be loaded into a register and added in parallel, without overflow, resulting in a computationally inexpensive RGB output from a YUV input. In one embodiment, contributions of Y, U, and V to each of R, G, and B are retrieved from pre-computed tables. The YUV contributions for each value of R, G, and B are packed into three data elements and added together in parallel, resulting in a value for an RGB output.

Abstract: A method and apparatus of operating a shader having multiple texture or shader processing stations. That method includes feeding the output of a texture or shader processing station directly into the input of another texture or shader processing station. Further, only a subset of the processing stations has access to a shader register file.

Abstract: An automatic image correction circuit automatically performs image correction on obtained image data. The automatic image correction circuit includes the following elements. A storage unit stores setting values used for the image correction. A reading portion reads the setting values stored in the storage unit every time the image correction is performed on one frame of the image data. A writing portion writes new setting values into the storage unit at a timing different from a timing at which the reading portion reads the new setting values.

Abstract: The display controller includes a first memory storing image data and being accessed with a sequential access operation having a shorter access time than that of a random access operation, a second memory storing image data and consuming a less power than the first memory does at the time of the access operation and a data transfer control part performing an image data transfer control between the first memory and the second memory. The data transfer control part performs a transfer control to transfer the image data from the first memory to the second memory and transfer the image data written in the second memory after the image processing from the second memory to the first memory. The display controller supplies the image data in the first memory to a display driver.

Abstract: Circuits, methods, and apparatus that provide an L2 cache that services requests out of order. This L2 cache processes requests that are hits without waiting for data corresponding to requests that are misses to be returned from a graphics memory. A first auxiliary memory, referred to as a side pool, is used for holding subsequent requests for data at a specific address while a previous request for data at that address is serviced by a frame buffer interface and graphics memory. This L2 cache may also use a second auxiliary memory, referred to as a take pool, to store requests or pointers to data that is ready to be retrieved from an L2 cache.

Abstract: In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described. The invention is directed to a system for detecting either or both underflow and overflow of a circular buffer capable of holding n entries. The invention is also directed to a method of detecting either or both underflow and overflow of a circular buffer capable of holding n entries.

Abstract: A mail server extracts a character unregistered in a portable terminal from received mail data and affixes the font data of the character concerned to the mail data or inserts a reading tag indicating the reading (pronunciation) of the character concerned into the mail data. The portable terminal additionally registers the font data affixed to the mail data into a font database before the received mail data are displayed. Furthermore, in the display processing of the mail data, a character for which the corresponding font data is unregistered is replaced by a no-font symbol and then displayed. Furthermore, the font of each character constituting the reading tag is read out and this font is displayed subsequently to the no-font symbol.

Abstract: A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or more clock signals each having a different phase, and a setting signal which determines shift direction; and a selection circuit (switch array) which can select at least one clock signal from the three or more clock signals in accordance with the setting signal; wherein the unit registers are put in a reset state by one clock signal selected by the selection circuit, corresponding to each of the unit registers

Abstract: A method and apparatus for hardware-base edge handling in video post-processing. In one embodiment, the method includes the identification of at least one unstored input pixel required to compute an output pixel during output pixel computation. Once identified, a pixel value is generated for the at least one unstored input pixel according to a detected edge handling mode. The generation of the pixel value for the unstored input pixel is performed, in one embodiment, if a position of the unstored input pixel is outside a pixel frame boundary. For example, in one embodiment, for output pixel computation of a scaling operation, the frame boundaries include a left (top) edge and a right (bottom) edge for which input pixels required to compute output pixels at or near the frame boundaries do not exist. Other embodiments are described and claimed.

Abstract: The present disclosure includes system and method of mapping shader variables into physical registers. In an embodiment, a graphics processing unit (GPU) and a memory coupled to the GPU are disclosed. The memory includes a processor readable data file that has a register file portion. The register file portion has a rectangular structure including a plurality of data items. At least two of the plurality of data items corresponding to data elements of a shader program. The data elements have different data storage types.

Abstract: A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register configuration value and address information, and selects a transmission destination to which the register configuration value information is to be sent, from FIFOs 108 and 109 based on the address information and sends the register configuration value information to the selected destination. The FIFO 108 or 109 temporarily stores the register configuration value information sent from the FIFO selector 103, and reads-out and outputs the register configuration value information in predetermined timing.

Abstract: A pixel processing system includes a register-collecting mechanism and a pixel shader. The register-collecting mechanism corrects a first program to a second program. The first program requires a number of first registers. The second program requires a portion of the first registers of the first program. The pixel shader executes the second program. A method for register-collecting mechanism comprises the steps of: scanning the first instructions of the first program; decoding the first instructions to obtaining a plurality of first register numbers of busy register group of the first program; correcting the first program to a second program which only occupies the busy register group. As a result, the idle register group of the first program is available to be reallocated to the additional piled in pixels. Thus the pixel processing system can process more pixels in a batch using a given number of registers, and longer texture load latency can be hidden.

Abstract: A driving integrated circuit (IC) in which operations of registers and a method of programming setting data are improved, a display apparatus including the same, and the method of programming setting data of the display apparatus are provided. The display apparatus includes a panel displaying images, a driving IC disposed to drive the display apparatus and including a register block temporarily storing externally provided data, and a non-volatile memory storing setting data setting up operating conditions of the display apparatus. The register block includes one or more registers disposed in series, stores the data during a first interval of acquiring the setting data, and shifts and outputs data stored in the registers during a second interval for programming the acquired setting data to the non-volatile memory.

Abstract: A graphics controller for animating an overlay is described. The graphics controller includes a host interface for communicating with an external processor and a plurality of registers in communication with the host interface. Logic is configured to periodically change coordinates of an overlay image. The logic responds to values stored in the registers to cause display registers containing the coordinates to be updated every x number of frame refreshes, wherein x is a positive integer.

Abstract: Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port for read operations and for write operations. Either a single read or a single write operation is performed for a given clock via the single port. Moreover, the single-port RAM serially performs N read operations and M write operations associated with a data group using a clock phase of (N+M) clock phases generated from a clock. In another embodiment, a semiconductor device includes the architecture for compact multi-ported register file. The semiconductor device comprises a plurality of register files. Each register file comprises a RAM comprising a port for read operations and for write operations. Moreover, each RAM serially performs N read operations and M write operations associated with one of a plurality of data groups using a corresponding clock phase of (N+M) clock phases generated from a clock.

Abstract: A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.

Abstract: A storage device comprises a plurality of memory blocks each including a plurality of cells in correspondence with a data length of image data consisting of a plurality of pixel data, wherein a specific number of cells are simultaneously selected in order to commonly store a specific number of pixel data, each having a same value, which consecutively emerge in the image data. That is, they are defined between a first address and a second address, which is produced by adding run-length data representing the specific number of the first data consecutively repeated in the image data to the first address. Herein, the specific number of cells are limited within a specific storage unit, consisting of a predetermined number of cells, even though the first address and/or the second address is set outside of the specific storage unit.

Abstract: A host writes graphics commands and data to programmable registers through a command FIFO that is read by a graphics controller or BitBlt engine. Rather than write an address and a data value for each register programmed, the host writes one address, one index, and several data values. The address points to an index register. The index is a mapping index word with several multi-bit mapping fields. Each multi-bit mapping field in the index identifies a register to be programmed with one of the data values. Since N bits are used for each mapping field, the mapping field can select one register in a bank of 2N?1 registers. The registers in the bank can be programmed in any order, and registers can be skipped. Since only one index is stored in the command FIFO for programming several registers, less memory space and fewer bus cycles are required.