Abstract: A flat display unit has a display area including scanning lines, signal lines, switching elements arranged in the vicinity of intersections of the scanning lines and the signal lines, and display pixels connected to corresponding switching elements. The display area is divided into small regions, each of which includes a set of signal lines and signal line driving circuits, each of which is arranged to correspond to one of the small regions, for supplying a picture signal to each set of signal lines in parallel. At least one of the signal line driving circuits has a shift register for transferring a start pulse in a predetermined direction in a predetermined timing, a sampling circuit for sampling an input picture signal to supply the picture signal to a corresponding one of the signal lines on the basis of an output of each stage of the shift register, and a control circuit for inverting the transfer direction of the start pulse.

Abstract: In an image processing system or method, an image element memorizing device memorizes image elements which are image data that are subjects of process. An image element processing state memorizing device memorizes present processing states of the image elements in the image element memorizing device. A detecting device detects, in response to the present processing states, a pointer of one of the image elements that is capable of being processed by the image processing system. A temporary pointer memorizing device memorizes the pointer from the detecting device. A calculating device reads the pointer from the temporary pointer memorizing device to process an image in response to the image element of the pointer which is read.

Abstract: An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.

Abstract: A graphics processor includes a plurality of interrelated functional modules and at least one register associated with each of the functional modules. The plurality of interrelated functional modules are interconnected by a data pipeline for conveying data, and each register is configured to control a function of its associated functional module. The graphics processor also includes a control bus interconnecting each of the registers for conveying instructions, and an instruction controller for decoding instructions for use with the graphics processor. The control bus and the data pipeline are physically separate, and the instruction controller includes a register setting unit adapted to set the registers via the control bus in accordance with a decoded instruction. This enables the function of each of the functional modules to be configured in response to each instruction.

Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.

Abstract: A drive circuit for an electro-optical device, which has a plurality of pairs of shift registers for latching and holding signals representing bits of image data, a D/A converter for performing D/A-conversion on image data latched by the shift register n-bits by n-bits, for generating voltages corresponding to 2N gray scales and for supplying the generated voltages to signal lines, and a switch group for selectively supplying image data latched by one of the shift registers of each of the pairs to the D/A converter. This drive circuit is adapted to repeatedly perform an operation of supplying the D/A converter with image data held by one of the shift registers of each of the pairs during image data is latched by the other shift register. Thus, image data can be inputted thereto at a high speed.

Abstract: A command parser 308 is coupled to an incoming data stream to insert an end of state token at the end of a group of state data 480 and an end of primitive token at the end of a group of primitive data 484 to create a parsed data stream. The parsed state data stream is transmitted to a state controller 420 which loads state data 480 into shadow stages 412. The state controller 420 validates a shadow stage 412 upon receiving an end of state group token. The parsed primitive data 484 are also transmitted to primitive controllers 424. The primitive controllers 424 prevent primitive data from being transmitted into a processing element 464 responsive to receiving an end of primitive_B token. Upon receiving an end of primitive_E token, the primitive controller 424 ascertains whether the first shadow stage 412 has been validated.

Abstract: This invention provides an image display apparatus for displaying data stored in a random access memory (RAM) such as LCD, more specifically a display driver achieving easy and flexible display control such as scroll in a display screen without increasing load on CPU and an image display apparatus including the same.

Abstract: Apparatus for combining an auxiliary image and a main image includes a source of a main image signal and a source of samples representing an auxiliary image signal. A subsampler selectively subsamples the auxiliary image samples in either a quincunx subsampling pattern or a rectangular subsampling pattern. A signal combiner combines the main image signal and a signal representing the subsampled auxiliary image samples to generate a combined image signal. A control circuit generates a freeze control signal for the subsampler which conditions it to take samples in the rectangular subsampling pattern during a freeze frame operation, and in the quincunx sampling pattern otherwise.