Abstract: A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instruction set may then be loaded into texture processing cores to process texture data consistent with the program.

Abstract: An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.

Abstract: A method and an apparatus for determining an up scale factor and a down scale factor according to a scale factor received from a graphics application program interface (API) to scale a graphics data in a graphics processing unit (GPU) are described. The up scale factor and the down scale factor may be precisely stored in the GPU based on a fixed number of bits. An actual scale factor which can be precisely stored in the GPU corresponding to the scale factor may differ from the scale factor with a difference. Graphics commands may be sent to the GPU to scale the graphics data according to the up scale factor and the down scale factor separately.

Abstract: A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

Abstract: an image processing circuit includes a memory storing an image data, which includes a plurality of line data disposed regularly a first module performing a plurality of thinning processes, at each of which a plurality of line data are readout from the memory, and at each of which one line data is processed by using the readout line data, wherein the processed line data is restored in the memory, and wherein the first image processing module outputs a first signal after the thinning processes for a certain times are completed, and a second module, which start its operation in response to the first completion signal, performing a similar image-process performed by the first module, wherein the second image processing module outputs a second completion signal after the thinning processes for the entire image data stored in the memory are completed.

Abstract: Registers 32a-32d hold data for pixels interleaved. An operator 34 reads the pixel data from the registers and processes the pixel data in accordance with a program code. The operator 34 writes the result of the process back to the registers via a cache 38 or writes it in a memory. Program counters PC0-PC3 provided in association with the number of pixels interleaved store the addresses of instructions in a program for the respective pixels. An instruction loader 76 alternately reads from the program counters. An incrementer 74 increments the count of the program counters. The instructions in the program for the pixels are alternately loaded and interleaved on a pixel by pixel basis, before being supplied to the operator 34 and the like.

Abstract: An integrated circuit includes at least two different types of processors. The integrated circuit includes an integrated host and associated scheduler. At least one operation is supported by two or more different types of processors. The scheduler schedules operations on the different types of processors.

Abstract: A system for configuring a chip to perform certain operations is provided. The system includes a CPU. The CPU is in communication with a graphics controller. The graphics controller includes a non-volatile memory for storing a look up table (LUT). The graphics controller further includes a register port. The CPU provides a LUT value to the register port. Look up circuitry, which is in communication with the LUT register port, receives the LUT value from the register port and the LUT circuitry retrieves a corresponding LUT sequence from the LUT. The LUT sequence represents an operation to be performed by the LUT circuitry. The system is further provided with a register block, which can be programmed with values based on the operation to be performed.

Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.

Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.

Abstract: A graphics engine and related method of operation are disclosed in which a pixel distributor distributes pixel data across a plurality of pixel shaders using a first approach when the presence of one or more rendering features is indicated, else using a second approach different from the first approach.

Abstract: A graphics system reduces fetching from memory of color-key pixels when video pixels from a video-overlay window are displayed. A frame buffer is divided into multi-line, multi-pixel blocks that are arranged in block-rows and block-columns. Each block-row has primary and secondary row indicator bits and each block-column has two column indicator bits. When the primary row indicator bit is cleared, all pixels in the block-row are fetched from a frame-buffer memory. When the primary row indicator is set, a secondary row indicator bit selects either first or second column indicator bits for reading. When the selected column indicator bit for a block-column is set, fetching of pixels from the frame buffer memory is skipped. Instead, dummy color-key pixels are generated and inserted into the pixel stream. These dummy pixels match the color key and cause video pixels to be sent to the display. Memory fetching is reduced.

Abstract: A flat display device has a circuit configuration in which a division-driving system and an aspect conversion are integrated with each other, and performs driving appropriate to achieve higher resolution even in driving a display unit. The device comprises a memory circuit which includes n unit memories each storing unit data, a display unit of which the horizontal driver is supplied signals read from the memory circuit and of which the regions divided into a plurality of portions in a horizontal direction is division-driven, and a memory control circuit which divides a digital video signal of one line into n, supplies n pieces of the unit data to the n unit memories, selects each direction of write or read addresses of the n unit memories, and outputs the read addresses so that the arrangement order of the unit data for the adjacent regions is set in an inversion horizontal direction.

Abstract: A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.

Abstract: In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described.

Abstract: A method for generating an intermediate representation of computer program code written for running on a programmable machine comprises: (i) generating a plurality of register objects for holding variable values to be generated by the program code; and (ii) generating a plurality of expression objects representing fixed values and/or relationships between said fixed values and said variable values according to said program code; said objects being organized into a branched tree-like network having all register objects at the lowest basic root or tree-trunk level of the network with no register object feeding into any other register object.

Abstract: Methods and apparatuses for effectively clearing stencil buffers at high speed using surrogate stencil buffer clearing. A hardware register tracks the number of surrogate clears of the stencil buffer since the last actual clear. Bits are reserved in each stencil register for storing the surrogate clear number that cleared other stencil registers the last time the stencil register held an assigned value. A comparison between the contents of the hardware register and the reserved bits in each stencil register determines if each stencil register should be assigned a cleared value. If the numbers do not match the stencil register is assigned a predetermined surrogate clear value. In some applications the number of reserved bits is fixed, while in other applications the number of reserved bits can be set, either by a designer or by software.

Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. The intermediate representation is generated to include a combination of register objects and expression objects. Register objects represent abstract registers that provide a representation of the state of the first programmable machine based on expected effects of the instructions within the first program code, while expression objects represent elements, such as operations or sub-operations, of the instructions in the first program code. In the intermediate representation, a branched tree-like network is formed in which each register object serves as a basic root of the network and references expression objects to which they relate either directly or indirectly through references from other expression objects.

Abstract: An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multiple banks. A collector unit coupled to each bank gathers source operands needed to process a program instruction as the source operands output from one or more banks. The collector unit outputs the source operands to an execution unit when all of the source operands needed to process the program instruction have been gathered.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a Z-buffer memory. The apparatus also includes a set of bits, each of which corresponds to a block of the Z-buffer memory. The apparatus also includes an initialization (init) register. The apparatus also includes control logic coupled to the Z-buffer memory, the set of bits, and the init register. The control logic sets the set of bits upon receipt of an initialization request. The control logic retrieves a Z value from either the init register or from the Z-buffer memory according to the states of the set of bits.

Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.

Abstract: An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by the program instructions are allocated for processing in the shader program. The registers may be remapped for more efficient use of the register storage space.

Abstract: A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.

Abstract: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating.

Abstract: An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register is coupled to the circuitry. The temporary register can receive a result of the operation. The temporary register allows a result generated using one set of pixel data to be used with a subsequent set of pixel data in the same ALU. The result of the operation can thus be used in a second operation with a second set of pixel data that resides in the pipeline register after the first set of pixel data.

Abstract: A video platform architecture provides video processing using parallel vector processing. The video platform architecture includes a plurality of video processing modules, each module including a plurality of processing elements (PEs). Each PE provides parallel vector processing. Specifically, means are provided to read all elements of one or two source vector registers in each PE simultaneously, process the read elements by a set of arithmetic-logical units (ALUs), and write back all results to one of the vector registers, all of which occurs in one PE cycle. To provide such parallel vector processing capabilities, the datapath of each PE is built as a set of identical PE processing slices, each of which includes an integer arithmetic-logical unit (ALU), a vector register bank, and a block register bank. A block/vector register bank holds all I elements of row J in a two-dimensional I×J data blocks for all block/vector registers provided by the architecture.

Abstract: A display driver, electro-optical device and electronic appliance are provided that make unnecessary processing that calculates positions in a RAM where display data is to be written according to a mounting state thereof. A display driver includes a mounting state setting register in which mounting state setting data showing a mounting state of the display driver is set, a RAM that stores display data, a row scanning flag generation circuit that generates a row scanning flag showing a scanning direction of row addresses based on the mounting state setting data, a row address decoder that decodes row addresses in accordance with the scanning direction designated by the row scanning flag, a column address decoder that decodes column addresses, a display address decoder that decodes display addresses, and a driving circuit that drives a display section based on display data read from the RAM in accordance with a decoding result of the display address decoder.

Abstract: In a system including a color liquid crystal panel, a drive control device for driving the panel, and a microprocessor, the drive control device reduces the burden on the microprocessor as well as power consumption. In a liquid crystal display drive control device that incorporates a memory for storing image data displayed on a color liquid crystal panel, reads out the image data sequentially from the memory, generates image signals of the three primary colors for each pixel of the panel, and outputs the image signals from external output terminals, the drive control device includes a transparency arithmetic circuit that applies calculation processing to two image data read out from built-in memory and generates data for a transparent display, supplies display data generated by the transparency arithmetic circuit to a driver, and makes the driver generate and output drive signals to the liquid crystal panel.

Abstract: A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, and a cache for texels for use by the circuitry to generate texture value for any pixel.

Abstract: A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instruction set may then be loaded into texture processing cores to process texture data consistent with the program.

Abstract: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating.

Abstract: Disclosed is an image signal processor for use in an image processing system. The image signal processor includes a local memory to store data and a memory command handler having a plurality of memory address generators. Each memory address generator generates a memory address to the local memory and interprets a command to perform an operation on the data of the local memory located at the memory address to aid in image processing tasks.

Abstract: A method and apparatus for optimizing processing of graphics data. An equation for use in processing graphics data is simplified by identifying variables in the equation that remain constant over a set of repeated operations. This simplified equation is implemented in a processing unit containing logic units, wherein the logic units are used to perform a graphics operation in which a set of constants is required for the graphics operation. A first set of connections is present in which these connections connect the logic units to each other, wherein the first set of connections are used to configure the plurality of logic units to determine the set of constants. A second set of connections connecting the logic units are present. This set of connections is used to configure the logic units to perform the graphics operation in which the graphics operation using the constants determined through the first set of connections.

Abstract: An input section inputs vertex data from a host CPU or a geometry process section to a rendering main process section. The rendering main process section performs a rendering process in accordance with the vertex data inputted into the input section. Therefore, the host CPU can directly write the vertex data, which does not require a geometry process, to a rendering process apparatus and a processing speed of an overall graphics system can be thereby improved.

Abstract: In a shift register and an LCD having the same, the shift register includes stages having odd stages for receiving a first clock signal and even stages for receiving a second clock signal and all stages receive a control signal. Each of the stages includes a pull-up section for providing one of first and second clock signals to an output terminal, a pull-down section for providing a first power voltage to the output terminal, a pull-up driving section for turning on/off the pull-up section in response to the control signal, a first pull-down driving section for outputting a second control signal, and a second pull-down driving section for turning off the pull-down section in response to the input signal and turning on the pull-down section in response to the second control signal.

Abstract: A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

Abstract: A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a branching operation is performed to a second operation. The first operation and the second operation are associated with instructions selected from a predetermined instruction set.

Abstract: The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.

Abstract: A system and method for accelerating 2D graphics in a computer system is disclosed, which has an graphic chip to perform graphic commands, each graphic command having an operation of a source pixel, a pattern and a destination pixel; and a 2D graphic device driver to set a command register of the graphic chip such that the graphic chip performs a graphic command. When the source pixel and the pattern of the graphic command received by the 2D graphic device driver are both colored, a copy procedure is performed to copy memory corresponding to the source pixel or the pattern and convert corresponding color for display. In addition, the 2D graphic device driver sets the command register of the graphic chip to perform a graphic command operation according to the source pixel or the pattern copied, the remaining one not copied and the destination pixel.

Abstract: A low power-consumption active matrix display device including gate lines, drain lines, and pixel electrodes, which are arranged at intersections between the gate lines and the drain lines. A drain line driver is connected to the drain lines to select a drain line and provide the selected drain line with an image signal. A gate line driver is connected to the gate lines to select a predetermined gate line and provide the selected gate line with a gate signal. Level shifters are connected to the drain line driver to operate in a time-dividing manner. Each level shifter supplies the drain line driver with a boosted voltage.

Abstract: A system and method for processing YCbCr video data stored in a paged memory with reduced page breaks. A method is disclosed for retrieving YCbCr planar video data in 4:2:0 format from paged memory. A page of the paged memory containing Y data is accessed; Y data corresponding to M pixels of video data is then retrieved, where M is a value greater than or equal to two. The retrieved Y data is then stored in a shift register. Similar steps are taken to access, retrieve and store Cb and Cr data. Within the shift register, the Y, Cb, and Cr data is stored as sets of planar video data. The Y, Cb, and Cr data is retrieved from the shift register as a series of pixel data for generating pixels on a video display unit.

Abstract: A method and apparatus for graphics processing using state and shader management includes at least one state and shader cache coupled to a compiler for compiling a hardware state and shader vector from an abstract state vector. Also included is an abstract state vector register containing the abstract state vector that is provided to the state and shader cache and the compiler. The state and shader cache receives the abstract state vector and determines whether a cache entry for that abstract state vector already exists. If the cache entry exists, the hardware state and shader vector is provided to hardware. If the entry does not exist, the state and shader cache provides a miss signal to the compiler, whereupon the compiler compiles the abstract state vector and generates a hardware state and shader vector. Thereupon the hardware state and shader vector is provided to the hardware.

Abstract: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating.

Abstract: An apparatus comprises two or more image processing units and a main merger unit. Each image processing unit comprises four information processing units and a sub merger unit for merging data output from the four information processing units. The main merger unit merges data output from multiple sub merger units. Data output from the information processing units are stored in parallel in a register on a unit length basis for serial transmission. Auxiliary data is added for identifying data that have been altered or modified. The serial data, with the auxiliary data added thereto, are output to the main merger unit.

Abstract: A method of self-programming a graphics processing unit (GPU) includes receiving a blit instruction defining a blit operation and storing a first control value in a control register, which determines the behavior of the GPU, using the blit operation. The blit instruction is read by the GPU from a command buffer asynchronously with the CPU. The blit operation is applied to a second control value to determine the first control value. The second control value can be stored in a memory, such as a second control register or a table of control values accessed by an index value. In one application, the second control value is a starting memory address for a display buffer, while in another application, second control value is a clip plane distance. The blit operation can include a copy operation, a colorkey operation, a logic operation, and/or a pattern copy operation on the first control value.

Abstract: A system and method are disclosed for a rasterization pipeline with a parallel initialization path that may provide an increased rate of triangle processing. The edge walker, span walker, and sample generator modules of a rasterization pipeline may be modified to enable the next primitive in the sequence of primitives to be initialized, while the current primitive is processed. Consequently, these two processes that were done in series may now be done in parallel. Data transmitted between modules may be separated into initialization data (data the module needs to define a primitive) and primitive data (the processed output of each module). The second path is for additional initialization data, which allows each of these modules to receive the initialization data for the next primitive, while processing the primitive data for the current primitive.

Abstract: A method, graphics system API and digital video system that provide more efficient processor usage and easier application programming. Register data for the hardware can be generated and written to the hardware control registers, recorded as a command list and recalled as a command list. Use of the command lists prevents repetitive calculation of register data and, hence, reduces processor usage and makes application programming easier.

Abstract: A system and method is provided for aligning multi-channel coded data over multiple clock periods. Data is received through a plurality of data channels and stored in a plurality of latches or queues. Data is scanned to determine whether a valid data transition has occurred. Once a valid transition is detected on all of the plurality of data channels, data is substantially simultaneously read out of the latches or queues resulting in synchronized or aligned data being provided at the output.

Abstract: A method for generating a series of digitized control values for an output device to represent a continuous series of source data, comprising the steps of: storing in a single register a first digitized control value and an indication of deviation between that value and the source data; and repeatedly adding an increment to the register to generate a further digitized control value and simultaneously update the indication of deviation.

Abstract: A graphics system and method for panning from one portion of a stored image to another portion of the image includes a frame buffer, one or more display devices, one or more raster parameter registers, and one or more raster parameter updaters. The image is stored in the frame buffer and each display device is configured to display less than the entire image. A panning operation is initiated by requesting an update of one or more of the raster parameter registers during a next blanking period.