Abstract: A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of aMOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of aMOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.

Abstract: An imaging apparatus includes an imaging element with a first pixel for receiving light flux passing through a first partial pupil area in a focusing optical system and a second pixel for receiving the light flux passing through the entire pupil area in a focusing optical system. A signal generating unit of a focus detection signal generates a first signal based on a light-receiving signal of the first pixel and a second signal based on a light-receiving signal of the second pixel. A control unit performs shift processing for the first signal and the second signal in a second focus detection (S200) following a first focus detection of a phase difference type (S100), and then, sums the shift-processed signals to generate a shift summation signal for a plurality of shift amounts. The control unit calculates a contrast evaluation value from the magnitude of the generated shift summation signal and acquires a defocus amount to control the focus adjustment operation of the focusing optical system.

Abstract: A solid-state imaging device of a three-transistor pixel configuration having no selection transistor has a problem of a non-selection hot carrier white point, which is specific to this apparatus. A bias current during a non-reading period of pixels is made to flow to a pixel associated with an immediately previous selection pixel, for example, the immediately previous selection pixel itself. As a result, dark current only for one line occurs in each pixel, and the dark current for one line itself can be reduced markedly. Consequently, defective pixels due to non-selection hot carrier white points can be virtually eliminated.

Abstract: A column readout amplifier and imaging array using the same method are disclosed. The column readout amplifier includes a signal amplifier having an amplifier signal output, a first filter capacitor, a buffer amplifier having a buffer amplifier input and a buffer amplifier output, and a switching network. The switching network connects the amplifier signal output to the buffer amplifier input and the buffer amplifier output to the first filter capacitor during a first time period, and connects the amplifier signal output directly to the first filter capacitor during a second time period. The time periods can be of fixed duration or determined by the difference in potential between the input and output of the buffer amplifier. The column readout amplifier can be used in an imaging array to readout columns of pixels.

Abstract: There is a need to provide a solid-state imaging apparatus capable of highly accurately analog-to-digital converting an analog voltage output from a pixel circuit. The solid-state imaging apparatus supplies a counter code to an integral A/D converter. The counter code CD includes 3-phase clock signals and gray signals. The clock signals each have a cycle equal to specified cycle multiplied by 8 and allow phases to shift from each other by specified cycle. The gray signals linearly increase count values at a cycle equal to specified cycle multiplied by 4. The counter code reverses only the logical level of a signal when a count value changes. A count value error can be limited to a minimum.

Abstract: A power system for an organic light emitting diode (OLED) display includes a power supplier and a power source controller. The power supplier respectively supplies a first power source voltage and a second power source voltage to first and second power source voltage application lines. The power source controller calculates a reference power source voltage corresponding to a maximum average grayscale using a distribution for each grayscale of first to third image data, models each voltage drop of the first and second power source voltages for first to third subpixels, and reflects the voltage drop to the reference power source voltage to change the second power source voltage.

Abstract: An image sensor includes first to fourth microlenses. A first height difference between a first valley between the first and second microlenses and tops of the first and second microlenses is larger than a second height difference between a second valley between the third and fourth microlenses and tops of the third and fourth microlens, a first angle formed by a tangent in an outermost portion of the first microlens, which contacts the first valley and a plane perpendicular to the normal is equal to or smaller than a second angle formed by a tangent in an outermost portion of the third microlens, which contacts the second valley and the plane.

Abstract: An apparatus, computer readable medium, and method for auto-focusing, the method including reading out a live-view signal from first group pixels; reading out an auto-focusing detection signal from second group pixels; and auto-focusing using the live-view signal and the auto-focusing detection signal, wherein the first group pixels and the second group pixels do not substantially overlap.

Abstract: A gate driving circuit includes N stages (where N is a natural number greater than or equal to 2). The N stages are cascaded, and each of the N stages has a gate line connected thereto. A first stage group includes k stages of the N stages (where k is a natural number less than N), and the first stage group outputs a first output signal in response to a start signal. A second stage group (including N?k stages) generates a second output signal in response to the first output signal and outputs the second output signal to a corresponding gate line. The first stage group includes a first buffer and a second buffer, each of which receives the start signal. A size of the first buffer is smaller than a size of the second buffer.

Abstract: A unit group which is formed by pixel cell rows L1, L2, L1A, and L2A is divided into groups BG1 and BG2. The defocus amount calculating unit calculates a phase difference of the output signal group of the phase difference detecting pixel cells 51R with respect to the output signal group of the phase difference detecting pixel cells 51L for BG1, calculates a phase difference of the output signal group of the phase difference detecting pixel cells 51L with respect to the output signal group of the phase difference detecting pixel cells 51R for BG2, and calculates a defocus amount based on a difference between the two calculated phase differences. The driving unit performs exposure in the order of the pixel cell rows L1 and L2 for BG1 and performs exposure in the order of the pixel cell rows L2A and L1A for BG2.

Abstract: A solid-state imaging apparatus includes a pixel unit which has a plurality of pixels disposed in a two-dimensional matrix shape, wherein each of the pixels that a photoelectrical conversion element which generates a photoelectrical conversion signal corresponding to an amount of incident light disposed on a first substrate, and which outputs a photoelectrical conversion signal generated by each of the pixels to each row as a pixel signal, and an analog-to-digital converter which is disposed on every one or more columns of the pixel unit and generates a digital signal by digitizing a phase state of a multi-phase clock including clock signals of a plurality of phases different from each other at predetermined fixed intervals according to the pixel signal. Each of first and second circuit configuration units whose circuit scales are determined according to the multi-phase clock is disposed on a different substrate of a first or second substrate.

Abstract: As a reset transistor is turned on, an FD (Floating Diffusion) is reset to VDD and then stores charges transferred from a light receiving element. By a source-follower circuit formed by an amplifying transistor, a selection transistor and a current source, a voltage in accordance with a potential of FD is output to a data line. A second output circuit generates an output voltage VOUT in accordance with the potential of FD at an output node. Output transistors in output circuit are configured to generate a potential difference equivalent to the potential difference between FD and data line caused by the amplifying transistor and selection transistor, between data line and output node.

Abstract: Dark current from a transfer transistor is suppressed and power-supply voltage in a second semiconductor substrate is lowered. A solid-state image pickup device includes a pixel array, a plurality of common output lines receiving signals read out from a plurality of pixels, a transfer scanning unit sequentially driving the plurality of transfer transistors, a signal processing unit processing the signals output to the common signal lines, and a level shift unit making amplitude of a pulse supplied to a gate of the transfer transistor larger than amplitude of a pulse supplied to a gate of a transistor constituting the signal processing unit. The pixel array and the level shift unit are arranged on a first semiconductor substrate, whereas the plurality of common output lines and the signal processing unit are arranged on a second semiconductor substrate.

Abstract: A color imaging element, includes a color filter array, in which the color filter array includes an array pattern of a 3×3 pixel group in which first filters corresponding to a green color and second filters corresponding to red and blue colors are arrayed, and the first filters are placed at a center and 4 corners in the 3×3 pixel group, and the array pattern is repeatedly placed in horizontal and vertical directions, and in a pixel group within a predetermined area of the color imaging element, phase difference detection pixels for acquiring phase difference information are placed in entire components of one direction among components in the horizontal direction and components in the vertical direction in the pixel group.

Abstract: The present invention relates to a data generating system comprising a memory device (302), which comprises memory cells (306, 308) and a cell content access unit (310) arranged to access content in the memory cells and provide corresponding output data, wherein the output data originating from at least one of the memory cells (306) is changeable by means of an external physical effect acting directly on the memory device.

Abstract: Described herein is a pixel readout circuit which provides readout at two sensitivity levels depending on the amount of electrons generated by a pixel photodiode in the circuit. A floating diffusion capacitor operates to store charge up to a saturation value determined by its capacitance and an overflow capacitor is provided in an overflow region for storing charge above the saturation value of the floating diffusion capacitor. Readout at a high sensitivity level is provided when the floating diffusion capacitor is not saturated and readout at a lower sensitivity level is provided when there is saturation and subsequent overflow to the overflow region. Connection of the floating diffusion capacitor to the overflow capacitor shares the charge over the combined capacitance of the two capacitors and provides readout at a lower sensitivity without loss of charge.

Abstract: The invention describes image sensor array pixels with global and rolling shutter capabilities that utilize multiple BCMD transistors for storing and sensing charge for a single photodiode. This configuration improves the Dynamic Range (DR) of the sensor, by allowing sensing different image signals from a single pixel without saturation, a low level signal with long integration time followed by a high level signal with short integration time. Signal processing circuits can process these signals into a single Wide Dynamic Range (WDR) output. Further disclosed are pixels that use multiple-gate BCMD transistors for charge storage and sensing having multiple concentric gates, which allows changing the conversion gain of the BCMD transistors. Variable conversion gain is a useful feature when building WDR sensors since low conversion gain and high well capacity allows detection of high level signals and, at the same time, low level signals with high conversion gain and low noise.

Abstract: There is provided an image pickup apparatus which outputs a digital signal based on a comparison result signal that changes the signal value at Nth (where N is an integer of 1 or higher) among comparison result signals output by a plurality of comparators.

Abstract: An isolation structure and method of forming the same. The isolation structure includes a first isolation structure having including an insulation layer formed in a trench in a substrate and a second isolation structure, formed on the first isolation structure. The second isolation structure includes a first impurity region formed in the substrate, the first impurity region having a first impurity doping concentration, and a second impurity region that is formed around the first impurity region, the second impurity region having a second impurity doping concentration that is greater than the first doping concentration.

Abstract: An audio signal acquired by an audio acquisition unit during a predetermined period from when a drive signal has been output is analyzed, and a noise reduction period is determined based on a specific frequency component included in the audio signal of the predetermined period. The noise generated in the noise reduction period is then reduced from the audio signal acquired by the audio acquisition unit.

Abstract: An electronic device according to one or more embodiments of the invention comprises a plurality of first output lines and a plurality of current to voltage convertors. Current signals from a plurality of signal sources are output to the first output lines. Each of the current to voltage convertors are electrically connected to a corresponding one of the first output lines. The current to voltage convertor includes a first amplification unit. An offset reduction unit in a subsequent stage of the current to voltage convertor is provided for each of the first output lines.

Abstract: An apparatus includes an operational amplifier circuit comprising at least one operational amplifier and a feedback circuit coupled between the output terminal and input terminal of the operational amplifier circuit and configured to apply a feedback gain to an output signal at the output of the first operational amplifier. The apparatus further includes a variable compensation capacitor coupled to the output terminal of the operational amplifier circuit and configured to vary a capacitance thereof responsive to the feedback gain.

Abstract: An image capturing apparatus includes: an image sensor including image sensing pixels that generate a signal for image generation, and focus detection pixels dividing the pupil region of an imaging lens into pupil regions and generating a signal for phase difference detection by photoelectrically converting object images from the pupil regions obtained by the division; a switching unit that switches between an all-pixel readout mode in which signals from all of the multiple pixels are read out and a thinning readout mode in which the signals of the multiple pixels are thinned and read out; and a control unit that, in the case where the mode has been switched by the switching unit to the thinning readout mode, controls the accumulation of charges in imaging rows used for image generation and focus detection rows including the focus detection pixels independent from each other.

Abstract: A ramp signal generation circuit 21 comprises a plurality of unit circuits 221 to 22N, each including a capacitor 26 having one end 26a held at a fixed potential and a current source 27 connected to the other end 26b of the capacitor 26, while the other ends 26b of the capacitors 26 in the plurality of unit circuits 221 to 22N are connected to each other with a wiring member W.

Abstract: An object of the present invention is to provide a photoelectric conversion apparatus which can enhance photo responsibility. A photoelectric conversion apparatus includes: a photoelectric conversion element configured to output a photo current generated by a photoelectric conversion; a detecting unit configured to detect a potential of an output terminal of the photoelectric conversion element; a feedback input unit configured to input a feedback signal based on the potential detected by the detecting unit; a current detecting unit configured to detect the photo current; and a current amplifier unit configured to generate an amplified current based on the photo current detected by the current detecting unit, and to output the amplified current to the feedback input unit, wherein the feedback input unit outputs a current derived by adding the photo current to the amplified current.

Abstract: A photo-electric conversion device comprises a pixel array in which a plurality of pixels are arrayed, each pixel including a photo-electric converter, a floating diffusion portion, a transfer unit which transfers charges generated in the photo-electric converter to the floating diffusion portion, and an output unit which outputs a signal corresponding to a potential of the floating diffusion portion, a signal line which is connected to the plurality of pixels and transmits a signal output from each pixel, a load transistor including a drain connected to the signal line, and a source connected to a first reference potential, and a capacitance including a first electrode connected to a gate of the load transistor, and a second electrode connected to a second reference potential, wherein the signal line is arranged not to overlap the first electrode when viewed from a direction perpendicular to a light-receiving surface of the photo-electric converter.

Abstract: An image sensor includes a pixel array and a plurality of pairs of column lines. The pixel array includes a plurality of unit pixel areas arranged in a plurality of rows and columns. Each of the unit pixel areas includes a readout circuit connected to a corresponding pair of column lines, and first and second photo-electric conversion devices sharing the readout circuit. Each of the unit pixel areas is configured to output a first pixel signal corresponding to a photoelectron generated by the first photo-electric conversion device through the first column line, and to output a second pixel signal corresponding to a photoelectron generated by the second photo-electric conversion device through the second column line.

Abstract: A receiver compensation system and method to operate the receiver compensation system are disclosed. The compensation sensor system includes at least one receiver and at least one control loop. The method to operate the receiver compensation system is characterized in that the receiver is adjusted in its sensitivity by a control signal such that in the case of changes of an input received by the receiver, a control signal of the control loop resets an associated receiver output signal, except for a control error. Further, at least one other signal of the control loop represents or contains a measurement of the change of the input received by the receiver.

Abstract: A method for driving an imaging apparatus, a method for driving an imaging system, an imaging apparatus, and an imaging system are disclosed in which the number of times of operation which generates digital signals based on an offset component of a comparing circuit is fewer than the number of times of operations which generate digital signals based on photoelectric conversion signals output by a plurality of rows of pixels.

Abstract: A test mode activation circuit that includes a clock signal generating module, a resistor-capacitor circuit, a current generating module, an output capacitor and a comparator is provided. The clock signal generating module generates a clock signal to an input node such that the resistor-capacitor circuit electrically connected to the input node receives the clock signal to generate a triggering signal every predetermined time interval. The current generating module generates a charging current to an output node in response to the triggering signal. The output capacitor receives the charging current from the output node such that an output voltage of the output node gradually increases. The comparator receives the output voltage from the output node and a reference voltage, wherein the comparator compares the output voltage and the reference voltage to generate a test mode activation signal when the output voltage is larger than the reference voltage.

Abstract: A single-plate color imaging element, where color filters of the same color are arranged on a predetermined number of vertically and horizontally adjacent photoelectric conversion elements, the color filter array includes a plurality of unit blocks including the color filters arranged on the predetermined number of vertically and horizontally adjacent photoelectric conversion elements, the color filter array includes a basic array pattern including the unit blocks arranged in a square grid shape, one or more first filters are arranged in the horizontal, vertical, upper right, and lower right directions of the color filter array, one or more second filters corresponding to each color of the second color are arranged in the horizontal and vertical directions of the color filter array, and a proportion of the number of pixels of the first color is greater than a proportion of the number of pixels of each color of the second color.

Abstract: An anti-eclipse circuit for an imager is formed from pixel circuitry over the same semiconductor substrate as the imaging pixels. More specifically, two adjacent pixel circuits are modified to form an amplifier. One input of the amplifier is adapted to receive a reset signal from one of the pixel circuits while another input is adapted to be set at a predetermined offset voltage from the output of the amplifier. The amplifier is preferably a unity gain amplifier, so that the output of the amplifier set to a voltage level equal to the predetermined offset from the voltage level of the reset signal. Accordingly, the anti-eclipse circuit outputs a reference voltage at predetermined level from the reset voltage of a pixel and does not need to be calibrated for fabrication related variances in reset voltages.

Abstract: It is an imaging element in which pixels which are photoelectric conversion elements are placed at respective square lattice positions, in which, when, in a predetermined region where pixels of the imaging element are placed, a plurality of pairs are arranged in a first line which is any one line among lines and a second line which is parallel to the first line, each pair having pair pixels which are first and second phase difference detection pixels placed adjacent to each other to detect a phase difference among the pixels of the imaging element, the pairs in the first line are placed to be spaced apart from each other by at least two pixels, and the pairs in the second line are placed at positions, which correspond to positions where the pair pixels in the first line are spaced apart from each other.

Abstract: Disclosed is a method of acquiring physical information that acquires physical information by using a semiconductor device. The semiconductor device includes unit elements, each of which has a detecting unit and a unit signal generating unit. The method includes the steps of: providing an operation current supply unit supplying an operation current such that the unit signal generating unit outputs a unit signal, and a signal processing unit receiving the unit signal output from each of the unit elements forming the semiconductor device and outputting an output unit signal; and when a selective read mode is designated for reading the unit signal from a portion of the respective unit elements, an operation current of the output signal line of the unit signal generating unit not to be read is reduced so as to be smaller than an operation current of the output signal line of the unit signal generating unit to be read.

Abstract: A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N?1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N?1)th conversion stage or a range exceeding the range.

Abstract: A color imaging element comprising: first group pixels; second group pixels at positions shifted half; and color filters which are arrayed on each of the first and second group pixels, wherein the color filter array includes a basic array pattern in which first filters corresponding to a first color and second filters corresponding to a second color whose contribution rates for acquiring a brightness signal are lower than a contribution rate of the first color are arrayed, and is formed by repeatedly arranging the basic array pattern, one or more of the first filters are arranged in horizontal, vertical, diagonal upper right and diagonal lower right directions, one or more of the second filters are arranged in the basic array pattern, and a ratio of a number of pixels of the first color is greater than a ratio of a number of pixels of each color of the second color.

Abstract: This is generally directed to systems and methods for providing shiftable column circuitry for a pixel array of an imaging system. Columns of a pixel array can be switchably coupled (e.g., through multiplexers) to their default column circuitry as well as coupled to one or more instances of a neighboring column's column circuitry. In response to an instance of default column circuitry being identified as defective, its corresponding column may “shift” and choose to couple to the neighboring column circuitry. Similarly, all following columns may also shift and couple to a neighboring column circuitry. In some embodiments, the defective column circuitry can be identified during wafer testing and identifying information (e.g., an address) of the defective column circuitry stored in memory. The identifying information may then be accessed from memory and, during an image signal readout phase, used to suitably shift the columns to avoid the defective column circuitry.

Abstract: There is a problem that in an image sensor including an amplifier in each pixel, when a thin-film semiconductor is used as a transistor constituting the amplifier, voltage continues to be applied between source and gate of the transistor and thereby a threshold voltage value of the transistor varies, resulting in a variation of signal voltage. To solve the problem, a thin-film transistor formed with an oxide semiconductor is used as the transistor constituting the amplifier, and during a period other than a period of outputting an output of the amplifier, source potential of the transistor is controlled to be equal to drain potential thereof.

Abstract: Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to a column line having column readout circuitry. The column readout circuitry on each column line may include signal processing circuitry and a latch circuit. The latch circuit on each column line may be used to selectively enable and disable the signal processing circuitry on that column line. Each latch circuit may be coupled to first and second signal lines for globally enabling and disabling the signal processing circuitry on all of the column lines. Each latch circuit may be coupled to column decoder circuitry. The column decoder circuitry may provide a column-select signal to latch circuits on a chosen subset of column lines that enables the signal processing circuitry on those column lines by setting those latch circuits.

Abstract: Providing for operation of high-speed optical sensor equipment at full data path speeds in conjunction with testing equipment operating at a lower speed is described herein. By way of example, a data stream output from optical sensor equipment to testing equipment can be throttled at a serial interface between such equipment. Throttling can involve subdividing a set of pixel data and outputting a subset of the pixel data in a given readout frame. Consecutive outputs of respective subsets of pixel data are initiated with an offset from the previous readout frame. Accordingly, the optical sensor equipment can be operated at full speeds, simulating realistic operational conditions, while slower testing equipment can be utilized to perform data analytics, heuristics, and other quality tests on various portions of the optical sensor equipment.

Abstract: A solid-state imaging device includes a first chip and a second chip. The first chip includes a pixel array in which a plurality of photodiodes corresponding to each pixel of a captured image is disposed in a two-dimensional array shape. Each photodiode generates a pixel signal corresponding to a signal charge generated by the photoelectric conversion of the photodiode. The first chip is stacked on the second chip that includes a memory storing the pixel signals generated from the first chip, where the memory is located outside a projection region formed by projecting the pixel array and in a thickness direction of the first chip.

Abstract: An image sensor includes a pixel array. The image sensor may include a photoelectric conversion device generating electric charges according to photoelectric conversion in each of a plurality of pixels, a shutter of each of the plurality of pixels controlling movements of the generated electric charges according to a drive signal, a driving line connecting the shutters of all of the plurality of pixels of the pixel array, through which the drive signal is transmitted, and a plurality of driving buffers applying the drive signal to the driving line.

Abstract: An image processing apparatus includes: a target position selecting unit to select a pixel position on an input image, as a target position; a candidate line setting unit to set two or more sets of candidate lines including a pixel with a value, in the vicinity of the target position; a weighted-value calculating unit to calculate a weighted value that corresponds to a degree of expectation that the target position and the pixel position on the candidate line are on the same pattern; a direction classifying unit to selectively determine a set of candidate lines that are close to a direction of a pattern of the target position in accordance with the weighted value of each pixel on the candidate lines; and a first interpolated-value calculating unit to calculate a pixel value of the target position in accordance with the weighted value of each pixel on the candidate lines.

Abstract: An image sensor in which a first chip and a second chip are stacked comprises: a pixel unit; output lines each configured to output a pixel signal from the pixel unit; and an analog-digital converter provided for each of the output lines. The analog-digital converter comprises a plurality of sets of the following configuration: reference signal generation units configured to generate a reference signal, a comparison unit configured to compare a signal level of a pixel signal output to one of the output lines with a signal level of the reference signal, a counter configured to count until the signal level of the pixel signal coincides with the signal level of the reference signal compared by the comparison unit. The pixel unit is arranged in the first chip and the analog-digital converter is arranged in the second chip.

Abstract: An image sensor unit may have a backside-illuminated imager and an image co-processor stacked together. The image co-processor may be mounted in a cavity in a permanent carrier. The permanent carrier may include fluid channels that allow cooling fluid to flow past the image co-process and past the imager, thereby removing excess heat generated by the image sensor unit during operation.

Abstract: A unit pixel of an image sensor includes a photoelectric conversion region, an isolation region, a floating diffusion region and a transfer gate. The photoelectric conversion region is formed in a semiconductor substrate. The isolation region surrounds the photoelectric conversion region, extends substantially vertically with respect to a first surface of the semiconductor substrate, and crosses the incident side of the photoelectric conversion region so as to block leakage light and diffusion carriers. The floating diffusion region is disposed in the semiconductor substrate above the photoelectric conversion region. The transfer gate is disposed adjacent to the photoelectric conversion region and the floating diffusion region, extends substantially vertically with respect to the first surface of the semiconductor substrate, and transmits the photo-charges from the photoelectric conversion region to the floating diffusion region.

Abstract: An image pickup circuit including a plurality of circuit blocks. Each of the plurality of circuit blocks includes a plurality of comparing elements, a single counter, and a plurality of storage units. Each of the comparing elements compares a pixel signal supplied through a vertical signal line connected to vertically aligned pixels in a plurality of pixels arranged in a matrix, and a slope signal whose voltage is changed from an initial voltage at a constant slope. The counter counts an elapsed time since a voltage of the slope signal starts to change from the initial voltage. Each of the storage units stores a count value obtained by the counter in accordance with a comparison result of the comparator, the count value corresponding to an elapsed time until the voltage of the slope signal is changed from the initial voltage to a voltage coinciding with the pixel signal.

Abstract: A solid-state imaging device includes a pixel array section that has at least one pixel with a photoelectric conversion unit and a charge detection unit. A driving section is configured to read out a signal of the pixel, a first portion of said signal being based on signal charge, a second portion of said signal being based on a reset potential. A signal processing section is configured to read out the first portion of the signal as a reference voltage, with the reference voltage being adjusted to cause the first and second portions of the signal to be within an input voltage range.

Abstract: A device, comprising a plurality of pixel arrays. Two or more pixel arrays are stacked in overlapping fashion and rotated. Optionally, one or more of the pixel arrays are shifted with respect to others. As a result, the horizontal and vertical Nyquist spatial sampling frequency limits are increased, thus permitting an increase in image resolution, for example in terms of line pairs that can be resolved, without reducing the pixel size. Certain stacked pixel pattern arrangement can also be read out as Bayer color pattern for processing by traditional Bayer image signal processors.

Abstract: An object of the present invention is to provide a comparator which has an input voltage range larger than the case where a conventional offset cancel technique is used, while reducing an offset voltage. A comparator circuit includes: a comparator having an inverting input terminal, a non-inverting input terminal and an output terminal; a first switch having one terminal connected to the inverting input terminal and having the other terminal connected to the output terminal; a first capacitor which has one end connected with the inverting input terminal; a first signal input terminal which is another end of the first capacitor; and a second signal input terminal which selectively inputs either one of a fixed voltage and a comparing signal into the non-inverting input terminal.