Abstract: In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.

Abstract: A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell having a first circuit to store a bit and a second circuit to decouple the stored bit from a power supply and from a return. The method includes storing a bit in a memory cell by a first circuit and decoupling the stored bit from a power supply and a return by a second circuit. Another memory is provided. The memory includes a memory cell having means for storing a bit by a feedback and means for disabling the feedback.

Abstract: In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate.

Abstract: A tracking circuit for a memory includes a tracking cell. A tracking word line is connected to the tracking cell. A tracking bit line is connected to the tracking cell. A voltage generator is configured to provide a variable tracking cell power supply voltage to the tracking cell based on a control signal.

Abstract: The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor.

Abstract: A circuit includes: a first word line; a second word line; and a memory cell. The memory cell includes: a first pass gate, between a transistor and a first data line (RBL), having a gate coupled to the first word line; the transistor having a drain coupled to the first pass gate, a source coupled to a reference node, and a gate coupled to a data node of the memory cell; and a second pass gate, between the data node and a second data line, having a gate coupled to the second word line. The first word line is configured to turn on the first pass gate. The second word line is configured to turn on the second pass gate after an elapse of a first delay.

Abstract: A semiconductor device includes a fuse block configured to store repair information corresponding to a fail address, and output fuse data in a boot-up operation; a dummy mat formed in a predetermined region of a cell array, and configured to store the fuse data in the boot-up operation; and a repair latch block configured to store the fuse data in the boot-up operation, wherein the fuse data stored in the dummy mat are updated to and stored in the repair latch block in a refresh operation.

Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

Abstract: An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.

Abstract: A static random access memory (SRAM) cell is provided with improved write margin. The SRAM cell includes: a pair of inverters cross coupled to each other and forming two storage nodes; read access switches electrically coupled between a read bit line and the two storage nodes; write access switches electrically coupled between write bit lines and two storage nodes; and supply switches electrically coupled between a supply voltage and the pair of inverters and operable, in response to a signal on at least one of the write bit lines, to selectively connect the supply voltage to at least one of the inverters in the pair of inverters. During a write operation, the supply switches operate to cut off the supply voltage to the inverter in the pair of inverters having a charged state.

Abstract: A memory and a method to operate the memory are provided. The memory includes a plurality of memory cells and a wordline driver configured to output a wordline. The memory cells are coupled to the wordline. A control circuit is configured to supply an operating voltage to the memory cells and to the wordline driver. A voltage-adjustment circuit is configured to adjust the operating voltage supplied to the memory cells during the control circuit supplying the operating voltage to the memory cells and to the wordline driver. The method includes supplying an operating voltage to at least one memory cells and to a wordline coupled to the at least one memory cells and adjusting the operating voltage supplied to the at least one memory cells during the supplying the operating voltage to the at least one memory cells and to the wordline.

Abstract: An 8-transistor SRAM (static random access memory) storage cell provides differential read bit lines that are precharged to a low voltage level for read operations. The 8-transistor storage cell provides separate ports for read and write operations, including differential read bit lines. Prior to each read operation, the differential read bit lines are precharged to the low voltage level. During read operations, one of the two differential read bit lines is pulled high towards a high voltage level while the complementary bit line remains at the low voltage level resulting from the precharge. The difference in voltage between the differential read bit lines is sensed to determine the value stored in each 8-transistor SRAM storage cell and complete the read operation.

Abstract: Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.

Abstract: Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.

Abstract: A mutltiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and second bit lines coupled to the first memory access component, first and second bit lines coupled to the second memory access component, first and second write lines coupled to the first memory access component and first and second write lines coupled to the second memory access component. The multiport memory cell also includes a read/write assist transistor, coupled to load transistors of the data storing component, that during read operations is activated for the duration of the read operation and during write operations is activated to impress the desired voltage level before or after one or more memory access components activated as a part of the write operation are deactivated.

Abstract: A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first NMOS transistor, and a second NMOS transistor. A first high supply voltage and a low supply voltage are coupled to the first inverter. A second high supply voltage and the low supply voltage are coupled to the second inverter. The first NMOS transistor has a gate terminal coupled to a first word line. The first NMOS transistor has a source terminal coupled to the first node. The second NMOS transistor has a gate terminal coupled to a second word line, and the second NMOS transistor has a source terminal coupled to the second node. The first word line provides ON signals to turn on the first NMOS transistor, and the second high supply voltage provides a first boost voltage simultaneously.

Abstract: A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.

Abstract: According to one embodiment, a semiconductor storage device includes a flip-flop circuit configured with two stages of inverters composed of TFETs. The flip-flop circuit includes first and second nodes. A first access transistor composed of a TFET is provided between the first node and a first write word-line. A second access transistor composed of a TFET is provided between the second node and a second write word-line. A MOS transistor which has a gate connected to the first node and responds to a voltage impressed on a read word-line to supply a voltage corresponding to a potential at the first node to a read bit-line is included. The first and second access transistors are configured with TFETs connected in a manner that a drain current flows from the first and second nodes to a write bit-line when turned on.

Abstract: A static memory circuit includes a pull-up transistor, a pull-down transistor, a pass-gate transistor associated with the pull-up and pull-down transistors, and first and second word lines electrically insulated from each other. The pass-gate transistor includes a number of Fins and a gate electrode having a number of first and second gates, each one of the gates is disposed on one of the Fins, the first gates are connected to the first word line, and the second gates are connected to the second word line. During a read operation, one of the first and second word lines is asserted low, so that the beta ratio is greater than or equal to a first predetermined value. During a write operation, one of the first and second word lines is asserted high; so that a gamma ratio is greater than or equal to a second predetermined value.

Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.

Abstract: Defective memory may cause expensive and unnecessary replacements of the memory especially for higher density dynamic random access memory that has ever shrinking topologies. Running memory stress tests in the background for a period of time at set intervals while the operating system is idle may detect and identify memory problems in real-time without requiring a re-boot of the information handling system. The memory defects may be repaired in real-time so as not to cause loss of data by future read or write requests to the identified defective memory.

Abstract: The present inventions are related to systems and methods for storing data, and more particularly to systems and methods for writing data to a storage device.

Abstract: Multi-bit non-volatile random access memory cells are disclosed. A multi-bit non-volatile random access memory cell may include a volatile storage element and a non-volatile storage circuit. The non-volatile storage circuit may include at least one first pass transistor connected to a data true (DT) node of the volatile storage element and at least one second pass transistor connected to a data complement (DC) node of the volatile storage element. The non-volatile storage circuit may also include multiple non-volatile storage elements. Each non-volatile storage element may be configured to be selectively connectable to the DT node of the volatile storage element via the at least one first pass transistor and selectively connectable to the DC node of the volatile storage element via the at least one second pass transistor, allowing the multi-bit non-volatile random access memory cell to store/recall more than one databit per cell.

Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

Abstract: A bit line precharging circuit includes a first switch that connects a bit line to a first power source, a second switch that connects the bit line to a second power source whose voltage value is higher than voltage value of the first power source, and a control circuit including a delay element and configured to bring the second switch into conduction after a delay time by the delay element after bringing the first switch into conduction at the time of precharge of the bit line.

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; a row decoder configured to authorize or deauthorize a write voltage to each word line through the word line driver, wherein the write voltage is selected from an operational write voltage or a first write voltage; and a control line configured to provide an operational write voltage or a first write voltage to each word line authorized by the row decoder, wherein the first write voltage is greater than an operational write voltage.

Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.

Abstract: A method of accessing a semiconductor memory includes operations as follows. A first voltage is received at a first data line, and a second voltage is received at a second data line, during a write operation of the semiconductor memory, in which the first voltage is lower than the second voltage, and a first coupling line is capacitively coupled with the first data line to lower the first voltage at the first data line in the write operation of the semiconductor memory.

Abstract: A device may provide a baseline uplink audio signal and a baseline downlink audio signal to create a double talk communication for a user device. The device may receive an audio signal, transmitted by the user device, based on providing the baseline uplink audio signal and the baseline downlink audio signal. The device may determine a score based on the audio signal. The score may indicate an effectiveness of the user device with regard to processing audio associated with the double talk communication. The device may provide information that identifies the score to indicate the effectiveness of the user device with regard to processing audio associated with the double talk communication.

Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.

Abstract: A system uses both MOS-based and bipolar-based decoding circuitry in an address decoder for MOS-based memory. The system includes a MOS-based memory, which includes an array of a plurality of memory cells configured to store data, and an address decoder including MOS-based circuitry and bipolar logic circuitry. The address decoder is configured to accept a word comprising a plurality of bits and access the array of memory cells using the word.

Abstract: Systems and methods are provided for coordinating the partial reconfiguration of a region of a configurable device (e.g., a SDM/CNoC/LSM system or device) through an interface that coordinates the stopping of the current persona in that region, the resetting of the new current persona, and the starting of the new persona in a manner that does not corrupt the memory of the affected region. The interface further provides signaling that the static region can use to protect itself during the partial reconfiguration, and disallows multiple partial reconfigurations of the same region at the same time.

Abstract: Aspects of the present disclosure generally relate to static random access memory (SRAM), and more specifically, to a low-power, row-oriented memory write assist circuit. The SRAM may generally comprise an array of bit cells arranged in rows and columns, wherein each bit cell in a row is selected for writing via a corresponding wordline for that row and wherein each bit cell in a column is coupled to a corresponding pair of bitlines for supplying complementary data values, and at least one row-oriented write assist circuit configured to temporarily reduce, to a desired voltage level, a voltage on an internal voltage line used to supply power to the bit cells of a row selected for writing.

Abstract: An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.

Abstract: A static random access memory (SRAM) with high efficiency. The SRAM has a first bistable cell, a first bit line, a first complementary bit line, a first word line, and a second word line. The first bistable cell has a first access terminal, a second access terminal, a first access switch and a second access switch. The first access switch is controlled by the first word line to couple the first access terminal to the first bit line. The second access switch is controlled by the second word line to couple the second access terminal to the first complementary bit line.

Abstract: Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation.

Abstract: A static random access memory (SRAM) chip including a plurality of SRAM cells and a plurality of cell current tracking cells. Each of the SRAM cells include a source voltage reference conductor, a first ground reference conductor, two cross-coupled inverters, and two pass-gate devices. Each cell current tracking cell include a first half-cell and a second half-cell. The first half-cell is different from the second half-cell.

Abstract: An image forming apparatus comprises a sensor, a base, a clamping section and a limiting section. The sensor includes a hook having a claw section. The sensor is held on the base. The clamping section and the limiting section are arranged on the base. The claw section is clamped with the clamping section. The limiting section is elastically deformable when the sensor is mounted on the base. When the claw section is clamped with the clamping section, the limiting section faces the hook from the opposite side of the clamping section so as to limit the position of the hook.

Abstract: A cross-coupled circuit provided between first and second bit lines that form a bit line pair includes first to fourth fin transistors of p-channel type. The first transistor has its source connected to a first power supply and its gate connected to the second bit line. The second transistor has its source connected to the first power supply and its gate connected to the first bit line. The third transistor has its source connected to the first transistor's drain and its drain connected to the first bit line. The fourth transistor has its source connected to the second transistor's drain and its drain connected to the second bit line.

Abstract: A circuit buffer for outputting a voltage signal having a magnitude greater than a withstand voltage of any circuit element in the circuit buffer includes a first transistor and a second transistor. The first transistor includes a first terminal and a second terminal electrically connected to an input terminal and an output terminal of the circuit buffer respectively, a third terminal electrically connected to a first power supply terminal, and a fourth terminal electrically connected to the third terminal of the first transistor. The second transistor includes a first terminal and a second terminal electrically connected to the input terminal and the output terminal of the circuit buffer respectively, a third terminal electrically connected to a second power supply terminal, and a fourth terminal electrically connected to the third terminal of the second transistor. Voltages of the first and second power supply terminal are switched between two different levels, respectively.

Abstract: A circuit includes a latch circuit, a buffer transistor having a control terminal coupled to a first output of the latch, a first write transistor having a conduction terminal coupled to the first output and a control terminal coupled to a first write bitline, and a second write transistor having a conduction terminal coupled to a second output of the latch and a control terminal coupled to a second write bitline. A method of operating a memory cell circuit includes providing a first value on first and second write bitlines when a read operation is performed, and when a write operation is performed, providing first and second values on the first and second write bitlines, respectively, when a first storable value is to be stored, and providing the first and second value on the second and first write bitlines, respectively, when a second storable value is to be stored.

Abstract: Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node of the cross-coupled inverter, a read buffer transistor having a drain terminal connected to a bit line for read operation and a gate terminal connected to the pass gate transistor, a write operation transistor connected between the pass gate transistor and a bit line for write operation, and a drive transistor unit which is connected to a local line between the pass gate transistors and the write operation transistor and which provide a voltage to a gate terminal of the read buffer transistor based on a data value stored at the bit-cell.

Abstract: In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the instruction memory to selectively power up the branch prediction unit from a powered-down state when fetched instruction data includes a branch instruction and maintain the branch prediction unit in the powered-down state when the fetched instruction data does not include a branch instruction in order to reduce power consumption of the microprocessor during instruction fetch operations.

Abstract: An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.

Abstract: Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells. Each memory cell may include a pair of programmable resistive devices that may be dynamically programmed to configure the memory cell in a particular logic state.

Abstract: Approaches for providing write-assist boost for a Static Random Access Memory (SRAM) array are provided. A circuit includes a write driver of a Static Random Access Memory (SRAM) array. The circuit also includes a boost circuit that dynamically varies a write-assist boost voltage based on a stability assist setting applied to a wordline of the array.

Abstract: A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns.

Abstract: A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.