Abstract: A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

Abstract: The present invention provides a memory unit (4) comprising: a storage element (6) comprising a pair of back to back inverters (12a, 12b and 14a, 14b) having respective first and second storage access nodes (24, 26); first and second voltage lines (VSS, VDD 16a, 6b) across which said pair of back to back inverters (12a, 12b and 14a, 14b) are connected; a first access transistor (18a), connected to said first storage node (24); a second access transistor (18b), connected to said second storage node (26); a write word line (22) connected to a gate (18g1) on said first access transistor (18a) and a gate (18g2) on said second access transistor (18b); a first bit line (28) operably connected for controlling 10 said node (24); a second bit line (30) operably connected for controlling said node (26); in which there is provided a data dependent conductive path (46) between the first and second bit lines (28, 30).

Abstract: A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: A method is disclosed for writing a magnetic tunnel junction (MTJ) of a magnetic memory array by switching a magnetic orientation associated with the MTJ from anti-parallel to parallel magnetic orientation. One end of the MTJ is coupled to a bit line while the opposite end of the MTJ is coupled to one end of an access transistor. The method includes the steps of applying a gate voltage that is approximately a sum of a first voltage and a second voltage to a gate of the access transistor with the second voltage being less than the first voltage; raising the bit line to the first voltage; and applying the second voltage to the opposite end of the access transistor to program the MTJ while maintaining a voltage difference between the gate and the one end of the access transistor to be less than or equal to the first voltage.

Abstract: At least one method, apparatus and system disclosed involves testing a dual port memory cell in a memory device. A semiconductor wafer is processed for providing a dual port memory device. An inline DC contention margin test is performed for testing a contention margin related to a write operation into a cell of the memory device. A determination is made as to whether the contention margin is within a predetermined range. A responsive action is performed in response to determining that the contention margin is outside the predetermined range.

Abstract: A power management chip and a power management device including the power management chip. The power management chip includes at least one power switch and a driver unit for generating a driving signal for driving the at least one power switch, the driver unit including one or more circuit units formed on a same substrate as the at least one power switch.

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell.

Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

Abstract: Device, system and method of accessing data stored in a memory. For example, a device may include a memory to store a plurality of data items to be accessed by a processor; a cache manager to manage, a cache within the memory, the cache including a plurality of pointer entries, wherein each pointer entry includes an identifier of a respective data item and a pointer to an address of the data item; and a search module to receive from the cache manager an identifier of a requested data item, search the plurality of pointer entries for the identifier of the requested data item and, if a pointer entry is detected to include an identifier of a respective data item that matches the identifier of the requested data item then, provide the cache manager with the pointer from the detected entry. Other embodiments are described and claimed.

Abstract: A storage device with long data retention time is configured to include a first transistor, a second transistor, and a third transistor. The first transistor controls electrical connection between a first wiring and a gate of the second transistor. The second transistor controls electrical connection between a second wiring and a gate of the third transistor. The off-state current of the first transistor is lower than that of the third transistor. The leakage current of the second transistor is lower than that of the third transistor.

Abstract: A discharge circuit includes a first circuit connected between a high-voltage terminal and a connection node, wherein first circuit includes a depletion high voltage NMOS transistor of which a drain connected to the high-voltage terminal, a source connected to the connection node, and a gate receiving a reference voltage, and a second circuit connected between a power supply voltage terminal and the connection node and suitable for discharging the connection node through the power supply voltage terminal when a power-off of a power supply voltage occurs. The discharge circuit may stably perform a discharge operation in the case of sudden power-off.

Abstract: A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM) circuit, in which the F-RAM circuit stores a bit of data from the SRAM circuit during power-out periods, the F-RAM circuit is further coupled to bit-line(s) to output the bit of data stored in the F-RAM circuit when operation power is restored.

Abstract: An object is to reduce standby power in a data processing device, without loss of convenience, in a structure in which a power supply control device includes the data processing device. In a structure of a power supply control device which supplies power to an external device using a main switch, a data processing device is provided in the power supply control device to control the main switch; a sub-switch supplying power to the data processing device is provided; and a volatile memory unit and a nonvolatile memory unit are provided in the data processing device. Further, the sub-switch is off in a period in which data is stored in the nonvolatile memory unit of the data processing device, so that power supply to the data processing device is intermittently stopped.

Abstract: The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (SRAM) cell having a first cell size; and a second SRAM cell having a second cell size greater than the first cell size. The first SRAM cell includes first n-type field effect transistors (nFETs) each having a first gate stack. The second SRAM cell includes second nFETs each having a second gate stack different from the first gate stack.

Abstract: A circuit is disclosed that includes a plurality of voltage control circuits. Each voltage control circuit of the voltage control circuits includes a driver circuit and a switch circuit. The driver circuit is configured to receive a control signal having a series of pulses. The switch circuit is configured to generate a driving voltage when being turned on. The driver circuit alternately turns on and off the switch circuit in accordance with the series of pulses.

Abstract: An integrated circuit device includes a memory cell coupled to a supply voltage line to receive a supply voltage and a voltage control circuit operable to reduce a magnitude of the supply voltage prior to a write cycle to the memory cell. The voltage control circuit includes a first capacitor that is selectively coupled between a supply voltage line and a first reference supply voltage line of the integrated circuit device in anticipation of a write cycle to the memory cell.

Abstract: Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells are disposed in a matrix, each memory cell being connectable to any one of a plurality of bit lines, and a capacitance that suppresses coupling noise among the plurality of bit lines, the capacitance being added to at least one of the plurality of bit lines.

Abstract: A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.

Abstract: A method for manufacturing a digital circuit is described including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.

Abstract: Described herein is a 6T bitcell for dual port SRAM that performs single ended read and single ended write. The bitcell and architecture does not have either a write bitline pair or a read bitline for each bitcell. It has only one read bitline per port per mux. Also presented herein is an 8T bitcell for dual port with single ended read and single ended write. The conventional dual port bitcell is an 8T bitcell which neither has single ended read nor has single ended write. Our bitcell which gives single ended read as well as single ended write has just 6 transistors. This gives area advantage. This bitcell also provides huge advantage in terms of leakage power, dynamic power, and speed. Also presented bitcells and architectures for multiport memories where each additional port, only requires half or one additional transistor based on the chosen architecture as against two transistors in the conventional architectures.

Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.

Abstract: A semiconductor in which the area of a circuit that is unnecessary during normal operation is small is provided. A semiconductor device including a first circuit has a function of storing a start-up routine in the first circuit and executing the start-up routine, a function of operating the first circuit as a buffer memory device after executing the start-up routine, and a function of loading the start-up routine into the first circuit from outside before the semiconductor device is powered off.

Abstract: Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Abstract: A method of designing a semiconductor device is provided. The method includes a step of defining a dummy structure area on the floorplan layout of the semiconductor device. The method also includes a step of adding dummy cells to the dummy structure area. Each dummy cell may be associated with a different data type. The method may improve a design optimization process of dummy cells on the semiconductor device layout by automating the removal process of dummy cells to optimize dummy density. Apart from that, semiconductor devices that are manufactured using the described method, and an apparatus to perform the steps described in the method are also described.

Abstract: A memory includes a first memory cell, a second memory cell, a latch unit, and a switch unit. The latch unit has a true node and a complement node. The switch unit is responsive to a first control signal and a second control signal, and is configured to connect the first memory cell to the true node and to disconnect the second memory cell from the complement node in response to the first control signal and to connect the second memory cell to the complement node and to disconnect the first memory cell from the true node in response to the second control signal. A semiconductor device that includes the memory is also disclosed. A method for testing the memory is also disclosed.

Abstract: A design structure can include elements that, when processed in a semiconductor manufacturing facility, produce an SRAM that includes a first local evaluator coupled to a first global bit line (GBL) and a first set of local bit lines (LBLs). The SRAM can also include a second local evaluator communicatively coupled to the first local evaluator. The second local evaluator is coupled to a second GBL and second set of LBLs. The second GBL is consecutive to the first GBL. The first and second evaluators are to generate signals from the LBLs such that one GBL of a combined first and second GBLs is active at any point in a read or write cycle.

Abstract: A method in a computer-aided design system for generating a functional design model of a static random access memory is described herein. The method comprises generating a functional representation of a first local evaluation logic coupled to a first set of consecutive global bit lines (GBLs) and a first set of local bit lines (LBLs), the first local evaluation logic comprising a plurality of devices. The method further comprises generating a functional representation of a second local evaluation logic communicatively coupled to the first local evaluation logic via the devices; the second local evaluation logic is coupled to a second set of consecutive GBLs and a second set of LBLs. In addition, the second set of consecutive GBLs consecutive to the first set of consecutive GBLs, the first and second evaluation logics to generate signals from the LBLs such that one GBL is to be active at any point in a read or write cycle and the other GBLs are not concurrently active.

Abstract: A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the switch is responsive to an output of the inverter.

Abstract: Systems, methods, and other embodiments associated with improving a static noise margin of memory cells by using charge sharing to under-drive a wordline are described. In one embodiment, a system includes power logic to, in response to a memory request, connect a voltage source with a virtual power network to store an electric charge within the virtual power network based on a voltage from the voltage source. The virtual power network includes a network of interconnects that electrically connect a plurality of driver interconnects. The system includes wordline logic to under-drive a requested wordline of a plurality of wordlines by connecting the requested wordline with the virtual power network to share the electric charge stored in the virtual power network with the requested wordline. The wordline logic under-drives a voltage of the requested wordline to be lower than a source voltage provided by the voltage source.

Abstract: A memory device includes a memory cell electrically connected to a power line and a power supply unit configured to control a voltage level on the power line. The power supply unit receives a control signal corresponding to a write cycle of the memory cell and, responsive to a first state of the control signal, outputs a first voltage level on the power line. Responsive to a second state of the control signal, the power supply unit outputs a second voltage level on the power line, the second voltage level having a magnitude less than a magnitude of the first voltage level.

Abstract: A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and second memory cells in the first area and second area, respectively. The plurality of first and second memory cells are coupled the first signal line, and each has a reference node. A first voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of first memory cells, wherein the first voltage adjustments circuit includes: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal; and a first bias element coupled to the reference nodes of the plurality of first memory cells. A second voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of second memory cells.

Abstract: A first current value flowing through a transistor coupled with a storage node of a memory cell is determined when the transistor is off. A second current value flowing through the transistor is determined when the transistor is in on. A first reference voltage value at a reference node of the memory cell when the transistor is off is higher than a second reference voltage value at the reference node when the transistor is on. Based on the first current value, the second current value, and a relationship between the first current value and the second current value, a number of memory cells to be coupled with a data line associated with the memory cell is determined.

Abstract: An embodiment solution for operating a non-volatile memory of a complementary type is proposed. The non-volatile memory includes a plurality of sectors of memory cells, each memory cell being adapted to take a programmed state or an erased state. Moreover, the memory cells are arranged in locations each formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively.

Abstract: A latch circuit includes a write driving unit configured to output fuse data as boot-up data according to a fuse set select signal in a boot-up operation; and a latch set configured to latch the boot-up data when a latch select signal is activated in the boot-up operation, and output data latched as the latch select signal is activated as a repair column address in a normal operation.

Abstract: A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.

Abstract: A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit. The latch circuit has a function of receiving a pulse signal and a reset signal and outputting a first signal. The delay circuit has a function of receiving the first signal and outputting a second signal. The first signal controls power supply to the arithmetic circuit and the delay circuit. The second signal is obtained by delaying the first signal so as to correspond to a delay in a critical path of the arithmetic circuit. The first output timing generation circuit has a function of receiving a third signal obtained by a logical operation on the first signal and the second signal and outputting the reset signal.

Abstract: The invention relates to a reprogrammable logic device comprising a plurality of elementary patches, each patch comprising: at least one logic block configurable by one or more volatile memory cells storing configuration data; and a memory comprising: a plurality of non-volatile memory cells storing refresh data, each non-volatile memory cell comprising first and second resistance-switching elements, each being programmable so as to have one of a first and of a second resistance value representative of the refresh data; and a read-write circuit adapted for periodically refreshing the configuration data on the basis of the refresh data.

Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element configured to be changed in a resistance value according to a value of data stored therein; a first reference resistance element having a first resistance value; a second reference resistance element having a second resistance value larger than the first resistance value; and a comparison unit configured to receive a voltage corresponding to the resistance value of the resistance variable element through a first input terminal and a second input terminal thereof, a voltage corresponding to the first resistance value of the first reference resistance element through a third input terminal, and a voltage corresponding to the second resistance value of the second reference resistance element through a fourth input terminal, the comparison unit configured to output a result of comparing inputs to the first input terminal and the second input terminal and inputs to the third input terminal and fourth input termi

Abstract: A sense amplifier device for sensing a differential signal produced by a memory cell includes a first n-type metal-oxide-semiconductor field-effect transistor (NMOS) stack having multiple NMOS devices sharing a gate connection connected to a complementary data line; and a second NMOS stack having multiple NMOS devices sharing a gate connection connected to a true data line. At least one of the devices in the first stack has higher gate-to-source and drain-to-source voltages than a gate-to-source and drain-to-source voltages of at least one device in the second stack when the voltage of the complementary data line is higher than the true data line. At least one of the devices in the second stack has a higher gate-to-source and drain-to-source voltages than the gate-to-source and drain-to-source voltages of at least one device in the first stack when the voltage of the true data line is higher than the complementary data line.

Abstract: It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to manufacture a highly reliable wiring board or semiconductor device with high yield. In a wiring board or a semiconductor device having a multilayer wiring structure, a conductive layer having a curved surface is used in connection between conductive layers used for the wirings. The top of a conductive layer in a lower layer exposed by removal of an insulating layer therearound has a curved surface, so that coverage of the conductive layer in the lower layer with a conductive layer in an upper layer stacked thereover can be favorable. A conductive layer is etched using a resist mask having a curved surface, so that a conductive layer having a curved surface is formed.

Abstract: A method of operation of a static random access memory (SRAM) storage element includes programming a value to the SRAM storage element prior to a power-down event. The method further includes, in response to a power-on event at the SRAM storage element after the power-down event, increasing a supply voltage of the SRAM storage element and sensing a state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event. In a particular example, an apparatus includes the SRAM storage element and control circuitry coupled to the SRAM storage element. The control circuitry may be configured to program the value to the SRAM storage element, to increase the supply voltage, and to sense the state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event.

Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

Abstract: The present disclosure provides a memory apparatus including a memory cell array, a plurality of sense amplifiers, at least one first comparing circuit, and a plurality of second comparing circuit. The memory cell array includes a plurality of memory cells. Each of the sense amplifier generates a data signal and an inverted data signal according to a bit line signal and an inverted bit line signal. The first comparing circuits compares the data signals of first and second sense amplifiers with a first tag to generate a first comparing result. The second comparing circuits respectively compare a plurality of second tags with the data signals of the sense amplifiers to respectively generate a plurality of second comparing results.

Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.

Abstract: Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.

Abstract: A static RAM includes: a plurality of memory cells provided at intersections of bit line pairs and word lines; a write driver connected between a high potential power source line and a drive line; a column switch including a first transistor pair which connects one of the plurality of bit line pairs to the write driver; and a boost circuit which boosts the drive line to a negative potential, wherein the boost circuit includes: a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which a boost signal is applied; and a boost control transistor connected between the drive line and a reference potential power source line, the boost signal is applied to a gate of the boost control transistor, and the threshold value of the boost control transistor is lower than the threshold value of the first transistor pair.

Abstract: Handshaking sense amplifier. In accordance with a first embodiment, an electronic circuit includes a sense amplifier configured to differentially sense contents of a memory cell. The circuit also includes a self-timing circuit configured to detect a completion of evaluation by the sense amplifier; and to initiate a subsequent memory operation responsive to the completion. A completion of evaluation may not be aligned with a clock edge.

Abstract: A circuit includes a first data line, a second data line, a reference node, and a memory cell. The memory cell includes a data node, a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor are connected in series between the first data line and the reference node. The first transistor is configured to be turned off when the gate of the first transistor has a voltage level corresponding to the first logical value. The third transistor is between the data node and the second data line. The third transistor is configured to be turned off when a gate of the third transistor has a voltage level corresponding to a second logical value different from the first logical value.