Abstract: An integrated circuit includes a memory array having a plurality of SRAM memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. The plurality of memory cells include a plurality of asymmetric cells, each of the asymmetric cells configured with a strong side including a first inverter having a strong side latch node, and a strong side pass transistor coupled to the strong side latch node, and a weak side including a second inverter cross-coupled with the first inverter having a weak side latch node and a weak side pass transistor coupled to the weak side latch node. Separate ones of the plurality of word lines are coupled to a gate of the strong side pass transistor and a gate of the weak side pass transistor.

Abstract: Provided are a non-volatile memory device and a method of programming the same. The method includes: performing a program operation; performing a program verify read operation; and performing a pass/fail determine operation simultaneously with one of a verify recovery operation and a bit line setup operation, after the performing of the program verify read operation.

Abstract: A one read/two write SRAM circuit of which memory cell size is small, and high-speed operation is possible. The SRAM circuit includes first and second flip-flop circuits which are connected in parallel to a common write word line; a first write control circuit which is connected to said first flip-flop circuit, is conducted by a write control signal supplied to said write word line, and supplies a first write signal to said first flip-flop circuit; and a second write control circuit which is connected to said second flip-flop circuit, is conducted by a write control signal supplied to said write word line, and supplies a second write signal to said second flip-flop circuit.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage for a resistive sense memory (RSM) cell, such as an STRAM cell. A dummy reference cell used to generate a reference voltage to sense a resistive state of an adjacent RSM cell. The dummy reference cell comprises a switching device, a resistive sense element (RSE) programmed to a selected resistive state, and a dummy resistor coupled to the RSE. A magnitude of the reference voltage is set in relation to the selected resistive state of the RSE and the resistance of the dummy resistor.

Abstract: A data processing system comprising a memory array having a plurality of memory cells and read circuitry for reading a logic value stored in one of the plurality of memory cells. The read circuitry is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.

Abstract: Some embodiments of the present invention provide methods of programming memory devices that include an array of vertical channels passing through a stacked plurality of word plates, wherein respective columns of vertical channels are configured to be coupled to respective bit lines. In some method embodiments, potentials of the vertical channels are boosted, followed by selectively applying respective data to vertical channels via the bit lines to thereby selectively change the potentials of the vertical channels according to the data. A program voltage is subsequently applied to a selected word plate to thereby program a plurality of cells.

Abstract: In one embodiment, a memory system is disclosed. The memory system has at least one memory chip having an address and data interface coupled to an internal address and data bus, and a memory controller and interface chip also having a an address and data interface coupled to the address and data interface of the at least one memory chip via an internal address and data bus. The at least one memory chip, the memory controller and interface chip and the internal address and data bus are disposed within a common chip package. The memory controller and interface chip has an external interface configured to be coupled to a standard memory bus via external contacts of the common chip package.

Abstract: A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.

Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.

Abstract: In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.

Abstract: A system for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

Abstract: A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.

Abstract: A nonvolatile memory device is operated by receiving a dual plane read command for simultaneously reading first and second planes, each comprising memory cells, receiving an MSB read address for reading data stored in the memory cells, checking whether an MSB program operation has been performed on each of the first and second planes, and performing the read operation on the first and second planes according to a result of the check and outputting the read data.

Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

Abstract: A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

Abstract: A phase change memory device is presented that includes a phase change resistance cell array and a cache register. The phase change resistance cell array includes a phase change resistor configured to sense crystallization changed depending on currents so as to store data corresponding to resistance change. The cache register is configured to store a plurality of data applied externally depending on a register write command and to simultaneously output the plurality of data to the phase change resistance cell array depending on a cell write command.

Abstract: A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

Abstract: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

Abstract: The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

Abstract: A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location occurs based on the monitored number of read cycles. Selectively pre-write verifying and writing of the received write data may include, for example, writing received write data to the selected memory cell region without pre-write verification responsive to the monitored number of read cycles being greater than a predetermined number of read cycles.

Abstract: The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a write

Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.

Abstract: The present invention provides a method of reading data from a non-volatile memory device including word lines and bit lines that intersect each other and electrically rewritable memory cells that are arranged at intersections of the word lines and the bit lines and that respectively have variable resistive elements nonvolatily storing a resistances as data. The method includes: precharging a selected word line and unselected word lines to a first word line voltage and a selected bit line and unselected bit lines to a first bit line voltage; and reading data from a memory cell connected to the selected word line and the selected bit line by changing the voltage of the selected word line from the first word line voltage to a second word line voltage and changing the voltage of the selected bit line from the first bit line voltage to a second bit line voltage after the precharging.

Abstract: A static random access memory device capable of preventing stability issues during a write operation is provided, in which a memory cell is coupled to a read word line, a write word line, a read bit line, a write bit line and a complementary write bit line, and a multiplexing unit is coupled to the read bit line, the write bit line and the complementary write bit line. The multiplexing unit applies first and second logic voltages representing a logic state stored in the memory cell to the write bit line and the complementary write bit line, respectively, when the memory cell is not selected to be written by an input signal from a data driver and the read word line is activated, in which the first and second logic voltages are opposite to each other.

Abstract: A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.

Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

Abstract: Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.

Abstract: In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell is indexed during a first programming pass with the application of a series of incrementing programming pulses. The first programming pass is followed by verification and one or more subsequent programming passes to trim any short-falls to the respective target states. If a cell fails to verify to its target state, its program index is incremented and allows the cell to be programmed by the next pulse from the last received pulse. The verify and programming pass are repeated until all the cells in the group are verified to their respective target states. No verify operations between pulses are necessary.

Abstract: Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory and is configured to prevent precharge of the respective bank of memory until after execution of buffered write commands issued to the respective bank of memory is completed.

Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.

Abstract: A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and a memory module coupled to the memory controller. In the memory system, the memory controller is coupled to the memory module via at least two independent memory channels. In the memory system, the at least two independent memory channels are coupled to one or more memory hub devices of the memory module.

Abstract: A one read/two write SRAM circuit of which memory cell size is small, and high-speed operation is possible. The SRAM circuit includes first and second flip-flop circuits which are connected in parallel to a common write word line; a first write control circuit which is connected to said first flip-flop circuit, is conducted by a write control signal supplied to said write word line, and supplies a first write signal to said first flip-flop circuit; and a second write control circuit which is connected to said second flip-flop circuit, is conducted by a write control signal supplied to said write word line, and supplies a second write signal to said second flip-flop circuit.

Abstract: A page of non-volatile multi-level storage elements on a word line WLn is sensed in parallel while compensating for perturbations from a neighboring page on an adjacent word line WLn+1. First, the programmed thresholds of storage elements on WLn+1 are sensed in the time domain and encoded as time markers. This is accomplished by a scanning sense voltage increasing with time. The time marker of a storage element indicates the time the storage element starts to conduct or equivalently when the scanning sense voltage has reached the threshold of the storage element. Secondly, the page on WLn is sensed while the same scanning voltage with an offset level is applied to WLn+1 as compensation. In particular, a storage element on WLn will be sensed at a time indicated by the time marker of an adjacent storage element on WLn+1, the time when the offset scanning voltage develops an appropriate compensating bias voltage on WLn+1.

Abstract: A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage. A magnetic field is applied through the magnetic tunnel junction data cell forming a magnetic field modified magnetic tunnel junction data cell. Then a second read current is applied thorough the magnetic field modified magnetic tunnel junction data cell forming a second bit line read voltage and the bit line read voltage is stored and compared with the first bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. Methods of applying a magnetic field to the MTJ and then writing the desired resistance state are also disclosed.

Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Abstract: A voltage supply circuit includes a voltage generator and a controller. The voltage generator is configured to pump an externally input voltage and store the pumped external voltage as a first voltage having a set voltage level, before power-up begins, or pump the external voltage, add the pumped voltage to the stored voltage, and output the added voltage as an operating voltage. The controller is configured to output a first control signal to drive the voltage generator or stop operation of the voltage generator, according to an operating state.

Abstract: The invention relates to accessing contents of memory cells. Some embodiments include a memory structure that has a first cell, a second cell, and a sense amplifier. The first cell stores a first value. The first and second cells are connected to the sense amplifier by one or more bit lines. The sense amplifier receives the first value stored by the first cell by using the one or more bit lines and drives the received first value to the second cell through the one or more bit lines. The receiving and driving occur in a single clock cycle. In some embodiments, the second cell outputs the first value. The memory structure of some embodiments also includes a third cell connected to the sense amplifier by the one or more bit lines. The sense amplifier drives a second value to the third cell while the second cell outputs the first value. Other embodiments include a method for accessing data in a memory structure. The method receives a value stored by a first cell; and drives the received value to a second cell.

Abstract: A radio frequency identification (RFID) device includes an antenna configured to transmit or receive a radio frequency signal to or from an external communication apparatus; an analog block configured to generate a first power voltage in response to the radio frequency signal; a digital block configured to receive the first power voltage from the analog block, to transmit a response signal to the analog block, and to output a memory control signal; and a memory configured to read/write data in response to the memory control signal, the memory including a high voltage generating unit for generating a second power voltage from the first power voltage, a first portion driven by the second power voltage, and a second portion driven by the first power voltage, wherein the level of the first power voltage is lower than that of the second power voltage.

Abstract: In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed.

Abstract: One embodiment of the present invention includes applying a first value to a bit line, boosting word lines associated with the bit line and a common selection line to create a first condition based on the first value, and cutting off a boundary non-volatile storage element associated with the common selection line to maintain the first condition for a particular non-volatile storage element associated with the bit line and common selection line. A second value is applied to the bit line and at least a subset of the word lines are boosted to create a second condition for a different non-volatile storage element associated with the bit line and common selection line. The second condition is based on the second value. The first condition and the second condition overlap in time. Both non-volatile storage elements are programmed concurrently, based on their associated conditions.

Abstract: Provided is a resistance variable memory device and a method for operating same. The resistance variable memory device has a phase change material between a top electrode and a bottom electrode. In the method for operating a resistance variable memory, the write current is applied in a direction from the top electrode to the bottom electrode, and the read current is applied in a direction from the bottom electrode to the top electrode. The phase change material is programmed by applying the write current, and a resistance drift of the phase change material is restrained by applying the read current.

Abstract: A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.

Abstract: Embodiments of the present disclosure provide methods, apparatuses and systems including a storage configured to store and output multiple address strides of varying sizes to enable access and precharge circuitry to access and precharge a first and a second group of memory cells based at least in part on the multiple address strides during operation of the host apparatus/system, the first and second group of memory cells being different groups of memory cells.

Abstract: A memory device includes an array of resistance change memory cells divided into a first memory block including a first selected memory cell of a first plurality of memory cells and a second memory block including a second selected memory cell of a second plurality of memory cells, and sensing and writing circuitry configured to simultaneously activate a line connected with the first and second selected memory cells. The first and second selected memory cells may be written by iteratively applying a level-controlled write signal to memory cells not having a programmed state equal to the write data until a verify-read operation indicates respective programmed states for the first and second selected memory cells are equal to the write data.

Abstract: A memory device architecture includes N arrays respectively for storing a 1/N of a page and N write/read circuits, where N is a natural number, respectively for writing or reading a 1/N of the page to/from each of the N arrays.

Abstract: Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to access the second memory cells. The first and second memory cells have a number of threshold voltage values corresponding to a number of states. The states represent values of information stored in the memory cells. During a read operation to read the first memory cells, a first voltage may be applied to the first line and a second voltage may be applied to the second line. At least one of the first and second voltages may include a value based on a change of at least one of the threshold voltage values changing from a first value to a second value. The first and second values may correspond to a unique state selected from all of the states. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator includes two PMOS transistors coupled to a voltage source providing a source voltage. The two PMOS transistors are characterized by a first size. The memory cell also includes two NMOS transistors coupled to ground. Each of the two NMOS transistors are coupled to one of the two PMOS transistors and are characterized by a second size substantially equal to the first size. The memory cell further includes two word line transistors coupled to a word line and characterized by a third size substantially equal to the first size. Power savings associated with the precharge circuit on the order of (Vdh/Vdl)2=36 are achieved in some embodiments.

Abstract: A semiconductor device, which allows a bank interleaving operation by issuing a write command and a read command to different banks while switching them without a waiting time to thereby prevent a drop in data transfer efficiency, is provided. The semiconductor device includes: a memory chip with banks each including at least one memory cell; a logic chip; and data buses, provided corresponding to the banks, for transmitting/receiving write data and read data between the banks and the logic chip. The logic chip includes: a writing data bus for transmitting write data to the memory chip via a data bus; a reading data bus for receiving read data from the memory chip via a data bus; and a switch for, corresponding to a write command or a read command to a bank, connecting the writing data bus or the reading data bus to a data bus connected to the bank.

Abstract: A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are arranged at an intersection point between one of the two bit lines and an even address word line, and an intersection point between the other one of the two bit lines and an odd address word line, respectively; a plurality of booster circuits which are arranged in a plurality of memory banks, respectively, and each of which generates a write voltage and a read voltage to be supplied to a corresponding one of the anti-fuse elements of the respective memory banks, each of the memory banks obtained by dividing the memory cell array; a booster circuit controller to issue an instruction to generate the write voltage and the read voltage to the plurality of booster circuits; a word line selector to activate a different word line at the time of writing from one to be activated at the time of reading, with respect to the s

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.