Abstract: The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

Abstract: A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair or provide stored data to the local line pair, and a precharging circuit configured to precharge the local line pair by selectively using a first voltage and a second voltage in response to a precharge control signal and an operation mode signal, wherein the second voltage is lower than the first voltage.

Abstract: Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.

Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time.

Abstract: A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.

Abstract: A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs.

Abstract: An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.

Abstract: A method of screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing a known data state to the memory cells under test, a forward back-bias is applied to the load transistors of those cells. A write of the opposite data state is then performed, followed by a read of the memory cells. The process is repeated for the opposite data state.

Abstract: Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage.

Abstract: A semiconductor device has a hierarchical bit line structure and comprises first and second local bit lines transmitting first and second signals of first and second memory cells corresponding to a selected word line, and first and second global bit lines electrically connected to the first and second local bit lines through first and second switches, first and second sense amplifiers connected to the first and second global bit lines, and a control circuit. During a first period after the first and second memory cells are simultaneously accessed, the control circuit controls the first switch to conduction state so that the first sense amplifier amplifies the first signal and controls the second switch to non conduction state. During a second period after sensing of the first sense amplifier finishes, the control circuit controls the second switch to conduction state so that the second sense amplifier amplifies the second signal.

Abstract: A system can include write circuitry configured to implement a write finite state machine selected from a plurality of write finite state machines and read circuitry configured to implement a read finite state machine selected from a plurality of read finite state machines. The system also can include a multi-port memory having a write port controlled by the write circuitry and a read port controlled by the read circuitry. The write circuitry and the read circuitry can be configured to implement the selected write finite state machine and the selected read finite state machine to perform one of a plurality of different data transformations using the multi-port memory.

Abstract: An integrated circuit precharges a node 6 to a precharge voltage using precharging circuitry 4. During a discharge phase discharging circuitry 8 selectively discharges that node 6 is to represent a data/signal value. Sensing circuitry 10 detects a discharge characteristic to identify the data/signal value being represented. During the subsequent precharging operation of the node 6 back to the precharge voltage, validating circuitry 12 detects a precharge characteristic, such as the precharge current, the charge transferred, changes in the node voltage or a like, and compares this to the detected discharge characteristic corresponding to the data/signal value sensed by the sensing circuitry. If there is a mismatch, then an operation error signal is generated. The operation error signal may be used to adjust operation parameter, such as the operating voltage/frequency, the timing of the operation of a portion of the integrated circuit or another parameter.

Abstract: A nonvolatile memory device includes: a memory array including a plurality of memory banks which are arranged in a first direction; a write global bit line and a read global bit line extending in the first direction to be shared by the memory banks; a write circuit connected to the write global bit line and disposed on a first side of the memory array; and a read circuit connected to the read global bit line and disposed on a second side of the memory array opposite the first side of the memory array, wherein each of the memory banks extends in a second direction different from the first direction and comprises a plurality of nonvolatile memory cells, each of the nonvolatile memory cells having a variable resistive element whose resistance value varies according to data stored therein.

Abstract: An integrated circuit can include at least one programmable metallization cell (PMC) comprising an ion conducting material and a metal dissolvable in the ion conducting material, selectively connected to a shunt node; and a biasing circuit comprising a current source coupled to the shunt node configurable to provide a first current in a first type operation, and a voltage regulator coupled to the shunt node configured to regulate a potential at the shunt node; wherein in the first type operation, the voltage regulator shunts current with respect to the shunt node in a same direction as a current flow of the at least one PMC.

Abstract: A semiconductor storage device includes a memory cell array including memory cells arranged at respective intersections between first wirings and second wirings. Each of the memory cells includes a rectifier element and a variable resistance element connected in series. A control circuit is configured to apply a first voltage to a selected first wiring and a second voltage lower than the first voltage to a selected second wiring so that a certain potential difference is applied to a selected memory cell positioned at an intersection between the selected first wiring and the selected second wiring. The control circuit performs a concurrent read operation to perform a read operation from plural memory cells concurrently by applying the first voltage to a plurality of the first wirings concurrently. It is possible to switch the number of the first wirings to be applied with the first voltage concurrently in the concurrent read operation.

Abstract: Memory circuitry 2 includes a memory cell 12 coupled to a plurality of bit line pairs 18, 24 providing multiple access ports. Write boost circuitry 36 serves to increase a write voltage applied to write a data value into the memory cell during at least a boost period of a write access. Collision detection circuitry 10 detects when the write access at least partially overlaps in time with a read access. If a collision is detected, then write assist circuitry serves to drive the bit line pair of the detected read access with a write assist voltage difference having the same polarity as the write voltage and a magnitude less than the write voltage with the boost voltage applied. The write assist circuitry drives the bit line pair of the colliding read independently of the write boost circuitry applying the boost voltage such that the boost voltage is undiminished by the action of the write assist circuitry.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, circuits configured to receive program data when a program operation is performed and output a random signal in response to the program data, and a page buffer configured to logically combine the program data and the random signal and to store the logically combined data in the memory cells.

Abstract: A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.

Abstract: A method writes data to a resistive memory, such as spin torque transfer magnetic random access memory (STT-MRAM). The method writes received bits of data to a memory cell array, in response to a first write signal. The method also reads stored data from the memory cell array, after the first write signal is generated, and then compares the stored data with the received bits of data to determine whether each of the received bits of data was written to the memory. In response to a second write signal, received bits of data determined not to have been written during the first write signal, are written.

Abstract: The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.

Abstract: A write circuit writes a first data signal that is an input data signal that indicates a first logic level to each memory bank in sequence and writes a second data signal that is an input data signal that indicates a second logic level to each memory bank simultaneously.

Abstract: A memory system includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells, and a read/write module. The bit lines include a first bit line and a second bit line. The word lines include a first word line and a second word line. Each memory cell is located at an intersection of a respective one of the bit lines and a respective one of the word lines. The memory cells include a first memory cell and a second memory cell. The first memory cell is located at the intersection of the first bit line and the first word line. The second memory cell is located at the intersection of the second bit line and the second word line. The read/write module is configured to concurrently activate the first memory cell and the second memory cell for (i) a read operation or (ii) a write operation.

Abstract: A method and apparatus for controlling writing of data to a graphic memory is provided. In the method and apparatus, a plurality of consecutively input data pieces are controlled to be not consecutively written to the same memory area in terms of time or space.

Abstract: A memory cell stores therein data, a dummy cell replicates an operation of the memory cell, a write control unit makes the dummy cell to perform writing in synchronization with write timing of the memory cell, and a row decoder performs opening and closing of a word line that performs a row selection of the memory cell based on a monitored result of a write condition of the dummy cell.

Abstract: A memory includes at least first and second banks of single-port memory elements, a first local controller adapted to send read and write instructions to the first memory bank, and a second local controller adapted to send read and write instructions to the second memory bank. A global controller is configured to receive first and second memory addresses and a first indication of an operation to be performed at the first memory addresses and a second indication of an operation to be performed at the second memory address and to instruct the first local controller to perform the first indicated operation at the first memory address and to instruct the second local controller to perform the second indicated operation at the second memory address at the same time.

Abstract: A memory module including a plurality of ranks. Each of the ranks includes a parallel test apparatus for simultaneous testing and a parallel test control unit. In response to a parallel test mode control signal, the parallel test apparatus generates first parity data for write data including a plurality of bits and generating first data obtained by replacing a bit value of at least one bit of the plurality of bits of the write data with the first parity data during a write operation, and generates second parity data for the first data and transmitting the second parity data as read data during a read operation. The parallel test control unit controls the write operation and the read operation in a parallel test mode by generating the parallel test mode control signal. Combinations of read data from the plurality of ranks correspond to different bits of the write data.

Abstract: A circuit may include an array having a number of programmable impedance elements that may be placed into at least two different impedance states in a write operation; and a write circuit that applies temperature varying write conditions to the array in a write operation.

Abstract: An integrated circuit includes a normal data storage unit configured to store normal data and output the stored normal data in response to a write command, a read command, and an address signal in a normal operation mode, a test data storage unit configured to store the address signal as test data in response to the write command in a test operation mode, and output the stored test data in response to the read command, and a connection selection unit configured to selectively connect a data input/output terminal of the normal data storage unit or a data output terminal of the test data storage unit to a global line based on whether the integrated circuit is in a first or second one of the normal operation mode and the test operation mode, respectively.

Abstract: A memory system including a plurality of memory cells configured to receive digital signals includes an address decoder, a data bus, and a sense amplifier configured to receive data output from memory cells activated by addresses from the address decoder. The pre-charging the data bus and evaluating previous data by the sense amplifier occurs substantially simultaneously during a first period. The data bus and the sense amplifier are isolated from each other during the first period.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Abstract: A method is provided for achieving SRAM output characteristics from DRAMs, in which a plurality of DRAMs are arranged connected in parallel to a controller in such a way as to be able to obtain SRAM output characteristics using the DRAMs, comprising a process in which data is output to an external device when a control signal for data reading has been input from the external device, by sequentially repeating a step in which the controller sends a data output state control signal to one DRAM and sends a refresh standby state control signal to the other DRAMs, the data is read and sent to the external device from the DRAM in the output state, and a refresh standby state control signal is sent to the DRAM which was in the output state while an output state control signal is sent to another DRAM and data is read out from the DRAM in the output state, and a step in which the controller sends a control signal for changing the output state to the refresh standby state.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality.

Abstract: A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the “sea of gates” model, in which the base element of the structure is a cell able to be configured with a minimum width in relation to the particular technology used. Such a cell includes a bistable element with an input node operatively connected to a writing data line of the memory base cell, and an output node operatively connected to a reading data line of the memory base cell. The bistable element also has a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node of the bistable element.

Abstract: Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.

Abstract: A semiconductor memory device includes a memory cell array configured of at least a first portion and a second portion each including a plurality of memory cells each with a variable resistor which stores an electrically rewritable resistance value as a data, and a control circuit which controls a first operation including selected one of operations to erase, write and read the data in the first portion and a second operation including selected one of operations to erase, write and read the data in the second portion, the first operation and the second operation being performed in temporally overlapped relation with each other.

Abstract: A nonvolatile semiconductor memory device in which a memory cell life can be prolonged while making it possible to perform writing in units of bits. When command information represents writing, a comparing unit 37 compares written data in a target memory cell with write target data to give a comparison result to a write/read control unit 40, when the comparison result represents matching, the write/read control unit 40 does not instruct a decoder unit (51A, 51B, and 53) to perform writing in the target memory cell, and when the comparison result represents mismatching, the write/read control unit 40 instructs the decoder unit to write the write target data in the target memory cell.

Abstract: A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.

Abstract: A non-volatile memory device and a method for programming the same are disclosed. The method for programming the non-volatile memory device includes generating a simultaneous write current based on a program address in such a manner that bit line write cells corresponding to memory cells coupled to the same bit line from among memory cells to be programmed can be simultaneously programmed, and providing the simultaneous write current to the bit line write cells by simultaneously enabling the bit line write cells.

Abstract: To include a comparison circuit that generates comparison results by comparing plural pieces of data simultaneously read via data lines with expected values, an AND gate that activates a first determination signal in response to a fact that at least one of the comparison results indicates a mismatch, and an OR gate that activates a second determination signal in response to a fact that all the comparison results indicate a mismatch. With this arrangement, when a detection test of a defective address is performed in a wafer state, a defect of a column selection line can be detected.

Abstract: A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is stored in a non-volatile manner as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

Abstract: A non-volatile memory device includes a bank including a plurality of unit cells so as to output sensed data to a global input/output (I/O) line, and a data input/output (I/O) unit configured to store the same data as that of a unit cell contained in a bank in a register, store external input data in the register during a write operation, and output data stored in the register to an external part during a read operation.

Abstract: A driving integrated circuit and methods thereof are provided. The driving IC includes a memory for driving a display panel and having a memory structure including at least one cell block, a scan register receiving data read from the memory, a source driver receiving data output from the scan register and outputting the received latched data to the panel and a switching unit establishing a connection between an activated cell block and the scan register in response to an activation of the activated cell block. One method includes performing a read operation to read data from a memory, the read operation including sensing and amplifying data stored within a memory cell, turning on a switch to increase a bit line voltage above a voltage threshold and latching the amplified data received through a line connected to the switch and transmitting the read data to the panel of the display device.

Abstract: Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.

Abstract: A method, circuit arrangement, and design structure utilize a lock prediction data structure to control ownership of a cache line in a shared memory computing system. In a first node among the plurality of nodes, lock prediction data in a hardware-based lock prediction data structure for a cache line associated with a first memory request is updated in response to that first memory request, wherein at least a portion of the lock prediction data is predictive of whether the cache line is associated with a release operation. The lock prediction data is then accessed in response to a second memory request associated with the cache line and issued by a second node and a determination is made as to whether to transfer ownership of the cache line from the first node to the second node based at least in part on the accessed lock prediction data.

Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.

Abstract: A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.

Abstract: A memory device and method are provided incorporating a technique for controlling a write operation within the memory device. The memory device has an array of memory cells, each memory cell supporting writing and simultaneous reading of that memory cell. Write circuitry is arranged, during a write operation, to provide write data to a number of addressed memory cells within the array, whilst word line select circuitry is responsive to the start of the write operation to assert a write word line signal that enables those addressed memory cells to store the write data. Comparing circuitry is arranged, during the write operation, to compare the write data with data currently stored in the addressed memory cells. On detecting that the write data matches the data currently stored in the addressed memory cells, the comparing circuitry asserts a control signal to the word line select circuitry to cause the word line select circuitry to de-assert the write word line signal.

Abstract: A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting a phase-controlled clock signal, and a controller for generating and outputting a control signal for enabling the phase controller that is disabled, at a predetermined time in the additive latency period.

Abstract: A data bus line control circuit prevents a problem of a data access operation on a global data bus (GDB) line although two blocks are simultaneously selected. The data bus line control circuit includes: a global data bus line which is arranged between memory units adjacent to each other as two pairs, and transmits a data from a local data bus line positioned between adjacent sub blocks; and transmission means which is connected between the local data bus line and the global data bus line, and transmits bit line signals of two sub blocks to one pair of global data bus lines different from each other through the local data bus line, when the two sub blocks are simultaneously selected by a block isolation selection signal. As a result, a circuit arrangement and a layout design become simplified, and two operations of 8K refresh and 4K refresh are possible in one chip, therefore, two kinds of effects can be achieved by one chip.

Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.