Abstract: Systems and methods to improve reliability of sensing operations of semiconductor memory arrays requiring reading references such as MRAM or any type of phase change memory (PCM), and to improve yield of the memory arrays have been achieved. The memory array is divided into multiple parts, such as sections or segments. Reference word lines or reference bit lines or both are deployed in each of the multiple parts. Thus, the distance between an accessed line and the correspondent reference line is reduced, and hence the parasitic parameter tracking capability is enhanced significantly. Additionally spare reference word lines or spare reference bit lines can be deployed in each of the multiple parts.

Abstract: Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances.

Abstract: A semiconductor element and an operating method thereof are provided. The semiconductor element comprises a first metal oxide semiconductor (MOS) and a second MOS. The second MOS is electrically connected to the first MOS. The second MOS includes a floating bipolar junction transistor (BJT).

Abstract: A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted.

Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Abstract: A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting in enabling a sense amplifier. To better align detected completion of the discharge by the timer cells to a read from actual memory cells at any voltage in the operating voltage range of the memory, the gate to source voltage of the timer cells' access transistors is lowered by decreasing the logic high voltage level applied by the reference wordline. The timer cells may also, or alternatively, have pulldown transistors coupled to the internal true node, wherein a gate terminal of the pulldown is coupled to the reference wordline node and activated with the lowered gate to source voltage.

Abstract: A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate of the first transistor, a second potential supplied to the sense node, and a third potential supplied to the bit line are controlled so that the first potential applied to a gate of the first transistor is between the second and third potentials, the second potential is set larger than the third potential, and a predetermined potential obtained by subtracting a threshold voltage of the first transistor from the first potential is smaller than the third potential and higher than a low potential supplied to the second transistor. A potential of the bit line transitions from the third potential toward the low potential in accordance with data of a current change memory cell.

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract: A nonvolatile semiconductor memory device comprises a three-dimensional cell array block in which a plurality of cell array layers are stacked, each of the cell array layers including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of memory cells disposed at each of intersections of the first and second lines and each including a variable resistance element configured to store an electrically rewritable resistance value as data in a nonvolatile manner, and a reading control circuit for reading data from the memory cells under a condition set in respective groups to which one or more cell array layers having a common electric property of the memory cells belong.

Abstract: A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs and an output. The circuit is configured to combine (add or subtract) input signals. The first input may be connected to the analog input. The delta-sigma modulator may also include an integrator connected to the output of the circuit, an analog-to-digital converter with an input connected to an output of the integrator and an output connected to the digital output, and a digital-to-analog converter with an input connected to the output of the analog-to-digital converter and an output connected to the second input of the circuit.

Abstract: A non-volatile semiconductor device and a method for controlling the same are disclosed, which can increase a read efficiency of the non-volatile semiconductor device using the Low Power Double Data Rate (LPDDR) 2 specifications. The non-volatile semiconductor device includes a decoder configured to output a plurality of active control signals by decoding an active address and an active signal, and a plurality of active controls configured to be controlled by the plurality of active control signals and a plurality of active reset signals so as to generate a plurality of active enable signals that are independently activated.

Abstract: A semiconductor device includes at least one memory cell die. The at least one memory cell die includes a data storage unit. The at least one memory cell die includes at least one read assist enabling unit electrically connected to the data storage unit. The at least one read assist enabling unit configured to lower a voltage of a word line. The memory cell die also includes at least one write assist enabling unit electrically connected to the data storage unit. The at least one write assist enabling unit configured to supply a negative voltage to at least one of a bit line or a bit line bar.

Abstract: In at least one embodiment, a multiplexer has a plurality of sub-circuits, and each of the plurality of sub-circuits has a first transistor, a second transistor, and a third transistor. Drains of the first transistors are coupled with a first terminal of a fourth transistor, and drains of the second transistors are coupled with a second terminal of the fourth transistor. In at least one embodiment, a method of outputting data using the multiplexer includes turning on the second transistor of a selected one of the plurality of sub-circuits responsive to a clock signal and address information. The second transistor of a non-selected one of the plurality of sub-circuits is turned off. The fourth transistor is turned on responsive to the clock signal.

Abstract: A memory device in which a circuit reads a cell condition. A terminal provides voltage to a bit line of the circuit via a switch. The circuit outputs and enables storage of a first logical value when the voltage provided from the terminal does not exceed a threshold value. The circuit outputs and enables storage of a second logical value when the voltage provided from the terminal exceeds the threshold value. The output and storage occurs in the absence of an electrical connection between the cell and circuit. The switch provides voltage supplied from the terminal to the bit line of the circuit. The voltage increases from a value which does not exceed the threshold to a value which exceeds the threshold.

Abstract: A method of providing non-volatile memory in an integrated circuit is disclosed. The method may comprise storing a plurality of data blocks in volatile memory elements of the integrated circuit, wherein each data block of the plurality of data blocks comprises a plurality of data bits; reading back the plurality of data bits associated with a data block of the plurality of data blocks; determining, by a control circuit, whether values read back for the plurality of data bits associated with the data block indicate valid data in the data block; and reading back, for another data block of the plurality of data blocks, stored data bits to determine a value for the other data block. A circuit for providing non-volatile memory in an integrated circuit is also disclosed.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array configured by plural memory cells each including a variable resistor and each provided between first and second lines. A control circuit applies to a memory cell through the first and second lines a writing voltage for writing data or a reading voltage for reading data. A sense amplifier circuit senses data retained in a memory cell based on a current flowing through the first line. In a data writing operation, the control circuit applies a writing voltage to each of n number of memory cells configuring one unit such that the memory cells may be supplied with different resistance values. In a data reading operation, the sense amplifier circuit compares level relationship of the resistance values of n number of memory cells configuring one unit and reads out n! patterns of data from the one unit.

Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.

Abstract: A word line driver circuit for providing a suppressed word line voltage includes a switch configured to selectively load a word line to a suppressed word line voltage node and a word line charging circuit coupled between a high power supply node and the suppressed word line voltage node. The word line charging circuit includes a first transistor device responsive to a control pulse for charging the suppressed word line voltage node to a suppressed word line voltage and a second transistor device for maintaining the suppressed word line voltage.

Abstract: A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.

Abstract: Mechanisms for improving static noise margin and/or reducing misread current in multi-port devices are disclosed. In some embodiments related to dual port SRAM a suppress device (e.g., transistor) is provided at each word line port. When both ports are activated, both suppress devices are on and lower the voltage level of these ports, which in turn lower the voltage level at the node storing the data for the memory. As the voltage level at the data node is lowered, noise margin is improved and read disturb can be avoided.

Abstract: A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

Abstract: An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.

Abstract: Provided is a semiconductor memory device including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each row of the memory cells, a plurality of bit line pairs arranged corresponding to each column of the memory cells, a column selector that selects any of the plurality of bit line pairs based on a column selection signal and connects the selected bit line pair to a data line pair, a precharge circuit that precharges the data line pair, a sense amplifier that amplifies a potential difference of the data line pair, and a control circuit that controls current for driving the sense amplifier based on potentials of the data line pair after a lapse of a specified period from start of amplification of the potential difference of the precharged data line pair by the sense amplifier.

Abstract: One embodiment of the present invention sets forth a clamping circuit that is used to maintain a bit line of a storage cell in a memory array at a nearly constant clamp voltage. During read operations the bit line is pulled high or low from the clamp voltage by the storage cell and a change in current on the bit line is converted by the clamping circuit to produce an amplified voltage that may be sampled to read a value stored in the storage cell. The clamping circuit maintains the nearly constant clamp voltage on the bit line. Clamping the bit line to the nearly constant clamp voltage reduces the occurrence of read disturb faults. Additionally, the clamping circuit functions with a variety of storage cells and does not require that the bit lines be precharged prior to each read operation.

Abstract: Some embodiments of the invention relate to a sense amplifier configured to determine the slope of a bitline charging voltage and to utilize the determined slope in combination with a voltage level sensing scheme to aid in reading data from a memory cell associated with the bitline. In particular, a sense amplifier circuit is configured to determine a slope of a bit line charging voltage and based upon the determined slope to adjust the slope of the bitline voltage (e.g., by adding a dynamic slope dependent current to a memory cell current configured to charge the bitline) provided to a sense amplifier. By adjusting the slope of the bitline voltage, the charging speed of memory cells in a low resistive state (e.g., having a high cell current and therefore a good SNR) can be increased.

Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.

Abstract: Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector.

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

Abstract: A semiconductor memory device has: memory blocks; and a local bus connected to the memory blocks. Each memory block has: switches respectively provided between bit line pairs and the local bus and each of which is turned ON in response to a selection signal; a dummy local bus; first and second control circuits. The local bus and the dummy local bus are precharged to a first potential before a read operation. In the read operation, the first control circuit outputs the selection signal to a selected switch to electrically connect a selected bit line pair and the local bus, while the second control circuit supplies a second potential lower than the first potential to the dummy local bus. The first control circuit stops outputting the selection signal when a potential of the dummy local bus is decreased to a predetermined set potential that is between the first and second potentials.

Abstract: A data transfer circuit includes a write circuit to control writing of write data to a memory, a read circuit to control reading of data from the memory, a first circuit to register a store position in the memory at which data written to the memory is stored, and a second circuit to store a data pattern when the write data is comprised of repeated patterns each identical to the data pattern, wherein the write circuit does not register the store position in the first circuit with respect to the written data that is comprised of the repeated patterns each identical to the data pattern stored in the second circuit, and the read circuit reads the data pattern from the second circuit for provision to a source issuing a read request when data requested by the read request corresponds to the data pattern stored in the second circuit.

Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.

Abstract: An interleaved memory circuit includes a memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line. The interleaved memory circuit further includes a local control circuit coupled with the memory bank. The interleaved memory circuit further includes a global control circuit coupled with the local control circuit, an interleaving access including a clock signal having a first cycle and a second cycle for accessing the first memory cell, where the second cycle is capable of enabling the local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.

Abstract: A memory device including variable resistance elements comprises a plurality of memory cells configured to store data; a first signal transmission/reception unit and a second signal transmission/reception unit configured to transmit a signal to the memory cells or receive a signal from the memory cells; a first transmission line arranged to couple first ends of the memory cells to the first signal transmission/reception unit; and a second transmission line configured to couple second ends of the memory cells to the second signal transmission/reception unit, wherein a first resistance of a first signal path coupled between the first and second signal transmission/reception units through a first memory cell of the memory cells is substantially equal to a second electrical resistance of a second signal path coupled between a second memory cell and the first and second signal transmission/reception units through a second memory cell of the memory cells.

Abstract: To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

Abstract: In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between. The material has first and second lateral regions of different composition relative one another. One of the first and second lateral regions is received along one of two laterally opposing edges of the material. Another of the first and second lateral regions is received along the other of said two laterally opposing edges of the material. At least one of the first and second lateral regions is capable of being repeatedly programmed to at least two different resistance states. Other aspects and implementations are disclosed.

Abstract: A memory device includes: a plurality of word lines and bit lines specifying addresses to be accessed; and a plurality of memory cells of consecutive addresses arranged to correspond to each of the word lines. The plurality of memory cells of the consecutive addresses are accessible in parallel by the plurality of bit lines each corresponding to one of the memory cells. Among the plurality of word lines, a first word line and a second word line that specifies an address next to that of the first word line have an overlapping address range, and a first memory cell connected to the first word line and a second memory cell connected to the second word line are assigned in dual fashion to a same address.

Abstract: In an embodiment, a method of operating a memory cell coupled to a first port and to a second port includes determining if a first port is requesting to access the memory cell and determining if a second port is requesting to access the memory cell. Based on the determining, if the first port and the second port are simultaneously requesting to access the memory cell, the second port is deactivated, the memory cell is accessed from the first port, and an accessed memory state is propagated from the first port to circuitry associated with the second port.

Abstract: A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.

Abstract: A system including a reference voltage module to select a first reference voltage between a first threshold voltage corresponding to a first state of a memory cell and a second threshold voltage corresponding to a second state of the memory cell, a second reference voltage less than the first reference voltage, and a third reference voltage greater than the first reference voltage. The system includes a read module to perform a first read operation to determine a state of the memory cell based on the first reference voltage, and in response to a first failure to decode data read from the memory cell in the first read operation, perform a second read operation to determine the state based on the second reference voltage and a third read operation to determine the state based on the third reference voltage.

Abstract: The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one of some of bits of a column address signal. It is thus possible to reduce unnecessary switching current.

Abstract: An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.

Abstract: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.

Abstract: A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal.

Abstract: A SRAM device which can set a threshold voltage of a selection transistor appropriate for all the cells on an SRAM array is disclosed. The SRAM device uses a field effect transistor as the selection transistor. The field effect transistor includes a gate to drive the transistor and a terminal to control a threshold voltage, which are electrically separated from each other. The SRAM device also includes a circuit which, in a reading operation, gradually increases a voltage supplied to the terminal at the start of the reading to control the threshold of the selection transistor.

Abstract: A semiconductor memory device includes a data coding logic for generating converted data groups and a inverted flag data from original data groups received by the semiconductor memory device. The number of zeros in the converted data groups is less than or equal to the number of zeros in the original data groups. The semiconductor memory device also includes data decoding logic for generating the original data groups from the converted data groups and the inverted flag data. A peripheral circuit may be enabled to program the converted data groups and the inverted flag data into the memory cells and read the converted data groups and the inverted flag data from the memory cells. A control logic may be enabled to generate control signals for the data coding logic, the data decoding logic, and the peripheral circuit.

Abstract: An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.

Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.

Abstract: Integrated circuits may include configurable-port memory cells. The configurable-port memory cells may be operable in single-port mode and multiport mode. Each configurable-port memory cell may be coupled to first and second pairs of data lines. The configurable-port memory cell may include a first latching circuit having a first data storage node and a second latching circuit having a second data storage node. The first latching circuit may be coupled to the first pair of data lines through a first set of access transistors, whereas the second latching circuit may be coupled to the second pair of data lines through a second set of access transistors. An additional transistor may be coupled between the first and second data storage nodes. The configurable-port memory cell is configured in the single-port mode if the additional transistor is turned off and is configured in the dual-port mode if the additional transistor is turned on.

Abstract: According to one embodiment, a magnetic memory includes a magnetoresistive element includes a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is variable and a nonmagnetic layer disposed between the fixed layer and the recording layer. A direction of a read current is set to a first direction in a case where an expression of MR ratio ?|Ic+/Ic?|?1 is satisfied if a critical current of the first direction used to write the magnetoresistive element to the parallel state is set to Ic? and a critical current of a second direction used to write the magnetoresistive element to the anti-parallel state is set to Ic+.

Abstract: A system can include write circuitry configured to implement a write finite state machine selected from a plurality of write finite state machines and read circuitry configured to implement a read finite state machine selected from a plurality of read finite state machines. The system also can include a multi-port memory having a write port controlled by the write circuitry and a read port controlled by the read circuitry. The write circuitry and the read circuitry can be configured to implement the selected write finite state machine and the selected read finite state machine to perform one of a plurality of different data transformations using the multi-port memory.