Abstract: Various implementations described herein are directed to a method. The method may receive an address to access data stored in memory. The method may enable a data access pipeline to perform memory access operations so as to access the data stored in the memory based on the address. The method may dynamically adjust the data access pipeline during the memory access operations so as to output the data based on the address.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory controller is disclosed. The IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. Receiver circuitry receives the first and second read data via a first data link interface and the third and fourth read data via the second data link interface. For a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and at a first serialization ratio.

Abstract: Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.

Abstract: A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: A system and method for efficiently resetting data stored in a memory array are described. In various implementations, an integrated circuit includes a memory for storing data, and a processing unit that generates access requests for the data stored in the memory. When access circuitry of the memory array begins a reset operation, it reduces a power supply voltage level used by memory bit cells in a column of the array to a value less than a threshold voltage of transistors. Therefore, the p-type transistors of the bit cells do not contend with the write driver during a write operation. The access circuitry provides the reset data on the write bit lines, and asserts each of the write word lines of the memory array. To complete the write operation, the access circuitry returns the power supply voltage level from below the threshold voltage level to an operating voltage level.

Abstract: The present invention relates to a testing method, a testing system, and a testing apparatus for a semiconductor chip. The method includes: acquiring a target chip; obtaining an abnormal chip after a test of read and write functions is performed separately on a preset number of memory cells in an edge region of the target chip; recording location information of individual memory cells with abnormal read and write functions on the abnormal chip; judging whether an abnormality of read and write functions of the abnormal chip is a block abnormality based on the location information; wherein the abnormal chip refers to the target chip including the memory cell with abnormal read and write functions.

Abstract: An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.

Abstract: A memory access speed adjustment method, control device and memory module are provided. The method is for use in controlling a controller of a memory and includes steps of: obtaining a current temperature value of the memory; determining an access speed threshold of the memory according to a continuous variation relation with respect to a difference between the current temperature value and a target temperature value; and adjusting, by the controller, an access speed of the memory according to the access speed threshold.

Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

Abstract: A memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a memory cell array having pages. The memory system is configured to execute a first operation method and a second operation method. The memory system includes a control information storage unit in which a first value is set for pages having a write operation speed that is slower than a first speed, and a second value is set for pages having a write operation speed that is equal to or higher than the first speed. The memory system is configured to, at the time of write operation, select the first operation method for a target page having the first value and perform the write operation using the first operation method, and select the second operation method for a target page having the second value and perform the write operation using the second operation method.

Abstract: Disclosed is a static random access memory (SRAM) device. According to example embodiments of the present disclosure, a control logic of the SRAM device may include a tracking circuit connected with metal lines for tracking the number of columns of a memory cell array and the number of rows of the memory cell array. By the tracking circuit, a length of word lines of the memory cell array and a length of bit lines of the memory cell array may be tracked. The control logic of the SRAM device may generate control pulses optimized for the size of the memory cell array, based on a tracking result(s) of the tracking circuit. Accordingly, a power and a time necessary for a write operation and a read operation may be reduced.

Abstract: The present disclosure provides a signal transmission method and a signal transmission device, which are applied to a digital circuit including a plurality of circuit modules connected in series, and each circuit module is configured to perform corresponding operation processing based on a first clock signal provided by a first clock. The method includes: under driving of a second clock signal provided by a second clock, transmitting a first signal output by a current circuit module to a target circuit module in response to reception of the first signal, the first signal is a signal output by the current circuit module when operating based on the first clock signal, transmission of the first signal is completed within a current clock cycle of the first clock, and a clock rate of the second clock is greater than that of the first clock.

Abstract: Disclosed herein are related to reducing power consumption of a memory device when transitioning from a sleep state to an operational state. In one aspect, the memory device includes a memory cell to store data. In one aspect, the memory device includes an output driver configured to: generate an output signal indicating the stored data, in response to a sleep tracking signal indicating that the memory cell is in the operational state, and generate the output signal having a predetermined voltage irrespective of the stored data, in response to the sleep tracking signal indicating that the memory cell is in the sleep state. In one aspect, the sleep tracking signal is delayed from a sleep control signal causing the memory cell to operate in the sleep state or the operational state.

Abstract: Memory includes at least one memory chip, a command port and a data port. Each memory chip includes at least one channel. Each channel includes multiple banks that are configured to perform read and write operations alternately. The command port is configured to receive command signals at a preset edge of a command clock, and the command signals are configured to control the read and write operations of the banks. The data port is configured to receive data signals to be written into the banks or transmit data signals at preset edges of a data clock. The command port includes a row address port and a column address port. The row address port is configured to receive a row address signal at a position of a target memory cell, and the column address port is configured to receive a column address signal at a position of the target memory cell.

Abstract: A signal masking circuit includes a receiving circuit, a delay control circuit, and a logical operation circuit. The receiving circuit is configured to: receive a signal to be processed and a chip select (CS) signal, and output an initial processing signal and an initial CS signal. The delay control circuit is configured to perform delay and logical control operations on the initial CS signal to obtain a CS masking signal, where a pulse width of the CS masking signal is greater than or equal to two preset clock periods. The logical operation circuit is configured to perform invalid masking on the initial processing signal according to the CS masking signal to obtain a target signal.

Abstract: A phase interpolating (PI) system includes: a PI stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal; and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component. The capacitive component is tunable to exhibit non-zero capacitances. The capacitive component has a Miller effect configuration resulting in a reduced footprint of the amplifying stage.

Abstract: Methods, systems, and devices for self-refresh of memory cells are described. A controller coupled with a memory cell may be configured to apply a first voltage to a control gate of a first transistor, where the first voltage activates the first transistor to selectively couple terminals of the first transistor with each other based on a charge stored on the interstitial gate. The controller may be configured to apply a current to a bit line, where a second voltage of the bit line is based on the current and the charge stored on the interstitial gate. The controller may be configured to apply, based on applying the first voltage to the control gate of the first transistor and applying the current to the bit line, a third voltage to a gate of a second transistor to couple the bit line with the interstitial gate of the first transistor.

Abstract: A storage device and a manufacturing method thereof are provided and relate to the technology field of storage. The storage device includes storage a first chip and a second chip. The first chip includes a storage array. The storage array includes at least one storage block. The second chip includes a logic control circuit. The logic control circuit includes a global bit line decoder. The global bit line decoder is electrically connected to the at least one storage block. An occupied area after the first chip and the second chip are stacked can be reduced by constructing the global bit line decoder block constituted by the global bit line decoder in the top view projection area of the second chip, thereby reducing plane occupied space of the storage device. This is beneficial for minimizing the size of the storage device.

Abstract: A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship been the control signal and the timing signal.

Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

Abstract: A system and method compensate for latency, where the system includes a transmit module and a receive module that implements a DLL in a pseudo synchronous communications link. The method includes determining maximum data latency based on synchronous latencies and analog delays; measuring an actual data path latency by determining a delay in receiving a test pattern transmitted from the transmit module at the receive module using a common synchronization pulse provided the transmit and receive modules simultaneously or with a known fixed latency separation during calibration; determining a latency difference between the determined maximum data latency and the measured data path latency; and compensating for the latency difference for a subsequent data signal transmitted from the transmit module in the pseudo synchronous communications link, such that a total latency of the system with regard to the subsequent data signal is equal to the maximum data latency for the system.

Abstract: Disclosed is an operating method of a controller for controlling an operation of a semiconductor memory device including a plurality of memory cells. In the operating method of the controller, program data to be stored in a selected page of the semiconductor memory device is generated, and the semiconductor memory device is controlled to program the program data in the selected page. Bit data at a predetermined position in the program data is data for allowing a threshold voltage of a corresponding memory cell to maintain an erase state.

Abstract: A clock generation circuit, a latch using same, and a computing device are provided. The clock generation circuit includes an input end, configured to input a pulse signal; a first output end, configured to output a first clock signal; a second output end, configured to output a second clock signal; and an input drive circuit, a latch circuit, an edge shaping circuit, a feedback delay circuit, and an output drive circuit, where the input drive circuit, the latch circuit, the edge shaping circuit, the feedback delay circuit, and the output drive circuit are sequentially connected between the input end and the first output end as well as the second output end in series. A clock pulse can be effectively shaped, the use of a clock buffer can be reduced, and the correctness and accuracy of data transmission and latching can be improved.

Abstract: An electronic device is provided. The electronic device includes a power pin, a main circuit, and a start-up circuit. The power pin is configured to receive a power supply. The start-up circuit includes a switch coupled between the power pin and the main circuit, a timer and an oscillator. The switch is configured to selectively provide the power supply to the main circuit in response to a control signal. The oscillator, is configured to provide a periodic signal. The timer is configured to provide the control signal to turn on the switch when counting to a start-up time according to the periodic signal, so that the main circuit is configured to provide a fixed voltage according to the power supply.

Abstract: A semiconductor device includes an input control signal generation circuit configured to generate an input control signal when performing an internal operation and configured to adjust a time point at which the input control signal is generated, based on whether a frequency of a clock corresponds to a preset frequency range. The semiconductor device includes an output control signal generation circuit configured to generate an output control signal after a latency elapses when performing the internal operation. The semiconductor device includes a pipe latch circuit configured to latch input data based on the input control signal and configured to output the latched input data as output data based on the output control signal.

Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes a first-level memory unit which includes a plurality of second-level memory units. Each second-level memory unit includes N main banks and a redundant bank, where N is a positive integer. The I/O circuit is configured to direct N pieces of data to or from N working banks in a corresponding second-level memory unit. The I/O control logic is configured to determine the N working banks from the N main banks and the redundant bank in the corresponding second-level memory unit based on bank fail information indicative of a failed main bank of the N main banks and control the I/O circuit to direct the N pieces of data to or from the N working banks, respectively.

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

Abstract: Delay elements and multiplexers are in programmable delay elements. Each programmable delay element has a chain of delay elements to produce successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer to select among an input clock and delay element outputs in the chain of delay elements to produce a skewed clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select among clocks that include a first clock, and a second clock that is from one of the delay elements of another programmable delay element to produce the clock of the programmable delay element.

Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

Abstract: A semiconductor device capable of decreasing a jitter component is provided. A first calibration circuit searches a second delay value of a data delay circuit while determining a delay value of a strobe delay circuit to be a first delay value that is larger than the minimum value and smaller than the maximum value. A second calibration circuit determines a first corrected delay value and a second corrected delay value by shifting both the first delay value and the second delay value by the same correction value in a direction toward the minimum value, and sets the first corrected delay value and the second corrected delay value to the strobe delay circuit and the data delay circuit, respectively.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: Devices are disclosed. A device may include an interface region including two or more input circuits operably coupled to the number of input signals, wherein one of the two or more input circuits for each input signal is adjacent at least two other input circuits coupled to different input. Associated systems are also disclosed.

Abstract: Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

Abstract: Provided are a signal generation circuit and a memory. The signal generation circuit includes: a clock delay circuit for delaying an initial pulse signal to output an intermediate signal delayed by a first delay duration, the first delay duration being equal to one or more clock cycles; a physical delay circuit for delaying the intermediate signal to output a target signal, if an actual delay duration of the physical delay circuit is equal to a second delay duration, the target signal being delayed by a target duration, a difference between the actual and second delay durations fluctuating within a first preset range, and the shorter the second delay duration, the narrower the first preset range; and a generation circuit for outputting a function pulse signal having a pulse width equal to a time interval between rising edges of the initial pulse signal and the target signal.

Abstract: A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

Abstract: A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value.

Abstract: The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards.

Abstract: A method of controlling a memory device can include: determining, by the memory device, a time duration in which the memory device is in a standby mode; automatically switching the memory device from the standby mode to a power down mode in response to the time duration exceeding a predetermined duration; exiting from the power down mode in response to signaling from a host device via an interface; and toggling a data strobe when data is ready to be output from the memory device in response to a read command from the host device.

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

Abstract: The invention provides a dynamic random-access memory (DRAM) and an operation method thereof. The DRAM includes a memory cell array, a temperature sensor, and a refresh logic circuit. The temperature sensor senses a temperature of the DRAM. The refresh logic circuit enters a tRFC based on a refresh command issued by a memory controller to perform an automatic refresh operation on at least one memory cell row of the memory cell array. In a temperature-controlled refresh mode, the refresh logic circuit correspondingly adjusts a number of a plurality of tRAS periods in the tRFC according to a temperature sensing result of the temperature sensor. In a fine granularity refresh mode, the refresh logic circuit correspondingly adjusts the number of the tRAS periods in the tRFC according to a granularity specified by the memory controller.

Abstract: An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.

Abstract: A semiconductor device includes an internal command generation circuit configured to generate a synthesized command from a command which is inputted in synchronization with any one of a first internal clock and a third internal clock generated by dividing a frequency of a clock, and configured to generate a first internal command and a second internal command by delaying the synthesized command depending on a detected input time of the command. The semiconductor device also includes a data transmission circuit configured to generate transmission data from data in synchronization with any one of the first internal command and the second internal command.

Abstract: Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal.

Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.

Abstract: According to one embodiment, a memory system includes a memory interface circuit. The memory interface circuit has delay circuits, a detection circuit, and a control circuit. One of the delay circuits applies a delay to a data signal. Another delay circuit generates, fora strobe signal, a first delay strobe signal, a second delay strobe signal, and a third delay strobe signal, each with different delay amounts. The detection circuit detects a drift in the timing of the first delay strobe signal with respect to the delayed data signal by using the delay data signal, the first delay strobe signal, the second delay strobe signal, and the third delay strobe signal. The control circuit adjusts the first delay amount, the second delay amount, and the third delay amount in a direction to compensate the drift.

Abstract: A storage device and a manufacturing method thereof are provided. The storage device includes a first chip and a second chip. The second chip is stacked on the first chip in a third direction. The first chip includes a storage array, and the storage array includes at least one storage block. An occupied area after the first chip and the second chip are stacked can be reduced by constructing a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block, and a second local bit line decoder block in a top view projection area, thereby reducing plane occupied space of the storage device. This is beneficial for minimizing the size of the storage device.

Abstract: Techniques usable in optimization processing are described. A system includes an optimization processing unit (OPU). The OPU includes stochastic computing units and at least one programmable interconnect. Each of the stochastic computing units includes nodes and multiplication unit(s) configured to interconnect at least a portion of the nodes. The programmable interconnect(s) are configured to provide weights for and to selectably couple a portion of the stochastic computing units.

Abstract: Systems and methods are disclosed, including selectively providing one of a first reset or a second reset to transition to a storage system from a low power mode to an operational power mode in response to a hardware reset signal and a value of a control bit on the storage system.

Abstract: A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.