Abstract: A method for generating a channel stream. The method generally comprises the steps of (A) transforming a plurality of data streams, wherein every data stream entering the channel stream experiences a unique transformation and (B) serializing the data streams as transformed into the channel stream.

Abstract: To fully evaluate a real signal line and a real memory cell adjacent to a dummy signal line and utilize dummy signal line as real signal line, a semiconductor memory includes at least one real signal line connected to real memory cells driven by a real driver and at least one dummy signal line outside the real signal line connected to dummy memory cells, driven by a dummy driver. Real driver and dummy driver drive the real signal line and the dummy signal line synchronous with a common timing signal generated by an operation control circuit. Consequently, a stress evaluation is also performable, e.g., on a real signal line outside of a memory cell array under the same condition of a real signal line on the inner side. Dummy signal line is driven using common timing signal and evaluated, thus being usable as a redundancy signal line to relieve failure.

Abstract: Disclosed is a method and apparatus for synchronizing data in a number of separate integrated circuits. In one embodiment, the apparatus includes a first integrated circuit configured to receive first data, and a second integrated circuit coupled to the first integrated circuit configured to receive second data. The second integrated circuit is separate from the first integrated circuit. The second integrated circuit is further configured to synchronize the second data with the first data. In another embodiment, the apparatus includes a first integrated circuit configured to receive first data, and a second integrated circuit coupled to the first integrated circuit configured to receive second data. The second integrated circuit is separate from the first integrated circuit. The second integrated circuit is further configured to detect when the second data is out of synchronization with the first data.

Abstract: A system and method are provided for mapping information into Synchronous Payload Envelopes (SPEs). The method provides information bytes at a nominal system clock-based data rate, which is about equal to a system clock, but may be adjusted. An external clock has a rate approximately equal to the system clock rate. The method generates SPEs with identically-positioned information bytes, regardless of differences between the system and external clock rates. The SPEs are combined with Transport Overhead (TOH) and transmitted as a message frame at the external clock rate. SPEs are generated maintaining the positions of the information bytes within each SPE, without pointer adjustments, despite differences between the system and external clock rates. Expressed another way, message frames are generated with payload and TOH sections, and the information bytes are located exclusively in the payload sections. As a result, constant pointer values (e.g., H1/H2 or V1/V2) are maintained for all the SPEs.

Abstract: A method and apparatus for multiplexing and demultiplexing communication signals are described herein. In one embodiment, an apparatus includes first sample logic to sample a plurality of communication signals each including a clock component and a non-clock component. The first sample logic includes a first multiplexer to receive the clock components and a second multiplexer to receive the non-clock components. In addition, a first counter is coupled to a control input of the first multiplexer and the second multiplexer. A capture unit including a non-clock component storage element coupled to an output of the second multiplexer and edge detection logic is coupled to an output of the first multiplexer to detect a transition of a clock component and coupled to a control input of the non-clock component storage element.

Abstract: The present invention relates to methods and systems for transferring SONET/SDH frames between nodes by mapping the SONET/SDH frames onto individual channels of data and transferring the SONET/SDH frames over parallel transmission links. More particularly, the methods for transferring SONET/SDH frames includes transmitting SONET/SDH frames and receiving SONET/SDH frames using a transceiver module.

Abstract: A method, apparatus, and system for originating a packet.

Abstract: A method and apparatus for enabling repeated switching of a cross-connect and a timing source in a network element through the use of a phase adjuster. In one embodiment, a traffic card includes an aligner to adjust the occupancy of the data in two ingress FIFOs to synchronize their occupancy. In addition, the traffic card includes a clock control logic, including a phase adjuster, to adjust the phase of clock signals driving the two ingress FIFOs to avoid an underflow or overflow.

Abstract: A desired FIFO buffer fill level is continuously derived during mapping or demapping of plesiosynchronous data signals into synchronized data signals, or vice-versa. One of j predefined integer values Ii is repetitively consecutively produced during each consecutive one of j FIFO buffer write clock cycles, where i=1, . . . , j and where j and the integer values Ii are selected such that ? i = 1 j ? ? I i j closely approximates the number of bits read from the FIFO buffer per FIFO buffer write clock cycle. During each kth consecutive FIFO buffer write clock cycle, a Bits_Read value Ik+Ik-1 is produced where k=1, . . . , p; a Bits_Written value is produced; a Gap_Pattern value is derived by subtracting the Bits_Read value from the Bits_Written value; and, the Gap_Pattern is added to a predefined value representative a FIFO buffer center fill level to produce the desired FIFO buffer fill level.

Abstract: A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The retimers are configured to retime, amplify and retransmit a received data stream without altering the received data rate. Thus, the data rate from the first node is received at the same frequency at the last node, regardless of the number of retimers. In general, the retimer performs rate compensation on a retimer local clock, rather than on the data stream, so the attributes of the clean retimer clock can be applied to the data stream without changing the data rate.

Abstract: It is proposed that currently unused portions of transport overhead in frames sent on a high-speed outgoing channel be used to carry error count information from each of four low-speed input channels. At a 4:1 combiner, error monitoring bytes are extracted from transport overhead of frames received on each of the four input channels. Error counts are determined and accumulated for each input channel before being passed to a transport overhead generator for the outgoing channel, where they are inserted as bit patterns in unused portions of the transport overhead. At a receiving demultiplexer, the error counts are extracted from the transport overhead of incoming frames. The extracted error counts are then used to alter the error monitoring bytes included in the transport overhead of frames sent on each of four outgoing channels such that, at the far end of those outgoing channels, a correct number of errors for the three part path may be determined.

Abstract: A system and method are disclosed for parallel compression and decompression of a bitstream. For compression, the bitstream is separated into a plurality of components, and the components are encoded using a compression algorithm. Packets are then constructed from the encoded components. At least one packet is associated with each encoded component and comprises header information and encoded data. The packets are combined into a packetized encoded bitstream. For decompression, the packets are separated from the packetized encoded bitstream using the header information. The packets are then decoded in parallel using a decompression algorithm to recover the encoded data. The plurality of components are reconstructed from the recovered encoded data and combined to-recover the bitstream.

Abstract: Method of processing a transmitted encoded media data stream is received. If a data element arrives prior to, or at, a predetermined playout deadline, the data element is decoded, the media represented by the decoded data element is played, and the data element is provided to a decoder state machine to update a decoder state. If a data element arrives after the predetermined playout deadline, the data element is provided to the decoder state machine to update the decoder state. In one embodiment, if the specified data element fails to arrive by the playout deadline, a subsequently received data element is saved in memory. Then, if the specified data element arrives after the predetermined playout deadline, the specified data element and the saved, subsequently received, data element are provided to the decoder state machine to update the decoder state.

Abstract: In one aspect of this invention, a control unit generates a frame having control data, and transmits it to a controlled apparatus via a transmission/reception unit or the like at a predetermined priority. In the controlled apparatus, a transmission/reception unit receives the frame, and a control unit analyzes it to generate a predetermined signal on the basis of the analysis result. The signal is output to a driving system or the like via an external I/O or the like. The controlled apparatus generates a response frame and transmits it to the control apparatus. In the control apparatus, the control unit analyzes the contents of the response frame, and a predetermined display is provided on the LED of an output unit on the basis of the analysis result.

Abstract: A transmitter apparatus has a modulator for modulating a carrier wave to produce a modulated wave having communication data superimposed thereon and a transmitter for transmitting the modulated wave to a receiver apparatus. Before starting communication, the transmitter apparatus transmits a predetermined dummy pulse to the receiver apparatus so as to bring the communication data restored by demodulation in the receiver apparatus into a logic state in which the communication data should be kept when no communication is taking place. This makes it possible to perform correct communication even if the communication data demodulated in the receiver apparatus before the start of communication is not kept in the logic state in which it should be kept when no communication is taking place.

Abstract: A process for transmission of information between at least two devices comprises: generating a serial message coded by means of a time sequence of binary transitions called bits; reducing the time length of all bits in the message by changing them into shorter bits, in order to insert additional bits whose half duration falls at the moment in time where the transitions between unchanged bits occurred when no additional bits are inserted; keeping the half duration point of all reduced data bits to the same place as they were in the unchanged message; keeping the total duration of the message containing the additional bits identical to the total length of the unchanged message. The process is compliant with the MIDI standard and allows the increase of the amount of various distinct messages which it is able to convey.

Abstract: A transceiver for a code division multiple access communication system comprises a receiver to receive coded information signals and a transmitter to transmit coded information signals. A local oscillator provides a time and frequency reference for the receiver and the transmitter. A timing controller provides timing signals for the receiver and the transmitter. A signal processor decodes received signals to determine a common error associated with the timing controller. A timing correction circuit smoothly adjusts the timing of the coded information signals transmitted by the transmitter responsive to the timing error to reduce the timing error over a desired time interval.

Abstract: A method and system for processing communication at a node in a communication system makes use a series of fixed-length data frames in which multiple data streams are multiplexed. Each of the data streams originates from a corresponding source of data in the communication system, and least two of the data streams originate from a same source of data. For each of the series of fixed-length frames that are processed at a node, multiple offsets within the fixed-length frame are identified, each of these offsets being associated with a different one of the sources of data. The data streams which are multiplexed in the series of fixed-length frames are then processed. For each of the data streams, in each of the series of fixed-length frames, that data stream is processed according to the offset identified for that frame that is associated with the source of that data stream.

Abstract: A digital switching system comprises: (a) a line card layer containing a plurality of real or virtual line cards; (b) a switch card layer containing a plurality of real or virtual switch cards; and (c) an interface layer interposed between the line card layer and the switch card layer for providing serialization support services so that one or more of the line cards and switch cards can be operatively and conveniently disposed in a first shelf or on a first backplane that is spaced apart from a second shelf or from a second backplane supporting others of the line cards and/or switch cards. Such an arrangement allows for scalable expansion of the switching system in terms of number of lines served and/or transmission rates served. The flexibility of the system is owed in part to payload data being carried within payload-carrying regions of so-called ZCell signals as the payload data moves between the line card layer and the switch fabric layer.

Abstract: A technique for embedding a first clock phase within a second signal is described. In one embodiment, the invention comprises a method of embedding a phase of a first signal within a second signal comprising the steps of monitoring a first signal for a frame event, responsive to detection of a frame event in the first clock signal, determining a position of the frame event relative to a current segment of a second signal, and embedding in the current segment of the second signal a value representative of the relative position of the detected frame event.

Abstract: The present invention provides a test bitstream generator and method for generating test bitstreams to test a bitstream decoder that is arranged to decode bitstreams generated in accordance with a predefined syntax. The method comprises the steps of generating test code from the syntax, the test code being arranged when executed to generate a test bitstream dependent on values assigned to a plurality of variables, each variable having a number of interesting values. The method then involves executing the test code, including the step of, for each of said variables, assigning that variable one of its interesting values, in order to thereby generate a test bitstream dependent on the interesting value assigned to each variable. It has been found that this technique provides an automated process for extensively testing a bitstream decoder.

Abstract: The invention relates to a method for finding frame alignment and accepting and monitoring TTI identifiers contained in frames in an SDH system. Advantageously the method according to the invention comprises steps in which frame alignment is first sought for by means of a frame alignment signal. When frame alignment has been found, it is monitored that it stays correct and at the same time at least one TTI identifier is read. According to the invention, at least one TTI identifier is saved from a frame after the finding of frame alignment. If a loss of frame alignment is detected, the TTI identifier saved is stored for a predetermined time. The invention further relates to an arrangement comprising means to implement the method described above in an SDH system.

Abstract: A method for performing discontinuous transmission in an asynchronous transfer mode is described, wherein a downlink transmission of an ATM cell is performed each time a predetermined number of signal frames indicating a speechless period has been supplied, and wherein an uplink transmission of an ATM cell is only performed when a signal frame indicating a useful information has been supplied. In the downlink transmission, an idle frame can be generated at the receiving end, when no ATM cell is received. In the uplink transmission, a signal frame indicating a useless information can be generated, when no ATM cell is received. Thereby, only those signal frames required at the receiving end are transmitted. Moreover, known transmission functions and elements of a synchronous transmission system can be used at the respective ends of transmission.

Abstract: A method and apparatus for digitizing multiple data streams having different clocks spreads an error due to clock drift is spread across many clock cycles in extremely small amounts. To combine two data streams, the method interpolates one or more samples between existing samples of one of the two data streams and then adjusts a number of samples of said one of the two data streams to maintain balance in a downstream synchronizing buffer. This occurs prior to combining the two data streams. The adjusting may be performed by adding or decimating samples from the interpolated samples. To combine two asynchronous data streams having clocks offset in frequency, first, a first data stream is clocked into and out of a first buffer using a first clock associated with the first data stream. Second, a second data stream is clocked into a second buffer using a second clock associated with the second data stream and clocking the second data stream out of the second buffer using the first clock.

Abstract: A technique for provisioning cross-connects in network switching environment includes writing a first set of data into a first memory element during a first time interval and writing a second set of data into a second memory element during a second time interval. The technique reads a portion of the first set of data from the first memory element during the second time interval and reads a portion of the second set of data from the second memory element during a third time interval, and determines the first, second, and third time intervals based on a format of the sets of data, with the first time interval ending before the second time interval begins, and the second time interval ending before the third time interval begins.

Abstract: The invention discloses a method for detecting priority of data frames comprising the steps of extracting (S1) a bit pattern from a predetermined position in a frame, comparing (S2, S3) the extracted bit pattern with a search pattern, and identifying (S4) the received frame as a priority frame in case the extracted bit pattern (BP) matches with the first search pattern (SP). By this method, the priority of a data frame can easily be detected. The invention also proposes a corresponding device for detecting priority of data frames.

Abstract: Synchronization and desynchronization of a data signal transported in a synchronous frame across a synchronous communications network, such as SONET/SDH, reduces waiting-time jitter. A timing estimate (F) indicative of a relationship between a data rate (f1) of the data signal and a reference frequency (f2) of the synchronous communications network is calculated and communicated through the synchronous communications network, for example in the Synchronous Payload Envelope of a SONET frame. The data signal is recovered using a desynchronizer Phase-Locked Loop steered by the timing estimate (F). The timing estimate (F) can be any one or more of: a ratio between the data rate (f1) and the reference frequency (f2); a difference between the data rate (f1) and the reference frequency (f2); and a phase difference between a recovered data clock signal associated with the data rate (f1) and a reference clock signal associated with the reference frequency (f2).

Abstract: Two computer systems in a network each have a local store that contains a copy of a data item that is to be synchronized. One of the computer systems may be, for example, a mobile device while the other may be a synchronization server. In order to determine whether to synchronize a data item, and what synchronization mechanism to use, one of the computer systems references a flexible set of rules that may be influenced by instructions from a network administrator or a mobile device user. The flexible set of rules takes into consideration the value of the data, the cost associated with synchronization, the security of the synchronization mechanisms, the security of the mobile device, as well as the location of the mobile user in dictating whether and how to synchronize.

Abstract: Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between controllers in a distributed or localized control system, which is employed in order to allow operation of such controllers to be synchronized with respect to time. Also disclosed are synchronization protocols and hardware apparatus employed in synchronizing control operations in a control system.

Abstract: The invention concerns non-contact smart cards and, more particularly in such cards, a circuit for detecting data frames and providing them with a parallel format for their processing. The invention is characterised in that it consists in using the information contained in the first octets of the frame being currently received, thereby enabling to identify them as they are received and route them into registers (80). This is provided by a state machine (60) whereof the shift from one state to the other is switched by the circuitry (62, 76) output signals.

Abstract: An apparatus and corresponding method for preventing data loss in network devices is disclosed. The present invention monitors an incoming data stream to a network device, or devices, and in the event that an error condition is detected, predetermined error data is inserted into the data stream, wherein the predetermined error data is provided at the same data rate as the recovered data rate internal to the network device. Thus, the network device will not have to adjust to a different data rate and potentially lose data during the adjustment period.

Abstract: The invention comprises a method and apparatus for reducing uncertainty in timing on the network. The uncertainty in receive buffers is removed by time stamping the arriving packets before sending the packets to the receive buffer. The uncertainty in the transmission buffer is removed by giving the packets a timestamp in the future, and holding the packets until precisely that time. Time precision is ensured by only releasing time packets at the host physical layer to network boundary at the time specified within the packet.

Abstract: A concatenated signal carrying an arbitrary mix of concatenated data traffic is split and transported across a network between a start node and an end node through a hyper-concatenated connection set up through independent pointer processor state machines. At a start node, the concatenated optical signal is split into two or more hyper-concatenated data streams. If a split occurs at a frame within a concatenated signal, the start node replaces a concatenation indicator of the frame with a payload pointer from a first frame of the concatenated signal and inserts a split indicator in the SS bits of the frame overhead. At an end node, the hyper-concatenated data streams are recombined to recover the original concatenated signal. Frames containing split indicators are modified to remove the split indicator and to replace the payload pointer with a concatenation indicator.

Abstract: A method and apparatus for recording digital data streams. When a digital broadcast data stream received by a set top box is transmitted through a communication interface such as an IEEE-1394 bus to a streamer, program clock references contained in the data stream become different from the actual arrival time of the digital data stream because of different clock frequencies of the digital data stream and communication interface. The difference is compensated before the digital data stream is recorded on the streamer. The method in accordance with the present invention comprises detecting program clock references contained in received digital transport stream packets, creating the transport time reference of each transport stream packet based upon the detected program clock references and arrival times of the transport stream packets, and creating transport stream units by adding each of the created transport time reference to the associated transport stream packet.

Abstract: A system and method are provided for synchronizing a frame of related bits output from a deserializer to the related bits serially fed to the deserializer. Synchronization is achieved by overcoming a slip bit problem by selectively increasing the frame clock cycle during times in which the slip bit occurs. The deserializer is controlled by a clock generator that can include a counter which generates the frame clock. The counter can be asynchronously or synchronously reset, without any glitches occurring within the deserializer and, thus, avoiding any invalid bits output from the deserializer. The asynchronous reset forces the counter to a deterministic state, and the synchronous reset sets the counter to a valid state. In each instance, however, resets do not impart glitches to the deserializer and the deserializer output frame is maintained synchronous to related bits serially fed to the deserializer.

Abstract: The invention provides a novel scheme to align data streams across multiple transmission channels and match multiple transmissions with one receiving rate. The channel aligning aspect of this invention detects the occurrence of an aligning character in a plurality of input channel character streams, buffers the character stream until an aligning character has been detected on every input channel. The channel aligning system transmits filler characters over every output channel corresponding to an input channel where an aligning character has been received if an aligning character has not been detected on every input channel. The aligning system then synchronously transmits the buffered characters, starting with the aligning character and proceeding with the subsequently received characters. The rate matching aspect of this invention receives a plurality of character streams synchronized by a first clock and buffers the character streams.

Abstract: A method and apparatus for alignment of TDM-based signals for packet transmission using framed and unframed operations are described. In an embodiment, a line card in a network element includes a deframer unit that receives a Time Division Multiplexing (TDM) signal. The TDM signal includes a payload and overhead data. The deframer generates frame alignment data based on the overhead data. The line card also includes a packet engine unit coupled to the deframer unit. The packet engine unit receives the payload, the overhead data and the frame alignment data and generates a number of packet engine packets. The packet engine packets represent a frame within the TDM signal such that the packet engine packets include the payload, the overhead data and the frame alignment data. Additionally, the line card includes packet processor coupled to the deframer unit. The packet processor receives the packet engine packets and generates network packets based on the packet engine packets.

Abstract: An apparatus for reducing the effects of pointer adjustments, wander, and jitter during desynchronization of a non-uniformly gapped data stream from a payload of a synchronized signal is disclosed. The apparatus utilizes a combination of two pointer adjustment signals embedded in the synchronized signal to determine a bit leak rate of bits from an elastic store following a pointer adjustment event such that the elastic store provides as an output a more-uniformly-distributed-gapped data stream.

Abstract: The present invention refers to methods and apparatuses for providing synchronization in a time division multiplexed network, wherein data is transferred on multi-access bitstreams in circuit-switched channels that are defined by respective time slots of regularly recurrent frames of said bitstreams, said frames being defined by regularly recurrent frame synchronization signals transferred on said bitstreams. According to the invention an auxiliary regularly recurrent frame synchronization signal is generated and selected as a basis for defining said frames on a bitstream if the frame synchronization signal that is used as a basis for synchronizing said frames during normal operation is not detected in accordance with an expected frame rate.

Abstract: Framing techniques for ADSL systems that allow programmable fixed overhead efficient framing and seamless rate changes.

Abstract: A system and method are disclosed for parallel compression and decompression of a bitstream. For compression, the bitstream is separated into a plurality of components, and the components are encoded using a compression algorithm. Packets are then constructed from the encoded components. At least one packet is associated with each encoded component and comprises header information and encoded data. The packets are combined into a packetized encoded bitstream. For decompression, the packets are separated from the packetized encoded bitstream using the header information. The packets are then decoded in parallel using a decompression algorithm to recover the encoded data. The plurality of components are reconstructed from the recovered encoded data and combined to recover the bitstream.

Abstract: A method and apparatus is described for providing rate adaptation between a first node and a second node in a data communication environment employing bit stuffing and having a link budget of B bits per second. One or more N-sized frames of user data are randomized at the first node according to a predetermined random sequence to produce randomized N-sized frames which are then de-randomized at the second node according to the random sequence. N is the size of the N-sized frames in bits. Occurrences of a flag sequence related event is detected for in the N-sized frames after randomizing, and up to n bits are inserted in the N-sized frames according to a bit stuffing protocol. By performing randomizing before inserting, n and N are selected such that n+N does not exceed B. The bits are then removed such that de-randomizing can be performed. Randomizing includes combining N-sized frames with a random sequence and de-randomizing includes uncombining the N-sized frames with the random sequence.

Abstract: According to telecommunication standards relating to communication networks supporting an Asynchronous Transfer Mode (ATM), timing information relating to a Constant Bit Rate (CBR) service needs to be communicated between a source network entity and a destination network entity. Typically, the timing information is obtained by measuring a phase of an incoming CBR stream of bits at the source network entity against a synchronous standard, such as a master clock signal. However, where the stream of bits comprises multiplexed services, it is difficult to measure the phase of the parts of the stream of bits relating to a service of interest without first demapping or demultiplexing the stream of bits. Consequently, the present invention overcomes this difficulty by counting justification event amongst the stream of bits, the count of justification events corresponding to timing information relating to the service of interest.

Abstract: A data communication circuit includes a decoder and an alignment buffer. The decoder receives and decodes parallel (N) bit channels into parallel (M+X) bit channels with signaling bits that indicate headers in the parallel (M+X) bit channels. The decoder transfers the parallel (M+X) bit channels to the alignment buffer. The alignment buffer recovers and aligns parallel (M) bit channels using the signaling bits. The alignment buffer generates a clock selection signal using the signaling bits. The alignment buffer transfers the aligned parallel (M) bit channels and the clock selection signal. The alignment buffer can have a length that is a multiple of a frame length for the (M) bit parallel channels.

Abstract: A method and apparatus for transferring information in a communications system is described. In one embodiment, the method comprises creating a frame of information on a first line card and sending the frame over a backplane to a second line card using a serial link interconnect. The frame comprises first, second and third portions. The first portion includes information to process the second and third portions. The second portion has packet and time-division multiplexed (TDM) data in multiple channels. Each of the channels is allocable to packet data or TDM data. The third portion includes data placed into the frame to accommodate for differences in timing references between the line cards.

Abstract: A communications system includes N parallel communications channels connecting first and second devices. The N channels may include N−1 channels for carrying information symbols, and an Nth channel for facilitating deskewing and word framing. The first device may include an alignment symbol generator for generating alignment symbols on the Nth channel, and a word framing code generator for generating word framing codes on the Nth channel. The second device may include a deskewer for aligning received information symbols based upon the alignment symbols, and a word framer for determining word framing based upon the word framing codes. The word frame code generator in the first device or transmitter, and the word framer in the second device or receiver provide the desired feature of knowledge of where each word starts or begins. The start of each word may be determined in terms of a time and a corresponding one of the N−1 channels where the word starts.

Abstract: Group-wise testing of the clocks arriving at a switching office is undertaken by multiplexing the clocks onto a single line and developing a signal therefrom that is indicative of a problem, if it exists, in any of the component signals that were multiplexed. In one embodiment, the developed signal is a gated portion of the multiplexed signal. That signal is integrated over an integration frame and compared to the integrated signal of another integration frame. A difference between the two compared signals indicates that at least one of the clocks is out of frequency synch. Subsequent tests identify the offending clock, or clocks.

Abstract: A system and method are provided for encoding and decoding a bitstream according to the High level Data Link Control protocol (HDLC) without having to analyze the bitstream bit by bit. An optimized encoder and an optimized decoder are provided. Both encoder and decoder analyze their respective input streams by using a number of bits in parallel as an index into a table, the contents of which control an action by the encoder or decoder that emits in parallel a number of output bits.

Abstract: Disclosed is a WDM network which has: a lightwave path which connects between clients and each of which is provided with an overhead, and a sub-network which is defined by dividing the WDM network. In this WDM network, the sub-network has a partial lightwave path to go through the sub-network, the overhead has a partial lightwave path supervisory control information region which is terminated at both nodes of the partial lightwave path, and when a fault occurs on a lightwave path, the fault information of partial lightwave path including the position information of fault occurred is added to the partial lightwave path supervisory control information region of the overhead.

Abstract: An address retrieval apparatus includes a retrieval table having plural table nodes for different hierarchical levels of a hierarchical tree structure, a divided bit string retrieval block, and a transfer destination distribution information acquiring block for acquiring a transfer destination distribution information from a transfer destination distribution information table based on a retrieval result supplied from the divided bit string retrieval block. An original bit string providing an inputted route information is divided into plural divided bit strings correspondent to respective brunches with the different hierarchical levels, thereby to do retrieval processes by a sequential use of the plural divided bit strings in the sequence from the bottom level to the top level with shifting up by one level the hierarchical level until the location designation information is retrieved.