Abstract: A transmission system is indicated for digital signals combined into a multiplex signal, and a network element for such a transmission system. Each network element contains an adapter circuit to balance phase variations in an incoming multiplex signal. The adapter circuit has a buffer memory (1) for payload data bytes, a write address generator (2) which controls the buffer memory (1) in a way so that a number of payload data bytes is stored within one write cycle, and has a read address generator (3) which controls the buffer memory (1) in a way so that the number of payload data bytes stored within the write cycle is greater than the number of payload data bytes read during the read cycle. Each network element has a sort facility (5) which sorts the read payload data bytes, so that a multiplex signal that is transmitted by a network element has the established frame format.

Abstract: A user network interface device for interfacing between synchronous optical network (SONET)/synchronous digital hierarchy (SDH) which is characterized by a continuous stream of frames of data and an asynchronous transfer mode (ATM) characterized by a non-continuous stream of cells of data. The user network interface device includes an integral phase lock loop circuit to recover clock and data from an encoded incoming stream of data. In another embodiment, the network interface device synthesizes a high speed transmit clock from a low frequency reference source.

Abstract: A reception device in the ATM communication apparatus has a format conversion buffer, an underflow detecting circuit, and an in-device empty cell insertion control circuit in each of the active and backup systems. The format conversion buffer effects a format conversion on a transmission path from a format in which an ATM cell is inserted in only the payload of an SDH frame to a format in which an ATM cell is inserted in both the overhead and payload of an SDH frame, thereby to absorb the difference between transmission path lengths of the active and backup systems. The underflow detecting circuit detects an underflow of the format conversion buffer and outputs a detected underflow signal. The in-device empty cell insertion control circuit outputs an in-device empty cell insertion instruction signal in response to a detected underflow signal from the underflow detecting circuit in one of the active and backup systems.

Abstract: A method and system for preventing information losses during alternative frequency searches by a receiving unit in a communication system in which data is channel coded, interleaved, and segmented into a plurality of frames. The method comprises the steps of discontinuing demodulation at a predetermined time before a frame ends, inserting zero values into the frame, and performing a search for alternative frequencies while continuing to insert zero values into the frame and then a next frame. After the search is completed, insertion of zero values is discontinued and demodulation is resumed. In one preferred version, the receiving unit comprises a mobile radio station operating at a serving frequency. The step of inserting zero values is followed by a step of programming the mobile radio station to a search frequency and waiting for the mobile radio station to settle.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: A timing signal supplying device in a doubled timing synchronous system includes: a timing signal adjusting portion which feeds back a timing signal of a timing signal receiving circuit and a frequency signal of a transmitting buffer to regenerate a timing signal and compares the timing signal with an external input timing signal to detect and correct an error of the timing signal; and a timing signal transmitting portion which sequentially transmits the corrected signal of the timing signal adjusting portion and the regenerated timing signal to the timing signal receiving circuit.

Abstract: A wireless telecommunications system (1) includes a central terminal (10) for transmitting and receiving radio frequency signals to and from a subscriber terminal (20). A downlink communication path is established from a transmitter (200) of the central terminal (10) to a receiver (202) of the subscriber terminal (20). A downlink signal (212) is transmitted from the transmitter (200) to the receiver (202) during setup and operation of the wireless telecommunications system (1) carrying information partitioned into a plurality of frames. The downlink signal (212) includes an overhead channel (224) having a frame alignment signal (232) for each frame of information. The receiver (202) monitors the downlink signal (212) to identify the frame alignment signal (232). The downlink communication path is established when the receiver (202) identifies two successive frame alignment signals (232).

Abstract: A rate alignment apparatus for a satellite includes an on-board clock, an input switch, an output switch and a ping-pong buffer pair including first and second buffers and connected to the input switch and the output switch. The first and second buffers receive a stream of digital baseband symbols recovered from an uplink signal depending on the operation of the input switch and the output switch. The first buffer of the buffer pair receives the bits in accordance with an uplink clock rate obtained from the uplink signal. The second buffer of the buffer pair substantially simultaneously empties the stored contents thereof to a third buffer in accordance with the on-board clock, the operations of the first and second buffers being reversed upon actuation of the input switch and the output switch. First and second correlators generate a spike when a header denoting when a frame in the stream of baseband symbols is detected.

Abstract: In optical path signal termination equipment which converts between an SDH signal transmitted at the electrical level and an optical path signal transmitted at the optical level, an optical path supervisory signal is inserted in the optical path signal without increasing the signal length. This is accomplished by utilizing the SDH section supervisory signal area contained in the SDH signal as the area for the optical path supervisory signal in the optical path signal.

Abstract: An apparatus, to be used in a desynchronizer, for minimizing the output jitter of the desynchronizer. The desynchronizer is assumed to include a bit buffer for staging data that is to be output. The desynchronizer is also assumed to include a means for decoding the input signal to determine how justification opportunities in the input signal are used and therefore what justification bits must be leaked by the desynchronizer. The apparatus and method of the present invention uses the information about the incoming justification bits or incoming justification bytes and the state of the buffer to determine the longest possible time to wait before issuing a command to momentarily speed up or delay outputting the next data unit from the bit buffer.

Abstract: A hub port in a hub which preferably eliminates the transfer of jitter in the signal transmitted to an attached node port. In one implementation, jitter transfer is preferably eliminated by transmitting data to an attached node port using a local clock internal to the hub rather than a clock signal recovered from the datastream. The hub port includes smoothing circuits to synchronize data received from the attached node port to the local clock.

Abstract: A method and apparatus for determining synchronization and loss of synchronization in a high speed multiplexed data system. The system also includes a plurality of justification control bits and a backwards compatibility flag that allows the system to operate with older systems that have fewer justification control bits.

Abstract: An apparatus for processing an order-wire signal capable of providing a high quality communication between operators through an order-wire channel for use in a synchronous add drop multiplexer(ADM) including a multiplexing unit and a de-multiplexing unit comprises: mixer for mixing two signals to generate a mixed signal, one being a voice signal of an operator at the ADM, the other being an order-wire signal received from a de-multiplexing unit in the ADM; detector for detecting a slip to generate a control signal and generating slip data; and selector for selecting one out of the mixed signal and the received order-wire signal to produce a selected signal, and transmitting the selected signal to the multiplexing unit in the ADM.

Abstract: A synchronism detection and demodulating circuit includes: a circuit for frequency dividing the regenerative clock in an irregular manner, a circuit for reading out the input data in a special manner based on the clock and producing data that provides information about the readout data, and a circuit for deleting unnecessary data from the readout data based on the data providing the information.

Abstract: A method and system for time aligning a frame (60) in a communication network (10) involves the steps of; i) determining if a frame needs to be advanced at a BTS (14), and ii) sending a shortened synchronization pattern from the BSC (12). The BTS (14) then determines if a short or long synchronization pattern has been sent by determining (256) if the received data stream matches a long synchronization pattern and setting a first flag when they do match. If the received data stream does not match the long synchronization pattern and the first flag is set (264), the data stream is compared (266) to the short synchronization pattern. When they match a second flag is set (268).

Abstract: A system is provided for encoding clips of video data for multiplexing into a system level stream with associated audio and control data. By deriving a relationship between encoder and decoder buffer occupancy levels, and taking into account buffer fill rate, the multiplexer targets a starting occupancy for the video system layer buffer (the MPEG STD) at that for the decoders video buffer (the MPEG VBV). With knowledge of fill rate, the decoder buffer need only be filled to a predetermined level prior to reading out clips for decoding, rather than filling the buffer completely, and seamless joining of video clips can then be simply achieved. The technique has particular application to interactive multimedia systems where continuous display is required.

Abstract: Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of each E1 signal are mapped into the space of one DS1 signal in the logical space. The remaining eight DS0 signals of every three E1 signal are then interleavingly mapped into the space of one DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals are mapped into the logical space in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.

Abstract: Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of the first E1 signal are mapped into the space of a first DS1 signal in the logical space. The 8 DS0 signals of the first E1 signal are then mapped into the space of a second DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals may be mapped into the logical space of two DS1 signals in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.

Abstract: A telecommunications transmission system carries multiple tributary data streams with SDH compatible multiplexing and demultiplexing arrangements that include a tributary justification algorithm utilizing both byte and bit justification means as well as a double-ended payload protocol. The byte justification means employs an offset clock with a nominal constant frequency offset from the transmission system clock so that the offset clock can be used to force regular rate of byte justifications of constant sign. The bit justification means employs the difference between the tributary clock and the offset clock to determine the bit justifications necessary to multiplex the tributary data stream and the bit justifications are normally of complementary sign to the forced regular byte justifications except where the frequency of the offset clock lies between the frequency of the transmission clock.

Abstract: A method of transferring payload, control and messaging data in a communications system, in a serial data stream at a pre-set bit rate per second is disclosed. The method comprises, transferring a chosen integer number of frames of serial data per second. Each frame comprises a number of timeslots of data. Each timeslot comprises a predetermined number of first bits comprising payload related data or messaging bits and a calculated number of second bits comprising control bits. The calculated number is calculated so that the sum of the predetermined number and the calculated number multiplied by the number of timeslots and the chosen integer number equals the number of bits transferred in one second at the pre-set bit rate. Preferably, bits from the second bits at fixed intervals within the serial data stream comprise a out-of-band communications channel with the stream. Preferably, the pre-set bit rate is synchronized to the clock of a host communications system.

Abstract: A radio relay apparatus complying with SDH is provided which permits the value of B2 bytes received from a transmitting-side terminal station to be sent to a receiving-side terminal station even in the case where resetting of a pointer value is performed. B2 sampling means of the radio relay apparatus samples B2 byte information, and B2 recomputing means again performs B2 parity computation of received transmission information which has been subjected to the pointer value resetting. Adding means adds bit by bit the data sampled by the B2 sampling means to the data obtained by the B2 recomputing means, and transmitting means transmits the sum obtained by the adding means to a subsequent radio relay apparatus. Based on the sum transmitted from the transmitting means, the subsequent radio relay apparatus judges that data which is a subject of B2 parity computation and which corresponds to a bit having the value "1" is erroneous.

Abstract: The present invention provides an apparatus of stuff synchronization frame control which can realize great improvement in the power of error resistance of the stuff synchronization control bit when there occur so many erroneous stuff synchronization control bits that cannot be repaired even by the majority process in a radio section. Radio-side and network-side clocks from the clock counters 11 and 12 are compared by the comparator 13, and the comparison result is inputted into the register 14. On an entry of a new stuff synchronization control bit into the register 14, the stuff synchronization control bit in the frame immediately before the entry is stored in the register 15. The multiplexer 16 multiplexes the stuff synchronization control bit together with transmission data for transmission. The separator 21 receives the data separated from the received data, in the received data buffer 22.

Abstract: A transmission system includes a matching circuit (2) for equalizing frequency and/or phase variations between an incoming and an outgoing frame-synchronized signal. The matching circuit (2) includes a buffer memory (5) to buffer the data of the signal, a write address generator (6) generating cyclic write addresses to control the writing in the buffer memory (5), and a read address generator (7) generating cyclic read addresses to control the reading from the buffer memory (5). The read address generator is provided to generate, during a predefined structure of each frame of the outgoing signal, at least a double read address if a control signal indicates a positive justification action, and is provided to skip at least one read address if the control signal indicates a negative justification action.

Abstract: A bandwidth-adaptive digital phase locked loop-based clock control arrangement controls the generation of a read-out clock used for retiming digital data signal interfaced with a synchronous data channel of a communication system, in which pulse-stuffing synchronization is employed to maintain clock synchronization of the digital data signal that is not bit-synchronous with a synchronous digital data channel over which the digital data signal is transported. The bandwidth-adaptive digital phase locked loop includes a loop filter to which the error signal is applied and a phase accumulator, coupled to the output of the loop filter and being operative to stepwise adjust the read-out clock signal. The loop filter has a first scaled path that includes a first, controllably stepped gain stage, and a second scaled path that includes a second, controllably stepped gain stage coupled to a frequency accumulator.

Abstract: A synchronous digital transmission system has network nodes each operating at a respective fixed internal clock rate, each with a justification device for adapting an incoming signal to the respective fixed internal clock rate thereof by positive or negative justification actions, and for controlling a memory device which stores payload bytes of a frame of the incoming signal and outputs the payload bytes at the internal clock rate of a respective network node. The justification device has a first circuit (10) for counting incoming/outgoing frame bytes and calculating at sampling instants (T.sub.i) a difference value (.DELTA..sub.i) and a change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i), has a second circuit (20) for calculating a control value (OFFSET) which is dependent on the change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i) and on a correction factor (LEAK), and has a third circuit (30) for comparing at the sampling instants (T.sub.

Abstract: A node in a synchronous communication network performs communication by sending and receiving frames formed by successively adding pointers showing header positions to a plurality of data, wherein a comparison is made between the values of pointers added to data received from an opposing node side and the values of pointers to be added to the data sent from a home node to detect if the two values coincide. Synchronization has been established between the opposing node and the home node when they do.

Abstract: A frame sync acquisition mechanism accurately locates a frame synchronization word within successive selectively bit-stuffed frames of data by not only looking for the frame sync word in the two expected alternative frame sync word locations based upon either the addition of stuff bits or the lack of such stuff bits, but also selectively examining a pair of additional potential locations, one of which precedes and the other of which succeeds the two expected alternative frame sync word locations. If an exact match with the frame sync word is located in either of the expected locations, that location is selected as the reference for the next succeeding frame. During the search of the next successive frame and for every succeeding frame, an attempt is made to initially match the frame sync word with in either of these expected locations. If unable to do so, the search is expanded to encompass the entire window of location uncertainty, so as to include the two additional locations.

Abstract: The present invention provides reconstruction and resynchronization of wireless serial transmissions which are subject to fading causing erroneous uncorrectable bit errors exceeding the error correction code correction capacity present in frames of digitally encoded data. Valid data is reconstructed in frames which are determined to contain at least one erroneous uncorrectable bit exceeding the bit error correction capacity of the error correction code therein which have all erroneous uncorrectable bits within the error correction code bit held. A synchronization marker is transmitted with each frame group which does not represent any valid data in a frame. Detection of the synchronization marker by a digital signal processor after at least one frame is determined to contain at least one erroneous uncorrectable bit, which is indicative of a loss of synchronism of the receiving circuitry clock, resynchronizes the clock of a processor of the receiving circuitry.

Abstract: A signal detection circuit receives a data stream containing a signal to be detected and detects the contained to-be-detected signal. The signal detection circuit includes a memory circuit prestoring data for detecting the to-be-detected signal, a first data feeder for feeding data to the memory circuit per given time slot as an upper address, and a second data feeder for feeding data to the memory circuit as a lower address using data outputted from the memory circuit. The memory circuit outputs data stored in a storage area defined by the upper address and the lower address fed from the first and second data feeders, respectively. By arranging the memory circuit to output a given value as the foregoing output data when the to-be-detected signal is detected, detection of the to-be-detected signal is achieved.

Abstract: A method for receiving a signal used in a synchronous digital telecommunications system, such as the SDH or SONET system, in which pointer interpretation is performed where a receiver has three possible main states, the receiver entering from one main state to another under the control of event number counting. The main states are a normal state, a loss of pointer state and an alarm state. The events including reception of a new pointer indicating a new pointer value, wherein the number of successive new pointers is counted, and, when being in the loss of pointer state, the normal state is entered after the new pointer has been received a predetermined number of times in success. To improve the recovery rate of data transmission, the counting of the new pointers is continued upon transition from the normal state or the alarm state to the loss of pointer state irrespective of the said transition.

Abstract: A network switch uses a simple switch core of analog MOS transistor switches. The switch core is surrounded by many media-access controllers (MAC's) which buffer the data through the switch core. Multiple connections through the switch core may be made between different pairs of MAC's. Just one signal path through the switch core is needed per connection as a second path through the switch core for the clock is not needed. The clock is not encoded with the data, so PLL's are not needed for clock recovery. Data skew is instead measured for each packet transmitted through the switch core. A start flag is added to the packet by a source MAC as a packet header before being transmitted through the switch core. The start flag is a unique sequence which is detected by the destination MAC and triggers measurement of the data skew of the received start flag to the local clock. The measured data skew is then used to compensate for the rest of the packet.

Abstract: A SONET formatter circuit (10) receives a parallel STS-1** TX signal (19) from a highspeed interface module. The STS-1** TX signal (19), which contains a floating VT group payload, is demultiplexed into seven parallel VT groups (33). These seven parallel VT groups (33) are converted to serial by a parallel to serial converter (34) and transmitted serially to lowspeed interface modules as DEMUX direction VT group data signals (42, 43). The SONET formatter circuit (10) also receives serial MUX direction VT group data signals (68, 69) from lowspeed interface modules. These serial VT group data signals (68, 69) are converted to seven parallel VT groups (89) by a serial to parallel converter (64). These seven parallel VT groups (89) are multiplexed with overhead data (84) into a parallel STS-1** RX signal (50) which is transmitted to a highspeed interface module. To maintain continuous VT group frame transmissions, a VT group clock generation circuit (72) is required.

Abstract: A method for locating a frame position in an MPEG data stream within a computer system is disclosed. MPEG standard is a set of defined algorithms and techniques for the compression and decompression of moving pictures (video) and sound (audio), and the formation of a multiplexed data stream that includes the compressed video and audio data plus any associated ancillary service data. Although the MPEG standard is extremely flexible, there is a fundamental deficiency associated with the packet-oriented nature of the MPEG format, and that is there being no information about the position of each video frame encoded in the data stream. Even though such information can be deduced from the byte-rate, but because the calculation of a frame position depends on a constant byte-rate, a problem may still arise when the byte-rate is non-existent, incorrectly encoded, or constantly changed due to the presence of several packs with varying rates.

Abstract: A bit insertion apparatus and method used to error encode data stored on data storage media monitors the number of bit insertions made on a given randomized block of data to determine if the number of bit insertions falls within the tolerable limits for storing the data. If the number of bit insertions is not tolerable, the pseudo-random code used to randomize the data stream is reconfigured. In a preferred embodiment, the bit insertion technique monitors the phase and amplitude content of the data stream and inserts appropriate bit patterns to ensure that phase and amplitude lock are maintained on the data stream for reading and decoding purposes.

Abstract: A system and method is disclosed for wireless transmission of information which is subject to fading by using a RF carrier modulated with a subcarrier modulated with the information. The system has a bus interface which communicates with a digital signal processor which controls the transmitting and receiving circuitry functions. The bus interface is for connection to a computer bus which is connected to a computer which originates information to be transmitted by transmitting circuitry and which receives information from receiving circuitry. The digital signal processor provides first and second encoded information streams each comprising the information to be transmitted with the second stream being delayed by a time delay interval with respect to the first stream which is equal to or greater than the fading interval. The first and second encoded information streams modulate cycles of the subcarrier to produce first and second parallel information streams which are time offset by the time delay interval.

Abstract: A computer system that is able to specify a packet size transmission rate is disclosed. The computer system has a plurality of nodes, each node being serially connected on a P1394 bus to at least one other node in the computer system. The nodes communicate one to another by transmitting communication packets having variable byte sizes over the P1394 bus. The packet size transmission rate is specified by first establishing an average transmission of bytes per packet. Next, the system determines an approximate value of the average transmission rate and, based on this value, determines a periodic change on the average transmission rate for transmitting communication packets of length l or length l+1. Once the periodic change is understood, the system selects a repeating pattern for generating a sequence of packets representing this approximate value. This sequence allows for an even transmission distribution of l and l+1 packets.

Abstract: In a method of interleaving and deinterleaving STM-1 and STM-N SDH frame pointers transmitted between a transmitter and a receiver, each frame comprising a section overhead area, a pointer area and a payload area including the data to be transmitted. At the transmitter, the bits of the pointer area and those of the payload area are interleaved according to an interleaving law retaining the position modulo 24 in the interleaved bits. The interleaving produces an interleaved frame transmitted to the receiver at which it is deinterleaved using a law that is the reciprocal of the interleaving law. This interleaves all the bits of pointers in the frame without changing the values of the B1 and B2 parity control bytes.

Abstract: A data communication system, such as a local area network, is provided with a capability of transmitting isochronous data. Preferably the system conveys both isochronous data and non-isochronous data by time-multiplexing the data into a recurring frame structure on a four-bit nibble basis. An efficient encoding scheme permits transmission of both isochronous and non-isochronous data over existing media, such as twisted pair, without degrading bandwidth previously achieved for non-isochronous data over the same media, such as using an ethernet system. Bandwidth available for a particular isochronous source/sink is selectable and sustainable with a predefined granularity. The arriving data is de-multiplexed at the hub into separate channels for handling the separate streams by appropriate hardware. Preferably, the present invention can be implemented in a fashion that is transparent to already-installed media access controllers.

Abstract: A method for disassembling or assembling a frame structure used in a synchronous digital data communication system, such as the SDH or SONET system. In order to enable the disassembly or assembly of frame structures with less hardware than previously, and to allow a more efficient use of RAM memory blocks in such processes, the interpretation and generation process of the pointers of at least two signals on the same level of hierarchy is carried out at least at one processing stage on a time-division basis in a unit common to the signals.

Abstract: A synchronization method for synchronizing a plurality of base stations in a TDMA communication system is disclosed. The synchronization topology may be via dedicated hardwire, via any DSL from the PSTN, or via an ad-hoc RF synchronization technique. Slots containing data are arranged in frames and these frames are transmitted to the base stations, and received from the base stations, by wireless telephone handsets. Each of the slots in a frame have a guard field comprising a plurality of guard bits. The base stations derive frame sync pulses via the received Unique Word correlation detect. These derived frame sync pulses are ultimately synchronized with frame sync signals received from the master base station.

Abstract: A phase-comparison bit synchronizing circuit for establishing bit phase synchronization of signals transmitted by way of TDMA can reproduce data properly even in the presence of disturbance. A plurality of phase shifting units shift the phase of a given burst signal in a received frame, and a bit phase synchronizing unit synchronizes the bit phases of output signals from the phase shifting units. A determining unit determines an optimum one of the phase shifting units, and a first selecting/outputting unit selects and outputs a signal which is produced when the given burst signal is shifted in phase by the optimum phase shifting unit. A memory unit stores the identification code of the phase shifting unit which is determined by the determining unit.

Abstract: Data capacity mismatches between a communication node, including end node work stations, and a communication link usually require large buffer storage to prevent the loss of transmitted data frames due to transmission of an incomplete frame. Transmitted data frame continuity is maintained in the present invention by using small FIFO buffers in the node to store small portions of a data frame as data is sent and received. In addition, the data frame is maintained by stretching the transmitted frame on the link when necessary to prevent loss of the frame and compress the stretched frame when it is received from the link. The stretching and compressing is accomplished by inserting and removing non-data symbols, or command code words, in the transmitted and received string of data words. Small FIFO buffers (much less than a data frame in data capacity) operate on the fly to transmit and receive data without requiring contiguous transmission of a complete frame.

Abstract: In one aspect of the present invention, a coding part of a transmitter side codes N series of input data into N+1 series of transmission data so that each of N+1 series of transmission data have frames and have the same transmission rates as those of the input data. For example, a bit transfer unit comprised in the coding part moves i-th bits of series i to the additional series N+1 where i=1 to N and a complement bit insertion unit inserts complements of an (N+1)-th bit of series 1 and (j-1)-th bits of series j into a first bit position of series 1 and j-th bit positions of series j, respectively, wherein J=2 to N. A frame signal insertion unit units alternate frame signal into the series N+1. BSI is secured by this simple construction.

Abstract: A bi-directional data transmission system that facilitates communications between a central unit and a plurality of remote units using a frame based discrete multi-tone (DMT) transmission scheme is disclosed. The discrete multi-tone data transmission system has a multiplicity of discrete subchannels including an overhead bus. In a method aspect of the invention, frames transmitted from the plurality of remote units are synchronized at the central unit. When a selected remote desires to initiate communications, it loop times it own clock to the clock of the central unit and transmits a remote initiated synchronization signal to the central unit over a dedicated overhead subchannel in the overhead bus. The central unit responds with a centrally initiated synchronization signal that contains information indicative of a frame boundary phase shift required to synchronize the selected first remote unit with other remote units that are currently communicating with the central unit.

Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and substrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

Abstract: A data stream provided to a DMT transmitter (114) is altered to produce an ordered data stream. The ordered data stream is produced by storing the data stream using a first addressing scheme, and then reading the data using a second addressing scheme. The ordered data stream is then converted in to a DMT symbol which is transmitted to a DMT receiver (112). The DMT receiver (112), using the first and second addressing schemes, recovers the ordered data stream and then the original data stream.

Abstract: A jitter/wander reduction mechanism monitors the ratio of pulse stuffing, to detect whenever the pulse stuffing ratio is proximate a prescribed undesirable ratio of stuffs per stuffing opportunity, which causes the wander to be a large number of unit intervals. A stuffing pulse accumulator-controlled frequency shift control circuit monitors the signal produced by a multiplexer (and demultiplexer for full duplex mode) control logic circuit and incrementally adjusts, as necessary, the frequency of a synchronized clock signal input to the multiplexer (and demultiplexer). The magnitude of the incremental frequency shift is sufficient to drive the synchronized clock away from the frequency associated with the undesired stuff ratio to a frequency that is sufficiently separated from the undesired value to produce a stuffing ratio other than the undesired value and reduce the jitter/wander.

Abstract: This invention relates to "clear pipe" communication networks meaning the nodes and links handle a variety of data frame types depending on their communication protocols such as Token Ring, Ethernet, FDDI or ATM. More particularly, this invention relates to node/link interface adapters at nodes which include switching nodes and end nodes. The adapters identify data frame type and adapt the node/link adapter operative elements to handle the various types of data frames as they travel through the network.The invention identifies the frame type at the source, flags the frame type to the nodes by use of unique SDEL (start delimiter) symbols or codes, uses the SDEL codes as received with the frame at each node to find the destination address in the frame and to adjust the transmission rate for the frame. The transmission rate is adjusted by inserting null non-data symbols in the frame to effectively slow the data rate to the data rate capacity of the protocol.

Abstract: Variable rate data is reformatted for communication to an external device at a fixed rate. Fixed length packets of the variable rate data are recovered from a multiplex of data packets. A packet start byte is added to the beginning of each of the recovered packets. Fill bits are added to the recovered packets as necessary to maintain the desired fixed output rate if the output rate is greater than an information rate of the variable rate data. The recovered packets with the added packet start byte and fill bits are provided as output to the external device at the fixed rate. The recovered packets with the added packet start byte and fill bits are advantageously encoded using alternate mark inversion (AMI) and binary eight zero substitution (B8ZS). The packet start byte and B8ZS substitution can comprise unique AMI violation sequences.

Abstract: A first station is connectable to a second station for transmitting a predetermined fixed amount of data to the second station over a predetermined time period to achieve a predetermined fixed data transmission rate. The predetermined time period consists of a plurality of constituent time periods. An amount of substantive data, which is less than the predetermined fixed amount of data, is transmitted from the first station to the second station in the predetermined time period by transmitting the substantive data during a portion of the constituent time periods and transmitting "null" data during the remainder of the constituent time periods. Thus, over the predetermined time period, the substantive data is transmitted at an effective rate that is less than the predetermined fixed data transmission rate.