Abstract: In one embodiment, a method includes receiving a synchronization signal from a computing device and determining a first time associated with detection of a first edge of the synchronization signal. The method also includes determining a second time associated with detection of a second edge of the synchronization signal and determining whether the second time occurs within a first predetermined window of time from the first time. The method further includes, if the second time occurs within the first predetermined window of time from the first time, then determining that the synchronization signal is valid.

Abstract: Methods and apparatuses are described for timing skew mitigation in time-interleaved ADCs (TI-ADCs) that may be performed for any receive signal without any special signals during blind initialization, which may be followed by background calibration. The same gain/skew calibration metrics may be applied to baud sampled and oversampled systems, including wideband receivers and regardless of any modulation, by applying a timing or frequency offset to non-stationary sampled signals during initial training. Skew mitigation is low latency, low power, low area, noise tolerant and scalable. Digital estimation may be implemented with accumulators and multipliers while analog calibration may be implemented with adjustable delays. DC and gain offsets may be calibrated before skew calibration. The slope of the correlation function between adjacent samples may be used to move a timing skew estimate stochastically at a low adaptive rate until the skew algorithm converges.

Abstract: An apparatus and a method of optimizing voice quality on a network having end-points that are voice over Internet Protocol (IP) devices. Default parameters of the end-points are initialized. Network performance parameters are measured and evaluated to determine whether they signify that connection to the network is below a desired level of operation. If so, the default parameters of the end-points are re-set based on the evaluation. The adjustment may entail re-negotiating the CODEC connection and re-setting parameters for packet size and resetting parameters for jitter buffer size.

Abstract: According to one embodiment, an apparatus includes a first processing unit operating according to a first clock, a second processing unit operating according to a second clock running separately from the first clock, and a synchronization controller coupled to the first communication unit and the second communication unit. The synchronization controller is configured to (i) cause the first communication unit to generate a first indication of time at which the first processing unit transmits a signal to the second processing unit, according to the first clock, (ii) cause the second processing unit to generate a second indication of time at which the second processing unit receives the signal, according to the second clock, and (iii) determine an offset between the first clock and the second clock based on the first indication of time and the second indication of time.

Abstract: Clock recovery for a data receiving unit is disclosed. Clock recovery can include obtaining an early/late signal from an incoming data stream. The early/late signal indicates if a set of one or more data samples of the incoming data stream tends to be earlier or later than an edge of a phase-rotated clock signal provided depending on a phase offset value. Clock recovery can include updating a phase rotation counter value in response to the early/late signal. Clock recovery can include determining the phase offset value depending on a rounded phase rotation counter value. The phase offset value can be further determined by selecting one of a set of options including maintaining, increasing, or decreasing the rounded phase rotation counter value. The selecting is performed depending on the early/late signal and depending on the phase rotation counter value.

Abstract: Methods, systems, and apparatuses are provided for performing joint source channel decoding in a manner that exploits parameter domain correlation. Redundancy in speech coding and packet field parameters is exploited to generate conditional probabilities that a decoder utilizes to perform joint source channel decoding. The conditional probabilities are based upon correlations of parameters of a current frame with parameters of the same or other frames or historical parameter data. Parameter domain correlation provides significant channel decoding improvement over prior bit domain solutions. Also provided are methods, systems, and apparatuses for utilizing received statistics of monitored data bits from which conditional probabilities are generated to perform channel decoding. The techniques described may be implemented at the decoder side and thus do not interfere with transmission standards.

Abstract: On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a circuit arrangement and a corresponding method are proposed, in which a full duplex data transmission is possible.

Abstract: This invention relates to methods and devices for time and frequency synchronization. The invention has particular application where time and frequency synchronization over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP) is being carried out. The primary challenge in clock distribution over packet networks is the variable transit delays experienced by timing packets, packet delay variations (PDVs). Embodiments of the invention provide a method for time offset alignment with PDV compensation where a synchronized frequency signal is available at a slave device via Synchronous Ethernet and is used to determine the compensation parameters for the PDV.

Abstract: A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N?1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

Abstract: This invention relates to methods and devices for frequency distribution based on, for example, the IEEE 1588 Precision Time Protocol (PTP). Packet delay variation (PDV) is a direct contributor to the noise in the recovered clock and various techniques have been proposed to mitigate its effects. Embodiments of the invention provide a mechanism to directly measure and remove PDV effects in the clock recovery mechanism at a slave clock. One particular embodiment provides a clock recovery mechanism including a phase-locked loop (PLL) with a PDV compensation feature built-in. An aim of the invention is to enable a slave clock to recover the master clock to a higher quality as if the communication path between master and slave is free of PDV. This technique may allow a packet network to provide clock synchronization services to the same level as time division multiplexing (TDM) networks and Global Positioning System (GPS).

Abstract: This invention relates to methods and devices for compensating for path asymmetry, particularly with reference to time and frequency synchronization. The invention has particular application where time and frequency synchronization over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP) is being carried out. Typically communication path delays between a time server (master) and a client (slave) are estimated using the assumption that the forward delay on the path is the same as the reverse delay. As a result, differences between these delays (delay asymmetries) can cause errors in the estimation of the offset of the slave clock from that of the master. Embodiments of the invention provide techniques and devices for compensating for path delay asymmetries that arise when timing protocol messages experience dissimilar queuing delays in the forward and reverse paths.

Abstract: Systems, devices and methods are described including specifying a jitter response control parameter, receiving multiple timestamp pairs. A maximum jitter of the timestamp pairs may be determined along with an elapsed time, and a clock frequency may be adjusted if the maximum jitter is less than the elapsed time divided by the jitter response control parameter. The jitter response control parameter may be adjusted in response to changes in die jitter of the input A/V signal. Further, one or more Proportional-Integral-Derivative (PID) controller coefficients may be adjusted in response to the evaluated jitter of the timestamp pairs.

Abstract: An appliance receives packets that are part of a flow pair, each packet sharing an application protocol. The appliance determines the application protocol of the packets by performing deep packet inspection (DPI) on the packets. Packet sizes are measured and converted into packet size states. Packet size states, packet sequence numbers, and packet flow directions are used to create an application protocol estimation table (APET). The APET is used during normal operation to estimate the application protocol of a flow pair without performing time consuming DPI. The appliance then determines inter-packet intervals between received packets. The inter-packet intervals are converted into inter-packet interval states. The inter-packet interval states and packet sequence numbers are used to create an inter-packet interval prediction table. The appliance then stores an inter-packet interval prediction table for each application protocol.

Abstract: A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.

Abstract: A method performed by a device for performing synchronization between devices for a Device-to-Device (D2D) communication is provided. The method includes setting, according to a process of the device, the device to a group of devices for performing a dynamic switching; outputting a synchronization signal corresponding to the set group as a signal for setting synchronization in a physical layer; controlling, upon receiving another synchronization signal from another device, the outputting of the synchronization signal by applying a time offset according to a relation between the set group that includes the device and the group that includes the another device; and setting, if the synchronization signal and the another synchronization signal are converged, synchronization of the device based on a time point where the synchronization signal is output.

Abstract: The disclosure generally relates to a shortened training field preamble structure for high-efficiency Wi-Fi environments. In one embodiment, the disclosure relates to a communication system having a transmitter transmitting a Master-Sync packet received by stationary and mobile receivers. The Master-Sync packet contains information for communicating in a HEW environment. Upon receipt each receiver decodes the Master-Sync packet to (i) estimate a frequency offset and/or an automatic gain control (AGC) setting; (ii) select a transmission frequency consistent with the frequency offset; and/or (iii) determine a new transmission power consistent with the AGC; (iv) tune to a new frequency offset and gain control setting to receive subsequent packets from the transmitter.

Abstract: An I2C interface is provided which has a data line and a clock line, the clock line having a first input buffer, and the data line having a second input buffer and an output buffer, the data line being provided for the transmission of a data input signal and a data output signal, the clock line being provided for the transmission of a clock signal, the clock line having a first delay element, and the data line having a second delay element and a third delay element. A method for operating an I2C slave interface is also provided.

Abstract: A communication function between ports on a node that does not require a common time base to be distributed across the network is disclosed. A data stream received over a first port is placed on an interface between nodes using the time base of the first port; a second port samples the data stream on the interface and timestamps it using the time base of the second port. The data stream is timestamped by the second port and packetized before transmitted to the second node to another bridge or device. Alternatively, the first port extracts a time stamp from the data stream and calculates an offset using a cycle timer value from the bus connected to the first port. The offset is added to the cycle timer value on the bus connected to the second port and used to timestamp the data stream.

Abstract: A method and system is provided for clock synchronization between two devices comprising a clock. The method comprises the following steps: a step of determining a duration necessary for transmission of a data packet between the two devices, a step of sending by one of the devices a data packet containing a sending time of this packet, and a step of determining the time by the other device by adding the transmission duration to the sending time of the packet.

Abstract: Methods, transmitter, receiver and computer program product for transmitting or receiving data of a real-time communication event, the data being transmitted from the transmitter to a jitter buffer of the receiver. At least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer in the real-time communication event is determined at the transmitter. Data is processed for transmission from the transmitter to the jitter buffer in accordance with the determined at least one processing parameter. Control information based on the determined at least one processing parameter is transmitted from the transmitter to the receiver, wherein the control information is for use by the receiver to control a state of the jitter buffer. The processed data is transmitted from the transmitter to the jitter buffer of the receiver in the real-time communication event.

Abstract: A receiver receives a first data stream and a second data stream from a transmitting device over a packet-based communication network, the first data stream being of a first media type (e.g. audio) and the second data stream being of a second media type (e.g. video). The first jitter buffer will buffer each of a plurality of portions of the first data stream as they are received via the receiver, and apply a de-jittering delay before outputting each portion of the first data stream (e.g. audio stream) to be played out through the receiving device. The jitter buffer controller receives information on the second data stream (e.g. video stream), and adapts the de-jittering delay of the first jitter buffer (e.g. audio jitter buffer) in dependence on the information on the second data stream (e.g. information on the video stream).

Abstract: A terminal of an exemplary transmitting device is configured to receive an initial clock signal. A first phase lock loop is configured to lock a phase of an initial periodic signal with a phase of the initial clock signal. A transmitting data block interface is configured to provide the plurality of data blocks with samples of the initial periodic signal to a receiving device. An exemplary receiving device includes a receiving data block interface configured to receive the plurality of data blocks. A second phase lock loop is configured to recreate the initial periodic signal and lock a phase of the recreated periodic signal with a phase of the samples of the initial periodic signal. The clock signal generator is configured to recreate and provide the initial clock signal. The recreated clock signal is synchronized to the initial clock signal based on the phase of the recreated periodic signal.

Abstract: HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital communications protocol, the audio quality can be impaired by analog signal impairments and distortions even if there are no digital decoding errors. In particular, the very process by which the audio is converted from Digital (HDMI) to human audible “Analog Audio” can be prone to errors. This occurs when the Digital to Analog Converter (DAC) clock, which is derived from the HDMI TMDS clock or HDMI source, is “distorted” due to its jitter, resulting in erroneous sampling or outputting of vital audio samples, thereby reducing the audio quality of the experience. The present invention reduces the jitter on the TMDS clock, and hence the audio DAC clock, resulting in lower audio distortion.

Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.

Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a recursive least squares mechanism for clock offset and skew estimation. A major potential advantage of such estimation is that it does not require knowledge of the statistics of the measurement noise and process noise. An implementation using a digital phase locked loop based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client) is also provided.

Abstract: Clock phase errors are detected and adjusted in a network with loop back connections for clock signals. In one embodiment, a method is performed in a ring network with slave clock nodes. A timing packet is sent from the master clock node to a first slave clock node of the ring. A timing packet is received from a last slave clock node of the ring. A phase alignment offset is determined by comparing a recovered time from the received timing packet with the time of the master clock node local clock and a phase correction value is determined for the slave clock nodes based on the determined phase alignment offset. A phase correction packet including the phase correction value is then sent from the master clock node to at least one of the slave clock nodes.

Abstract: A transmission method simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device.

Abstract: Methods and test equipment for measuring jitter in a Pulse Amplitude Modulated (PAM) transmitter. Under one procedure, a first two-level PAM signal test pattern is used to measure clock-related jitter separated into random and deterministic components, while a second two-level PAM signal test pattern is used to measure oven-odd jitter (EOJ). Under another procedure, A four-level PAM signal test pattern is used to measure jitter-induced noise using distortion analysis. Test equipment are also disclosed for implementing various aspects of the test methods.

Abstract: Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.

Abstract: A radio measurement apparatus comprising: an array antennal selection unit selecting array antennas corresponding to received signals; a reference path selection unit selecting a reference array antenna; a signal processing unit selecting a reference antenna channel through analysis of signal characteristics measured through two reception channels; a sequential channel multiplex unit determining sequentially inputting received signals of remaining array antennas to output the sequentially input signals to a receiver; and a correction signal input unit compensating amplitude and phase characteristics of the respective reception channels.

Abstract: In general, techniques are described for performing grant scheduling in optical networks. An optical line terminal (OLT) comprising a control unit may implement the techniques. The control unit determines an amount of upstream data associated with a category of service that is waiting at a first one of a plurality of ONTs to be transmitted upstream to the OLT and computes a number of GCPs for each of the ONTs based on a determined amount of data associated with the category of service that is waiting to be transmitted upstream to the OLT for each of the ONTs. After computing the number of GCPs, the control unit then grants time slots to the one or more of the ONTs based on the number of GCPs computed for each of the ONTs, wherein the time slots comprise time slots for upstream communication form the ONTs to the OLT.

Abstract: The methods and apparatus disclosed herein provide an operative system for increasing the resolution of serial DRUs based on interleaved free running oversamplers. In particular, this system uses incoming data to measure and to compensate the skew between two or more free running oversamplers (e.g., SerDes), without the need for any hardware design requirement relating to the precision of the relative skew of the oversamplers.

Abstract: A master device and slave devices are connected with each other through an SDA and an SCL, and at least one of a serial communication data signal communicated through the SDA and a serial communication clock signal communicated through the SCL is latched with use of a noise removal clock signal whose frequency is higher than that of the serial communication clock signal, and is taken in.

Abstract: In one embodiment, a battery-operated communication device “quick-samples” a frequency hopping sequence at a periodic rate corresponding to a substantially low duty cycle, and is discovered by (e.g., attached to) a main-powered communication device. During a scheduled sample, the main-powered communication device transmits a control packet to be received by the battery-operated communication device, the control packet containing timing information and transmitted to account for worst-case clock drift error between the two devices. The battery-operated communication device responds to the control packet with a link-layer acknowledgment containing timing information from the battery-operated communication device. Accordingly, the two devices may re-synchronize their timing based on the timing information in the control packet and acknowledgment, respectively.

Abstract: The present invention relates to a method of operating a communications network, comprising the steps of: receiving a plurality of packets from a network node; determining a first parameter based on the time period between the reception of a packet and the reception of the subsequent packet; determining a second parameter based on the variation of the first parameter; and determining the performance of the communications network in accordance with the ratio of the second parameter to the first parameter.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: There is provided a transmitting device including a packet signal generation unit configured to generate a packet signal of a video; a transmitting unit configured to transmit the packet signal via an asynchronous transmission network; a timing generation unit configured to generate a video frame synchronization signal on the basis of a reference signal acquired from a reference signal source; and a timing adjustment unit configured to, on the basis of the frame synchronization signal, perform adjustment so that a transmission timing for the packet signal is different from a transmission timing for a packet signal at another transmitting device.

Abstract: A system is provided and includes a buffer, an interface, a processor, and an output device. The interface is configured to receive a packet from a network. The processor is configured to: determine a delay of the network in transmitting the packet; prior to storing the packet in the buffer, determine statistics of the buffer, and an amount the buffer is filled; determine a predetermined delay of the buffer based on the delay of the network, and the statistics; estimate an actual delay of the buffer for the packet based on the amount the buffer is filled; generate an error signal based on the predetermined delay and the actual delay; and based on the error signal, one of compress and expand the packet to change a first length of the packet to a second length. The output device is configured to output the packet based on the second length.

Abstract: A system including a receiving module in a device and receiving samples of data transferred from a data source. A memory stores the samples and timestamps when the data was sampled. A host module builds a frame including the samples based on a first timestamp and a predetermined latency period between the first timestamp and a second timestamp in a descriptor of the frame. The second timestamp indicates a time when the frame is expected to be received by a MAC module. A transfer module transfers the frame to the MAC module according to the second timestamp. A detector module determines a margin of latency based on a difference between a time subsequent to when the frame is finished being built and a time when the frame is received at the MAC module. The detector module updates the first predetermined latency period based on the determined margin of latency.

Abstract: In one embodiment, an apparatus for providing clock synchronization in a packet-based network, the network having as components nodes and links therebetween and having a network topology, is arranged to compute a forward clock synchronization packet path to a synchronization destination from the network topology according to a computation rule such that the return path for a clock synchronization packet from the synchronization destination is the same as the forward path.

Abstract: Method, device and system for detecting a disturbance, e.g., at least one short mechanical impact (shock or vibration) on a clock of a slave device by detecting a non-typical variation of a tracking error, i.e., a tracking error having a deviation that exceeds a predetermined threshold, wherein such a non-typical variation can be determined by the deviation from a statistical measure, e.g., a variance or a standard deviation, such that the determination of the quality of a clock signal is advantageously allowed and thus suitable counter-measures are provided. The method, device and system are applicable for all kinds of technical systems comprising slave devices that have a clock, e.g., devices in industrial and automation systems. The method, device and system are also applicable in communication systems that use a protocol to synchronize the clocks of its devices, e.g., Profinet.

Abstract: The present invention provides a noncontact interface technique capable of performing communication operation without stopping an internal operation even when a clock signal cannot be extracted from a carrier wave. In a semiconductor device that receives a modulated carrier wave from an antenna, generates an internal clock signal on the basis of a clock signal extracted from the received carrier wave, and performs operation synchronously with the internal clock signal, a PLL circuit that receives the extracted clock signal and generates the internal clock signal is provided with a voltage control oscillation function. In the case where the clock signal extracted from the carrier wave is discretely interrupted, the function makes the internal clock signal maintained at a frequency immediately before the interruption. With the configuration, even when the clock signal extracted from the carrier wave is interrupted, internal data processes such as decoding and bus interfacing can be continued.

Abstract: An exemplary embodiment of the present disclosure illustrates a clock rate control method. Firstly, a usage of a first input first output (FIFO) buffer in an electronic device is detected. Then, whether the usage falls within a first specific interval is determined, wherein the first specific interval has a first upper limit value and a first lower limit value. When the usage is larger than the first upper limit value, a clock rate of the inner device of the electronic device is increased; when the usage is less than the first lower limit value, the clock rate is decreased.

Abstract: A transmission apparatus for transmitting frames accommodating client data over a transmission network, comprising a clock generation unit that generates a clock for timing processing period of signal processing, a deviation detection unit that detects clock deviation between the clock generated by the clock generation unit and the clock used for timing processing period of signal processing by other transmission apparatus that receives the client data from outside the transmission network and adds them to frames, and a timing generation unit that generates timing signal of processing period of signal processing corrected with the clock deviation.

Abstract: A node device includes a processor, a wireless RF circuit, a memory, and a timer. The processor measures a clock time. The wireless RF circuit receives a clock time information frame containing clock time information used for correcting the clock time. The memory stores a transmission processing time period, as a fixed value, from when a transmission source node device of the clock time information frame obtains the clock time information until when the transmission source node device transmits the clock time information frame. The timer measures a reception processing time period, which is a period of time from when the clock time information frame is received until when the clock time information is obtained. The node device sets to the processor a value obtained by adding the fixed value and the reception processing time period to the clock time information.

Abstract: A transmission method simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device.

Abstract: A system for compensating for periodic noise in a time interleaved system having multiple phases of interest includes a master clock path, a detection circuit and an actuator circuit. The master clock path is configured to receive an input clock and to output an output clock, each of the input and output clocks having periodically occurring interleaving periods. Each interleaving period includes timeslots corresponding to the phases of interest of the time interleaved system. The detection circuit is configured to receive the input and output clocks for each timeslot, and to detect periodic noise in the output clock introduced by the master clock path by comparing the received input and output clocks. The actuator circuit includes a controllable delay element configured to adjust a delay of the input clock through the master clock path to compensate for the periodic noise detected by the detection circuit for each timeslot.

Abstract: In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship.

Abstract: In an OFDM transmission a transmission diversity technique is used without orthogonal signaling. The phases of the subcarriers received at the different antennas are compared by different techniques and then the phases of the signals for different antennas are adjusted for a subsequent transmission over the OFDM interface. The phase (and optionally amplitude) adjustment is calculated in only one (transmitting) side and no orthogonal signaling required. The number of antennas can be increased as much as necessary to get a sharper beam. The negative effects of fading and interference can be reduced so that at same time a down link transmission power can be reduced.