Abstract: Transfer of differential timing over a packet network is provided. A transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: A communication terminal includes first and second transmitters, which are coupled to produce respective first and second Radio Frequency (RF) signals that are phase-shifted with respect to one another by a beamforming phase offset, and to transmit the RF signals toward a remote communication terminal. The terminal includes a reception subsystem including first and second receivers and a phase correction unit. The first and second receivers are respectively coupled to receive third and fourth RF signals from the remote communication terminal. The phase correction unit is coupled to produce, responsively to the third and fourth RF signals, a phase correction for correcting an error component in the beamforming phase offset.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: A communication system and method is disclosed that performs symbol boundary synchronization by generating a symbol alignment estimate from a partial signal correlation; and then refining the symbol alignment estimate via a carrier phase calculation. To generate the symbol alignment estimate, two methods are disclosed. After an estimate is determined, an embodiment provides for refining the symbol alignment estimate via a carrier phase calculation by determining a carrier phase of two adjacent carriers, determining a phase error as directly proportional to an offset from the start of a symbol, determining a phase difference contribution due to a communication channel and device hardware, and counter-rotating the determined carrier phase by an angle of a constellation point at a transmitter.

Abstract: Communication methods and apparatuses are provided.

Abstract: In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit configured to provide a feedback signal to a driver IC. The IC system also includes the driver IC configured to receive a second clock signal and includes a waveform generator configured to provide synthesized waveforms from DC to K-band, a serializer/deserializer (SERDES) to receive data from the waveform generator and to provide the signal to the receiver IC and a phase selection circuit to provide a phase selection signal to the first integrated circuit based on the feedback signal. The phase selection signal calibrates the signal from the SERDES and provides phase correction to the SERDES.

Abstract: An electronic device includes a transmission module communicatively coupled to a synchronizer. The transmission module is configured to transform received data for transmission, receive a first instruction from the synchronizer, based on the instruction adjust the phase of a clock signal used to time the transformation of the received data, and send the adjusted clock signal to the synchronizer. The synchronizer is configured to receive the adjusted clock signal, receive a data signal comprising a frequency and a phase of data to be transmitted, based on the adjusted clock signal and the data signal, determine a second instruction for the transmission module, and provide the second instruction to the transmission module.

Abstract: The invention relates to audio signal processing and speech enhancement. In accordance with one aspect, the invention combines a high-quality audio program that is a mix of speech and non-speech audio with a lower-quality copy of the speech components contained in the audio program for the purpose of generating a high-quality audio program with an increased ratio of speech to non-speech audio such as may benefit the elderly, hearing impaired or other listeners. Aspects of the invention are particularly useful for television and home theater sound, although they may be applicable to other audio and sound applications. The invention relates to methods, apparatus for performing such methods, and to software stored on a computer-readable medium for causing a computer to perform such methods.

Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

Abstract: A Relay Station (RS) is provided. The RS is adapted to operate in a TDD type of wireless communication network which comprises at least one base station (BS) operative to communicate with the RS and with an IP network, and a plurality of Mobile Subscribers (MSs). The RS comprises: a subscriber terminal operative in conformity with IEEE 802.16e Standard; and a BS operative in conformity with said IEEE 802.16e Standard, and wherein that subscriber terminal and that BS that belong to the RS are connected to each other, and wherein all communications transmitted from the at least one BS to the RS are in conformity with the IEEE 802.16e Standard.

Abstract: In a method of recovering timing information over packet networks, raw network delays are measured using timing packets sent between a transmitter and receiver. The expected delay is predicted using a minimum statistics adaptive filter to track local minima of measured time delays over a smoothing window. Only those incoming timing packets which meet a particular criterion relative to the expected delay within a smoothing window are selected, and a local clock is adjusted based on the measured timing delays from the selected timing packets.

Abstract: A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data.

Abstract: A signal processing circuit for controlling reading of segment data from a buffer in which a plurality of segment data generated by dividing a frame and received via a plurality of switches which direct each of the segment data to a designated destination are stored, comprises: a start detecting unit which detects a starting segment representing the first transmitted segment data to the switch among the segment data received after the buffer has emptied; a transmission time acquiring unit which acquires a transmission time at which the starting segment was transmitted to the switch; and a read timing control unit which determines, based on the transmission time, a read timing for reading the segment data from the buffer.

Abstract: A method, system and master service interface transfer differential timing over a packet network. The transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface.

Abstract: Embodiments of the present invention set forth a method and system for reducing uncertainty in receive and transmit timestamps created by an NTP server. The uncertainty in the receive timestamps is removed by recording the time-of-arrival in the hardware clock of the NTP server before the incoming packets may be delayed by traversing the various layers of software in a timestamping system. The uncertainty in the transmit timestamps is removed by giving the outgoing packets a timestamp in the future using an estimate of the transmission latency calculated by the latency estimator filter. Subsequently, the actual time-of-departure is used to re-calculate and update the estimate of the transmission latency. In this fashion, superior control of the timestamping function may be implemented in existing NTP servers in a manner that retains interworking compatibility with the current NTP standards.

Abstract: It is a basic idea to determine the characteristics of a jitter profile measured over a plurality of packets, and classify the jitter profile based on the determined characteristics as well as information representative of the particular access used for communication between the sender and the receiver. The classified jitter profile is then matched to an appropriate action for media layer adaptation so that a proper action for media layer adaptation can be initiated.

Abstract: Signal quality of a composite received signal in a radio communication network is optimized by adjusting a phase offset between received and/or transmitted signals based on signal quality parameters of the received and/or transmitted signals. The phase offset is adjusted by varying the phase offset between the received or transmitted signals such that that the composite signal is circularly, elliptically, or linearly polarized. The phase offset between the received or transmitted signals is continually adjusted based on the received signal quality parameters.

Abstract: A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal.

Abstract: A device is described for receiving data transmitted using asynchronous data transmission technology, in particular audio and video data, which receives a clock signal, having a memory device (17), which stores the received data for the required period of time in order to compensate for transmission delays (Cell Delay Variation). The clock signal is sent to the memory device (17) for reading out the data. Furthermore, a method is described for receiving data signals using asynchronous data transfer technology, with the received data signals being temporarily stored and read out at the studio clock rate.

Abstract: A communications network includes multiple distributed nodes that are coupled by a circuit-switched network. To improve efficiency, a plurality of the nodes are associated with a single source synchronization block that injects timing messages over circuits in the circuit-switched network to the plurality of nodes. Each of the plurality of nodes is associated with a timing extraction and recovery block that extracts information from the timing messages injected by the source synchronization block to synchronize a local clock in each node to the frequency and phase of a clock received by the source synchronization block.

Abstract: Method, transmitter and computer program product for transmitting data of a real-time communication event from the transmitter to a jitter buffer of a receiver. Jitter buffer state information is received at the transmitter from the receiver, the jitter buffer state information indicating a state of the jitter buffer. At least one processing parameter is controlled based on the received jitter buffer state information, the at least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer in the real-time communication event. Data is processed for transmission from the transmitter to the jitter buffer in accordance with the determined at least one processing parameter. The processed data is transmitted from the transmitter to the jitter buffer of the receiver in the real-time communication event.

Abstract: Methods, transmitter, receiver and computer program product for transmitting or receiving data of a real-time communication event, the data being transmitted from the transmitter to a jitter buffer of the receiver. At least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer in the real-time communication event is determined at the transmitter. Data is processed for transmission from the transmitter to the jitter buffer in accordance with the determined at least one processing parameter. Control information based on the determined at least one processing parameter is transmitted from the transmitter to the receiver, wherein the control information is for use by the receiver to control a state of the jitter buffer. The processed data is transmitted from the transmitter to the jitter buffer of the receiver in the real-time communication event.

Abstract: A method and system of fine timing synchronization for an OFDM signal. The OFDM signal is coarse timing synchronized, generating a synchronization sequence and a CFR (Channel Frequency Response). The synchronization sequence is removed. A correlation coefficient of the correlation between the CFR applied to a number of carriers and the number of carriers with different window shifts is calculated. The largest window shift corresponding to a downsampling factor is indicated by the lowest correlation coefficient greater than a threshold. The CFR is downsampled by the downsampling factor, and an inverse FFT is performed on the downsampled CFR with a reduced number of calculations reduced by the downsampling factor, transforming the CFR into a CIR. A fine timing synchronization position is determined from the CIR and is utilized by an FFT unit within an OFDM receiver to accurately receive OFDM symbols of the OFDM signal.

Abstract: A system recovers a local media clock from a master media clock based on time-stamped packets received from a transmitter. The packets may include audio, video, or a combination of both, sampled at a rate determined by the master media clock at the transmitter. Timestamps in the packets may be based on values of a remote real-time counter at the transmitter that is synchronized with a local real-time counter at a receiver. The local media clock may be syntonized with the master media clock through the clock periods. The clocks may be synchronized by syntonizing the clocks and adjusting the phase of the local media clocks based on timestamps and a real-time counter.

Abstract: A method of transmitting audio data across a digital interface is provided. The method includes receiving audio data, organized as a plurality of audio samples. At least one of the plurality of audio samples may be placed into a data packet. The data packet may be transmitted during a valid transmission interval if the data packet is full or during a valid transmission interval in response to receiving a packet send event.

Abstract: An improved system and method for achieving high precision clock recovery, i.e. reconstruction of the clock signal having the same frequency, over a packet switched network. The proposed method utilizes a minimum network delay approach, which overcomes the problems caused by delay variation of the network and filters out network jitter, such as noise jitter and other “singular” anomalies causing latency deviations. Minimum network delay is defined herein as the time delay in which a packet remains in the network under assumption that all transmission queues through which the packet passes are empty. The proposed system and method perform clock recovery by including an improvement in the form of dynamically varying thresholds. Reconstruction of the clock signal is performed in accordance with the minimum network delay estimation based on an adjustable threshold, i.e., the latency change threshold, which increases when the noise threshold increases and decreases when the noise threshold decreases.

Abstract: A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.

Abstract: An apparatus and method for managing clock domain(s) crossing several communication networks are disclosed. In one embodiment, a process capable of managing clock domains receives a data stream over a circuit emulation service (“CES”). Upon storing the data stream in a traffic buffer, the process selects a first clock domain for processing the data stream in the traffic buffer. For example, the process is capable of using the first clock domain to process and/or empty a jitter buffer, which stores CES data packets. The traffic buffer is monitored and the first clock domain can be replaced with a second clock domain if the storage capacity of the traffic buffer indicates that a different clock domain is needed.

Abstract: The present invention provides a method for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The present invention provides a method for generating jitter test patterns by disabling the transmitter data scrambler of the second device; clearing the port_error register of the device under test; and sending a test pattern to said device under test. The present invention provides for a method for generating supply noise test patterns comprising: transmitting a test pattern to the DUT comprising a maximum length asynchronous packet containing alternate 0016 and FF16 bytes.

Abstract: One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer.

Abstract: Network timing is derived from the PSTN and distributed through the network to gateways capable of deriving timing from the incoming UDP stream. The derived timing has the correct frequency for voice telephony without using external timing sources or extraneous hardware components. For example, a digital signal processor (DSP) can derive the timing from a timed TDM bus and distribute messages, such as IP messages, to other gateways or port networks. The other gateways and port networks use the incoming stream to extract the timing which is then used to time their TDM bus. The port networks and gateways can also distribute other streams to other gateways in a fan-out type of arrangement. This internally generated timing can be used, for example, for Circuit Emulated Services (CES).

Abstract: One embodiment is a source router that monitors the performance of an Ethernet network. The source router generates an Ethernet connectivity check request frame that includes a transmission timestamp, and transmits the Ethernet connectivity check request frame to a destination router. The source router receives a reply from the destination router that is transmitted in response to receiving the Ethernet connectivity check request frame and determines a round trip time between the source router and the destination router based on a time of receipt of the reply and the transmission timestamp.

Abstract: In one embodiment, an adaptive clock recovery (ACR) system generates a current delay-offset estimate value (DOE(i)) using a window technique that selects the larger of (i) the maximum delay-offset value (DOP) in the previous window and (ii) the maximum delay-offset value so far (DOM) in current window. This windowing technique can be implemented without having to store all of the individual values over a specified window size, as in a conventional sliding window technique. This windowing technique can be used to find extreme (i.e., either maximum or minimum) values for applications other than ACR systems.

Abstract: Disclosed is a frame synchronizing device and method for a binary data transmission system wherein digital data are transmitted as a serial bit stream organized into frames, each frame including a pre-defined frameheader, wherein said serial bit stream is inputted into a serial input portion of a serial input parallel output shift register means having at least as many stages as the number of bits of a frame, and said frames are outputted in a consecutive order from a parallel output portion of said shift register means. The particularity of the present invention is that it is detected whether or not a frameheader is present in the output of said parallel output portion, and, if not, the outputting of a frame from said parallel output portion is delayed by at least one time period which is needed for shifting a bit in said serial input portion from a stage to a next one, until synchronization is reached.

Abstract: Buffering is made more efficient by resizing a jitter buffer based, for example, on a user's location within a TUI. To illustrate how this might be implemented in a TUI-based system, assume that two jitter buffer sizes are available: a larger one for voice and a smaller one for DTMF. Assume that the ability to select the buffer size is software-controllable. By virtue of the TUI structure, the initial state for a communication session could be a buffer size appropriate for DTMF. Since the messaging system may provide an audible beep whenever it's appropriate for a user to speak, the same sub-routine within the TUI code that triggers the beep could also command the buffer management mechanism instructing it to size the buffer for voice. Any subsequent DTMF entry or other event indicating that voice input has been terminated could cause the buffer to resize appropriately for DTMF.

Abstract: A method of receiving at a terminal a first signal transmitted via a communication network, said method comprising the steps of; receiving at the terminal the first signal comprising a plurality of data elements; analysing characteristics of the first signal; receiving from a user of the terminal a second signal to be transmitted from the terminal; analysing characteristics of the second signal to detect audio activity in the second signal; and applying a delay between receiving at the terminal and outputting from the terminal at least one of said plurality of data elements; and adjusting the delay based on the analysed characteristics of the first signal and on the detection of audio activity in the second signal.

Abstract: A jitter buffer control apparatus has a buffer for storing data included in an input packet transmitted from a telecommunications network, and a jitter buffer controller for controlling the buffer to store the input data into the buffer and take out the stored data from the buffer on the basis of a sequence number included in the input packet in a processing period. When under-running occurs in the buffer, the jitter buffer controller stores input data into the buffer with a storage location skipped which corresponds to the processing period associated with packet loss due to the under-running.

Abstract: A method of exchanging a round trip time between a transmitting device and a receiving device in a wireless network comprises receiving an echo request command from an audio video control (AVC) layer to a medium access control (MAC) layer, the echo request command including a first identifier for identifying the transmitting device, a second identifier for identifying the receiving device, and a third identifier; transferring a MAC message from the MAC layer to a physical layer, the MAC message including a message preamble, a message type, and the echo request command; transmitting a first physical layer data unit to the receiving device, the first physical layer data unit including at least one header, the MAC message, and audio/video (A/V) data; and receiving a second physical layer data unit from the receiving device, the second physical layer data unit including an echo report command in response to the echo request command, the echo report command including the third identifier.

Abstract: To provide a communication apparatus and a packetization period change method that allow a packetization period/TDM period to change during a service of a TDM-PW system without affecting the service traffic, there is provided a communication apparatus that receives packetized data converted from TDM data, including a period information detection unit, a jitter buffer that stores the packetized data for a certain period of time, and a jitter buffer capacity control unit. The period information detection unit extracts packetization period information indicating a period to packetize TDM data contained in the received packetized data and acquires a TDM period to time-division multiplex the packetized data based on the packetization period information. The jitter buffer capacity control unit receives the acquired TDM period and controls a capacity of the jitter buffer in accordance with the TDM period.

Abstract: Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.

Abstract: In accordance with a representative embodiment, a method for reducing the effect of jitter in a sampled signal is described. The method comprises: obtaining a frequency-domain data set representing the sampled signal; obtaining an average sideband amplitude distribution generated by jitter around one or more principal frequencies of the signal; estimating the jitter phases for sidebands generated by jitter in the frequency-domain data set; subtracting a jitter contribution characterized by the average sideband amplitude distribution and the estimated jitter phases from the data record.

Abstract: A method and device for performing skew detection on data transmitted over a data channel and a high speed optical communication interface including the device are disclosed, wherein data of a reference frame over a reference channel is composed sequentially of a reference data segment with a length of Umax over each of data channels to be subject to skew detection.

Abstract: Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

Abstract: Apparatuses and methods for multiplexing of DS1 traffic across wired and wireless Ethernet devices. A transmitter sends data packets to a receiver through an Ethernet system. The transmitter includes a modeling module that constructs a modeled jitter buffer corresponding to a receiver jitter buffer located at the receiver. The transmitter also includes a packetizing buffer that collects data to form data packets, that inserts buffer pointers into the data packets, and that sends the data packets through the Ethernet system. A buffer pointer is determined from the modeled jitter buffer. The receiver includes an Ethernet interface module that obtains the data packets from the Ethernet system, a jitter buffer, and a depacketizer that reads a buffer pointer in the data packet and that places the data packet into a position within the receiver jitter buffer in accordance with the buffer pointer.

Abstract: A basestation for a cellular communication system has an interface, for connection to a computer network, and also includes an oscillator, for generating wireless transmit and receive frequencies. A controller receives timestamped response messages from a time server over the computer network, each response message being subject to a network propagation delay, which is a sum of a minimum network propagation delay and a jitter component. For each received response message an apparent network propagation delay is determined as a function of a difference between a first timestamp applied by the time server and a second timestamp based on a clock derived from said oscillator. A subset of the received response messages are selected, whose network propagation delays include minimal jitter components. The frequency accuracy of the oscillator is then determined based on changes over time in the apparent network propagation delays of the selected received response messages.

Abstract: A method, arrangement, and transceiver for monitoring noise on a twisted pair cable adapted to transfer Digital Subscriber Line (DSL) signals with a given data symbol rate. A spectrum analyzer measures the power spectral density of a background or substantially pure noise signal. A switch and frequency detector determine whether the background pure noise signal includes repetitive impulse noise, and if so, a processor calculates the pulse width of the repetitive impulse noise utilizing an established relationship between the given data symbol rate and the frequency of the repetitive impulse noise given by the power spectral density measurements.

Abstract: A system and method for low-cost performance and compliance testing of local oscillators and transmitters for wireless RF applications. A preferred embodiment comprises observing a digital signal from within an RF circuit, manipulating the signal with digital signal processing techniques, and determining if the RF circuit passes a test based upon results from the manipulating. Since the signal is clocked at a much lower frequency than an RF output of the RF circuit and the manipulation is performed digitally, testing can be performed at different stages of the production cycle and expensive test equipment can be eliminated.

Abstract: The present invention is a method of correcting packet discontinuities using the steps of: (A) generating a continuous real time data stream from input of media content from a media source comprising packets transmitted by way of a computer packet network to a specific receiving device to establish a transmission portion of an end to end communication, (B) a jitter buffer receiving real time data stream packets from the packet network and temporarily storing at least some of them in the jitter buffer, (C) the jitter buffer operating on multiple fixed length packets to output a first output of a predetermined sequence of said fixed length packets, preferably substantially as they were originally transmitted, (D) a control unit receiving the first output and changing the length of one or more of fixed length packets of the first output to form a second output in response to a detected delay or other discontinuity in the packet sequence, (E) a playout buffer receiving the second output and operating on the stre