Abstract: A delay unit 103 adds holding time that has been set by a holding time setting unit 104 to a received data. The holding time is computed based on delay time of received data and the minimum delay time of data received up to a certain point for the purpose of reducing a total delay time. The delay time is estimated in a delay time estimating unit 106 from the difference between a reception time of a packet counted based on an internal clock generator 107 and a time designated by a time stamp in the received packet.

Abstract: Real-time communication of multimedia data over heterogeneous networks that may include constant delay networks, variable delay networks that have a common reckoning of time, and variable delay networks that do not have a common reckoning of time. If there are any variable delay networks in which there is no common reckoning of time in the heterogeneous networks, a common reckoning of time is established in each of those networks. Then, a constant delay network is emulated for each variable delay network using the specific common time reckoning present in each variable delay network.

Abstract: A novel method and apparatus is described for reducing the number of CDMA codes for a constellation of multiple trasponder platforms serving a number of subscribers in the same service area. A coherent processing technique synchronizes the phase of CDMA signals arriving at a subscriber from multiple trasponder platforms to increase the code capacity and thus the number of possible subscribers for most of the multiple transponder platform systems in current use.

Abstract: Transmission delay in a serial bus connected network is determined by transmitting a Ping packet which is replied to in a physical layer of the bus from a request node to a response node, and measuring the time required from transmission of Ping packet by the request node until a Self—ID packet corresponding to the Ping packet is returned to the request node. The delay deviation between cycle timers of the request node and the response node is compensated by this transmission delay. The delay deviation may be also compensated using a time stamp.

Abstract: A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the timing of a digital signal in relatively large phase increments. The delayed clock signal is used to clock a register to which the digital signal is applied to control the timing a the digital signal clocked through the register responsive to adjusting the timing of the fine delay circuit and the coarse delay circuit. The timing relationship is initially adjusted by altering the delay of the fine delay circuit. Whenever the maximum or minimum delay of the fine delay circuit is reached, the coarse delay circuit is adjusted. The variable delay circuit may be used in a memory device to control the timing at which read data is applied to the data bus of the memory device.

Abstract: A dual time/frequency generation apparatus having a first and a second time/frequency generator for generating time/frequency signals in a code division multiple access CDMA system, including: a first time/frequency dualizing unit for mutually synchronizing a first and a second time clock, 10 MHz frequencies, and time data TOD signals respectively received from the first and second time/frequency generators in accordance with the delay value information and monitoring the operation of a second time/frequency dualizing unit; a second time/frequency dualizing unit for synchronizing the first and second time clocks, 10 MHz frequencies, and time data TOD signals respectively received from the first and second time/frequency generators according to delay value information and monitoring the operation of the first time/frequency dualizing unit to control its output; and a time/frequency out put unit for selecting and outputting one of the other output signs from the first and second time/frequency dualizing units.

Abstract: Sort operations of an input signal are performed by providing a first sort part 6 comprising one shift circuit 8 and (l?1) sort circuits 9a to 9c, and a second sort part 7 comprising one delay circuit 10, (m?1) sort circuits 11a to 11c and m shift circuits 12a to 12d in a pattern synchronous circuit 100.

Abstract: The invention describes a method and a system for fast and economic synchronization of multiframe structures, such as PDH multiframe binary signals, by detecting a periodic binary signature in a binary signal using one final state machine (FSM) comprising a logical scheme interconnected with a memory block having a plurality of independent memory cells with serial numbers for cyclically connecting thereof to the logical scheme; the signature is detected by applying the signal to the FSM while synchronously switching the cells to the FSM. The arrangement is such that when the predetermined periodic binary signature occurs in the signal, one of the cells will reach its predetermined terminal state.

Abstract: A multiplexer is provided for making data into a plurality of cells and then for transmitting the plurality of cells through a cell transmission path. The multiplexer includes a first delay-fluctuation adding unit adding a first maximum value of delay fluctuation occurring when the multiplexer transmits the cell, to a predetermined area of the cell; a second delay-fluctuation adding unit adding a second maximum value of delay fluctuation occurring when the multiplexer reproduces the data from the cell, to the predetermined area; a storage unit storing the data; and a data-read control unit controlling reading the data stored in the storage unit by following a maximum value of delay fluctuation stored in the predetermined area. Accordingly, the multiplexer can control absorption of the delay fluctuation individually for each cell transmission path.

Abstract: A data transfer system makes more effective use of a band available for the data transfer. In data transfer systems having devices with a different delay time in sending back the data depending on the transfer rate of data, it is possible to make more effective use of the band available for the transfer by transferring predetermined data at a slowest transfer rate within the data transfer system.

Abstract: A method for modulating a basic clock signal for digital circuits, in which distances between adjacent switching edges are altered, the basic clock signal being conducted via a changing number of delay units for altering the distances between the adjacent switching edges, the method comprising the step of calibrating delay times of the delay units (D1-Dn), wherein the delay units (D1-Dn) each have a plurality of delay elements (10) which are controlled to impart zero delay or a non-zero value of delay to a clock signal individually or in groups of the display elements; wherein the respective distance between two adjacent switching edges is derived from numbers of a random number generator; and wherein the distance between two successive switching edges is derived as a function of the random number and a modulation factor.

Abstract: A detector for detecting packet arrival time for packets received by a Home Phoneline Network Alliance (HPNA) receiver. The detector correlates received preamble symbols with stored preamble symbols and generates an estimation of the packet arrival time when the entire transmitted preamble has arrived at the receiver. The estimation of the packet arrival time is defined on a symbol period boundary. The detector includes a complex correlator with a simplified structure based on characteristic of the received HPNA signal.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: In an improved system for receiving digital voice signals from a data network, a jitter buffer manager monitors packet arrival times, determines a time varying transit delay variation parameter and adaptively controls jitter buffer size in response to the variation parameter. A speed control module responds to a control signal from the jitter buffer manager by modifying the rate of data consumption from the jitter buffer, to compensate for changes in buffer size, preferably in a manner which maintains audio output with acceptable, natural human speech characteristics. Preferably, the manager also calculates average packet delay and controls the speed control module to adaptively align the jitter buffer's center with the average packet delay time.

Abstract: Methods for slice-based encoding of program guides and user interfaces. The program guides include multiple video streams for picture-in-picture and other applications. A method for encoding the program guide includes encoding a first set of slices for each of a plurality of graphics pages; and encoding a second set of slices for each of a plurality of video streams. The user interfaces are multi-functional and may be used for electronic commerce and other applications. A method of generating the user interface includes encoding a set of slices for each of a plurality of objects, each object being characterized by an identity, at least one attribute, and at least one operation. In one embodiment of this method, the plurality of objects include an electronic commerce object, where the electronic commerce object is attributed with a first hyper text markup language (HTML) page.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: A channel pointer extractor extracts channel pointer value inserted in a SDH signal based on the pointer position information contained in the channel information, each time the channel information is detected by a channel information detector. A reference data readout section readouts the reference data of the channel specified by the channel identification information contained in the channel information from a reference data memory, each time the channel information is detected by the channel information detector. A pointer processing section judges the states of justification and alarm, from the channel pointer value extracted from the channel pointer extractor, and reference data read out by the reference data readout section and generates a new reference data based on the judgment results.

Abstract: The invention relates to a communication system comprising a plurality of interactive terminals which communicate with a master station via a transmission medium. The invention is particularly applied to interactive satellite broadcast systems. The invention relates to a request mechanism permitting the interactive terminals to have reservations assigned to them on the transmission medium for transmitting information to the master station. When a terminal receives assignments that have not yet expired, it temporarily stores them in an assignment memory. The invention comprises taking the number of assignments contained in this memory into account when a new request is transmitted. It thus permits to avoid that requests for the assignments that have already been granted are formulated again.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of using a bypass buffer in a node coupled to a ringlet includes the steps of: writing a packet of binary digital signals on the ringlet into the bypass buffer; and retaining the packet of binary digital signals in the bypass buffer for a predetermined amount of time before transferring the packet to the ringlet. Briefly, in accordance with another embodiment, a node to be coupled to a ringlet includes: a transmit buffer and a receive buffer. The transmit and receive buffers are coupled in a configuration to transfer binary digital signals between the node and the ringlet via the transmit and receive buffers. The configuration further includes a bypass buffer to temporarily queue binary digital signals passing through the node. The bypass buffer is further coupled in the configuration to retain a packet of binary digital signals for a predetermined amount of time before transferring the packet to the ringlet.

Abstract: Transmission delays due to the buffering of data packets are registered for the purpose of regulating a jitter buffer. Weighted mean delay values are continuously derived from registered transmission delays, with a shorter transmission delay receiving a higher weighting than a longer transmission delay. A read-out speed of the jitter buffer is then regulated as a function of the continuously derived weighted mean delay values in such a way that the weighted mean delay values are adjusted as a regulating variable to a predefined desired delay.

Abstract: This invention relates to methods and apparatus for measuring the performance of packet transmission in a cellular wireless telecommunications network to a user of such a network. Test packetized data is transmitted to the user and echoed back by the user. Differences between the transmitted and received echoed packets and delay in receiving the packets are analyzed. Packets are echoed at the user's station without alerting the user. The test packets have time stamps in order to allow delay between the transmission of the test packet and the reception of the echoed test packet to be measured. The transmitted and echoed packets are analyzed to determine error rates and delay in order to determine a quality of service for the data transmission.

Abstract: A method and apparatus for synchronizing a synchronizing clock is disclosed for use in synchronizing a high-speed memory bus with a second, heritage memory bus. This method and apparatus includes generating an initial synchronizing clock from a reference clock of the high-speed memory bus. It then includes receiving a synchronizing packet on the high-speed memory bus utilizing the initial synchronizing clock. Finally, it includes delaying a clock transition of the initial synchronizing clock in response to the received data of the synchronizing packet.

Abstract: A tracking data receiver which can compensate for deterministic jitter is disclosed. The device utilizes a history of past data received to determine which of multiple samples taken within a bit period to utilize. Due to deterministic jitter that can occur in data signal communication, the delay of waveform development varies with the ratio of 0's to 1's transmitted prior to the bit period being observed. The present invention exploits the predictable nature of the deterministic jitter to decide which sample to choose.

Abstract: A packet switching network which allows the duration of guard time of each packet to be reduced to a minimum and the transmission efficiency of the network to be increased is disclosed. The sending nodes send the packet switch packets each having a guard time added thereto. The receiving nodes receive the packets from the packet switch. Each of the receiving nodes includes a switch timing detector for detecting switch timing of the packet switch based on a serial signal received from the packet switch, and a timing holder for holding the switch timing.

Abstract: First and second successions of data words, each data word including multiple payload data bits, a data block bit (C) and a block character (SOB) having a first state to indicate start of a sequence of data block bits and otherwise having a second state, are processed by detecting as a first event occurrence of the block character of the first succession of data words in the first state and as a second event the next succeeding occurrence of the block character of the second succession of data words in the first state, wherein the second event is delayed by a time Tz relative to the first event, reading the data block bits from successive data words of the first succession and generating a succession of delayed data block bits of the first succession of data words, delayed by the time Tz relative to the payload data bits of the first succession of data words.

Abstract: An input buffer switch scheduling method operates responsively to a global common time reference. The global time reference is used to enable pre-computed switching schedules from an input port to an output port, thereby, expediting switching and increasing the performance and scalability of the switching system. In the switch architecture disclosed in this invention the switching fabric operates according to predefined switching schedules. The switch decodes the data packet headers in order to determine the destination output port and the switching time responsive to the global common time reference. This decoded switching time is then used by the pre-defined switching schedules in order to switch the data packet from the input port to the output port. The usage of predefined switching schedules provides scalability to the design of high performance input buffer switch design.

Abstract: Apparatus, and an associated method, for compensating for variable delays in the communication of packet data to a receiving station during, for example, a VOIP (Voice-Over-Internet Protocol) communication session. Compensation is made for surges of data received at the receiving station subsequent to a congestion condition. A jitter buffer and a trimming buffer are both utilized to buffer data packets thereat. The data buffered at the trimming buffer is selectably trimmed in a manner to permit the informational content of the data received at the receiving station to be recovered without introducing significant delay times in the recovery of the informational content.

Abstract: Propagation delay compensation in a wireless network comprising a central access point and multiple subscriber terminals is achieved by defining a registration time slot in which new subscriber terminals must first transmit network registration signals to the access point. The subscriber terminals by default transmit at the start of the time slot, and the access point times the delay from the start of the slot to the receipt of the subscriber terminal registration request, and then transmits this information back to the subscriber terminal. In all subsequent transmissions the subscriber terminal uses this information to delay its transmissions to compensate for differences in signal propagation delay between each subscriber terminal.

Abstract: A system for performing pointer processing on large concatenated payloads, in a processing node of an optical communications networks. The system comprises a plurality of processing strips. Delay blocks are introduced between a pair of processing strips on the pointer interpreter and/or pointer generator sides of the processing strips, so that corresponding data is read on one of the pair of processing strips after a predetermined delay from a time moment when the data is read on the other of the pair of processing strips, in order to overcome timing constraints arising from the need to synchronize the processing of a concatenated payload across multiple strips. Inter-chip communication blocks are introduced in order to allow concatenated payloads to be processed on different chips.

Abstract: A method for setting the offset of a time stamp, in which the offset value that is added to the time stamp is automatically controlled according to a transmission window value in a packetizing system for a high speed serial bus, and an apparatus therefor are provided.

Abstract: A time frame switching method and system of data units that utilize a global common time reference, which is divided into a plurality of contiguous periodic time frames. The system is designed to operate with high-speed wavelength division multiplexing (WDM) links, i.e., with multiple lambdas. The plurality of data units that are contained in each of the time frames are forwarded in a pipelined manner through the network switches, and can be switched from any incoming WDM channel to any subset of outgoing WDM channels responsive to the global common time reference. The outcome of this switching method is called fractional lambda switching.

Abstract: A method and apparatus are disclosed for dynamically adapting the play-out delay for voice packets transmitted over a local area network using the Ethernet standard as an access mechanism. It has been observed that the distribution of voice packet delays in a LAN (shared by voice and data traffic) follows a log-normal distribution. An adaptive algorithm is disclosed to estimate the parameters of the log-normal distribution and to apply a dynamic play-out delay to improve the quality of packetized voice conversations, quantified by minimum delay and packet loss. For example, the size, B, of the play-out buffer can be established to ensure that the packet loss does not exceed one percent (1%). The distribution parameters are continuously updated and the size of the play-out buffer, B, is modified at the beginning of every calibration interval according to the illustrative 99% percentile of the delay distribution.

Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.

Abstract: A new algorithm for clock offset estimation for resources distributed across a network (such as the Internet). By exchanging a sequence of time-stamped messages between pairs of network nodes and separately estimating variable delays for each message direction, present inventive embodiments provide more accurate estimates for clock offset between node pairs. Present inventive algorithms operate in a variety of peer and server network configurations while providing significant improvement in convergence speed and accuracy.

Abstract: A method of inspecting a communication link between a UE and a Radio Access Network (RAN) of a mobile teleconmmunications network. A Protocol Data Unit (PDU) containing a loop request is sent from an RLC entity located at a serving RNC of the RAN to a peer RLC entity located at the UE. The loop PDU is received at said peer RLC entity and recognised as containing a loop request. In response to the loop request, the receiving RLC entity automatically sends a response PDU from the RLC entity at the UE to the RLC entity of the RAN.

Abstract: A circuit comprising a first circuit and a second circuit. The first circuit may be configured to present information after a delay in response to a plurality of transmit and receive inputs. The second circuit may be configured to adjust the amount of delay prior to presenting information. The second circuit may be implemented as a state machine.

Abstract: A special rendering mode for the first few seconds of play out of multimedia data minimizes the delay caused by pre-buffering of data packets in multimedia streaming applications. Instead of pre-buffering all incoming data packets until a certain threshold is reached, the streaming application starts playing out some of the data packets immediately after the arrival of the first data packet. Immediate play out of the first data packet, for example, results in minimum delay between channel selection and perception, thereby allowing a user to quickly scan through all available channels to quickly get a notion of the content. The immediate play out is done at a reduced speed.

Abstract: A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.

Abstract: This invention is a transmission terminal station apparatus. The transmission terminal station apparatus is connected to a low-order group terminal device through a low-speed line and connected to a high-order group terminal station device through a high-speed line. The transmission terminal station apparatus includes a detection unit, a first insertion unit, a multiplexing unit, and a second insertion unit. The detection unit, when a frame is received from the low-order group terminal device, detects, as detection information, information related to operation maintenance information to be transmitted from the overhead of the frame to the high-order group terminal station device. The first insertion unit inserts detection information detected by the detection unit into a space area of the frame. The multiplexing unit generates a multi-frame including the frame.

Abstract: In order to compensate for rate mismatches between near end (receiving) and far end (transmitting) devices, intelligent jitter buffer management is implemented by apparatus comprising: a data interface for receiving frames from a data network; a jitter buffer for temporarily storing said frames; a detector for detecting frames which satisfy a criteria; and a buffer manager for controlling the frames stored in said jitter buffer based on the condition of said buffer and on frames which satisfy said criteria. The criteria can include silence frames or frames received with errors. The condition can include a high water mark (high threshold), and a low water mark (low threshold). If the far end transmitter transmits at a faster rate than the near end receiver, the jitter buffer will eventually become full beyond the high water mark, in which case frame(s) which satisfy the criteria will be deleted.

Abstract: A digital signal processing device for processing an input signal includes delay generation circuitry and processing circuitry. The delay generation circuitry receives the input signal and includes a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith. The delay generation circuitry includes a zero delay signal path and at least one nonzero delay signal path associated therewith.

Abstract: Disclosed is a method for providing a minimum congestion flow of Ethernet traffic that is transported through a pipe from a sending point to a receiving point over at least one SDH/SONET network, the at least one SDH/SONET network comprising network elements, fiber connections connecting the network elements and SDH/SONET virtual containers, the transport being managed through a new layer over SDH/SONET network physical layer, the new layer comprising Access Points, links of Access Point pairs and circuits, namely the possible routes for connecting a pair of Access Points.

Abstract: We describe multiple methods and apparatuses for characterizing the quality of a network path by means of metrics that at the same time are (1) additive and (2) characterize the performance of network applications.

Abstract: A multi-sectored, multiple access communication system provides for low-skew sector transceiver clocks by novelly utilizing a multi-tap digital Phase-Locked Loop (PLL) in the delay match circuitry of each transceiver to efficiently and inexpensively generate clock signals for each transceiver that are temporally aligned within acceptable limits of the other transceivers. The inventive system and method obviate the need for matching the lengths of all of the cables connecting the base station (“master sector equipment”) to the transceivers (“slave sector equipment”), and also reduces the power requirement as a byproduct.

Abstract: An embodiment of the invention is a method of helping establish optimal latency in audio streaming applications over a packet switched network. The method involves determining whether an elapsed time between arrival of first and second packets, the packets being parts of a stream of audio sent by a transmit process through the network and received by a receive process, is primarily a network delay due to the second packet being slowed while traveling through the network, or primarily a transmit delay due to a delay by the transmit process in sending the second packet. The elapsed time is included as part of interpacket delay statistics only if it is determined that the elapsed time is primarily due to the network delay. The latency may then be adjusted by adjusting the size of a packet queue based on more accurate interpacket delay statistics.

Abstract: A clock forwarding circuit automatically detects the delay in transmission of data between a master circuit such as a central processing unit and a slave circuit such as a semiconductor memory and forwards clocks corresponding to the delay. The master circuit includes a clock forwarding circuit which generates a clock signal. The slave circuit is coupled to the master circuit and generates a second clock signal which is synchronized with the first clock signal. The clock forwarding circuit receives the second clock signal, detects delay between the first and second clock signals and sets initial data load/unload parameters of the master circuit based on the detected delay. By forwarding clocks, the data transmission between the clocked circuits can be performed in faultless fashion independently of the delay.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: Variable rate multiplexer devices have, by definition, a variable output rate for bits of information encoded therein. As a result necessary time sync information such as program clock reference information cannot be guaranteed to be delivered within the time interval thresholds mandated by certain industry broadcast standards, such as MPEG-2 and digital video broadcast (“DVB”). Transmission of reference signals, such as PCR information, may be assured by inserting detection means to detect the time interval between occurrences of the reference signal. If the interval between occurrences of the reference signal exceeds a predetermined time interval threshold, the detection means will instruct a memory device to provide a reference signal, which is then imprinted with reference signal information and inserted into the stream of information being output by the multiplexer.

Abstract: The invention relates to methods and apparatus for synchronously digital interfacing communications components. The apparatus includes a device configured to transmit and receive differential signals. One set of differential signals includes a transmit signal and a receive signal, and another set of differential signals includes a clock signal and a synchronization signal. The combination of clock signals and synchronization signals form other signals having a variable period. The other signals are used to modify the set of differential signals including transmit and receive signals.

Abstract: A system and method for generating and remotely installing a private secure and auditable network is provided. Node identification, link, and application information is input into a template. A generator generates components using the information in the template and the components are remotely installed using an installation server. The components include agent modules which are each installed at predetermined target site and establish communication with the installation server to facilitate the download of other components, including application software and configuration files. Each node can only be installed once and is specific to a predetermined target site. For each link, a unique pair of keys is generated in a form which is not human readable, each key corresponds to a different direction of communication over the link. Data transmitted between nodes is encrypted using public-private key pairs.