Abstract: A signal transmitting-receiving system which has a signal transmitting side system constructed by signal transmitter T1, voice processor T2 and signal receiver T3 and also has a signal receiving side system constructed by signal receiver R1, synthesis circuit R4, signal transmitter R5 and delay circuit R3. The signal transmitting-receiving system is constructed such that no processing for making a video signal coincide with a voice used in communication using voices in position on a time axis is performed.

Abstract: In the communication system using the binary phase shift keying (BPSK) modulation method, an erroneous data that might be caused by a carrier slip of carrier wave generated during coherent detection can be compensated. The modulation unit of the transmitter transmits identical data at differentiated timing through BPSK modulation, and the coherent detector circuit of the demodulation unit of the receiver detects waves upon receiving signals. The compensating circuit makes time differences in transmitted data equal and compares them to detect mismatch in order to compensate carrier slip found in the received signal and then the combination circuit realizes the combination.

Abstract: A phase error cancellation apparatus captures data bits of a serialized data stream with reduced phase error by aligning a generated clock signal to the data stream. The phase error cancellation apparatus includes a data delay pipe, a clock generator, a clock delay pipe, and a data stream sampling element. The data delay pipe receives the data stream and delays the data bits by a first amount. The clock generator generates a clock signal that the clock delay pipe delays by a second amount. The data stream sampling element receives the delayed data bits and the delayed clock signal, and samples the delayed data bits using the delayed clock signal to recover the data bits from the data stream with reduced phase error.

Abstract: A data variation detecting system can perform detection of data variation at an arbitrary timing without lowering process performance of a processing unit, and without requiring expansion of a memory region in the processing unit. In the data variation detecting system, a recent data and a preceding data are taken from a shift register, are compared by a comparator circuit for detecting whether data variation is present or not by a data variation detecting circuit. The recent data is stored in a memory of an interface circuit with a data holding circuit. A result of detection by the data variation detecting system is directly stored in the memory in the interface circuit. When data variation is detected, operation of storing the recent data by the shift register and the data holding circuit is disabled via a masking circuit. The occurrence of data variation is detected by the processing unit via the interface circuit, the processing unit obtains the recent data from the interface circuit.

Abstract: A system and method for converting data between a multi-bit time division multiplexed (TDM) bus and a faster single-bit TDM bus, wherein each TDM bus communicates data by means of frames, each frame comprising a fixed number of slots and each slot comprising a fixed number of bits, the system comprising digital circuitry for establishing a clock rate R.sub.SB for the faster single-bit TDM bus that has the following relationship to a clock rate R.sub.MB for the multi-bit TDM bus: R.sub.SB =R.sub.MB *((slots per frame)*(bits per slot)+1).div.(slots per frame).

Abstract: A device for identifying input data by using a first clock signal includes a first identifying unit which identifies the input data by using the first clock signal to generate first identified data and generates a first phase-relation determination result by determining whether a phase relation between the input data and the first clock signal is appropriate, a delay unit for delaying the input data by a predetermined phase amount to generate delayed input data, a second identifying unit which identifies the delayed input data by using the first clock signal to generate second identified data and generates a second phase-relation determination result by determining whether a phase relation between the delayed input data and the first clock signal is appropriate, and a selection unit which selects one of the first identified data and the second identified data based on at least one of the first phase-relation determination result and the second phase-relation determination result.

Abstract: In a ring-type network system including a plurality of nodes connected by an L-ring and a R-ring, each of the nodes is constructed by a branch unit for branching data to first and second directions, a first delay unit for delaying the data in the first direction by a first delay time period, a second delay unit for delaying the data in the second direction by a second delay time period, a first combiner for inserting the delayed data in the first direction into a first time slot of a data frame on the L-ring, and a second combiner for inserting the delayed data in the second direction into a first time slot of a data frame on the R-ring.

Abstract: A mobile communication system is capable of establishing mutual synchronization of radio communication channels among a plurality of radio base stations. A synchronization timing control center is included in a wired telephone network as a terminal equipment of the wired telephone network. Each radio base station in the mobile communication network makes a connection to the synchronization timing control center by way of a mobile switching center, for establishing frame synchronization. Each radio base station measures a value of transmission delay between the radio base station and the synchronization timing control center, and then receives a frame signal as a reference signal from the synchronization timing control center. The formal frame signal to be used by each radio base station is reproduced by compensating the received frame signal by the transmission delay value which varies for each radio base station.

Abstract: A method and apparatus for providing full duplex asynchronous communication between two transceivers in a communication system is disclosed. First each bit period is divided in half creating a transmit half bit period and a receive half bit period wherein each transceiver can transmit data during the transmit half bit periods and can receive data during the receive half bit periods. The bit periods of the two transceivers are synchronized so that the transmit half bit periods of each transceiver are aligned with the receive half bit periods of the other transceiver.

Abstract: In a cellular radio communication system, a downlink signal is multicast from a cental station and multiple base stations receive the multicast downlink signal via transmission links and respectively transmit the downlink signal on radio waves of same frequencies so that a cluster of adjoining areas is illuminated with the radio waves. A mobile station having a tapped-delay line equalizer receives signals from the base stations via multipath fading channels and equalizes the received signals. Interference between the transmitted signals is avoided by adjusting the relative propagation delay times of the transmission links so that the signals received by the mobile station occur within the tapped-delay line length of the equalizer.

Abstract: According to decode system and method of the present invention in which a system clock is generated on the basis of a time stamp contained in transmission data to be transmitted every packet, and the transmission data are decoded on the basis of the system clock, the transmission data are stored into a buffer memory before a time stamp is extracted, and a packet storage amount of the transmission data stored in the buffer memory is detected to increase the read-out rate of the transmission data from the buffer memory when the storage amount is larger than a predetermined reference value and reduce the read-out rate of the transmission data from the buffer memory when the storage amount is smaller than the predetermined reference value.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of using a bypass buffer in a node coupled to a ringlet includes the steps of: writing a packet of binary digital signals on the ringlet into the bypass buffer; and retaining the packet of binary digital signals in the bypass buffer for a predetermined amount of time before transferring the packet to the ringlet.Briefly, in accordance with another embodiment, a node to be coupled to a ringlet includes: a transmit buffer and a receive buffer. The transmit and receive buffers are coupled in a configuration to transfer binary digital signals between the node and the ringlet via the transmit and receive buffers. The configuration further includes a bypass buffer to temporarily queue binary digital signals passing through the node. The bypass buffer is further coupled in the configuration to retain a packet of binary digital signals for a predetermined amount of time before transferring the packet to the ringlet.

Abstract: Method and apparatus are used to reshape isochronous Constant Bit Rate (CBR) and Variable Bit Rate (VBR) data at a receiving point (such as a multimedia workstation) using precise universal real time clocks that are provided by Global Position System (GPS) satellites.

Abstract: A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter.

Abstract: In a discrete multitone spread spectrum system, a base station receives a transmission burst from a remote unit being installed that includes delay compensation pilot tones that are uniformly spread throughout the transmission bandwidth. The arrival time transmission burst is not synchronized with the other remote units transmitting to the base station. The base station measures the phase delay of each tone and calculates the delay of the remote unit from the slope of the line of phase angle versus tone frequency. The base station transmits a signal to the remote unit that includes the magnitude and direction of the delay, which allows the remote unit to adapt the timing of its transmission to be synchronized with the other remote units.

Abstract: In ATM networks, the information transmitted in ATM cells is subject to jitter. This should be avoided particularly in the transmission of video signals and voice signals. The method provides a remedy here by reading the ATM cells into a buffer memory at the transmission clock rate and by reading them out again using the average value of the jitter.

Abstract: A clock distribution system including a variable delay circuit responsive to a reference clock signal having a fixed clock pulse width and a variable clock period for providing a delayed clock signal, an inverter for inverting the delayed clock signal to an inverted delayed clock signal, a clock tree for providing multiple replicas of the inverted delayed clock signal, a comparator responsive to the reference clock signal and a selected one of the multiple replicas of the inverted delayed clock signal for controlling the variable delay circuit such that the selected replica is delayed by one clock pulse width relative to the reference clock signal. Also disclosed is a shift register controlled variable delay line that can be implemented in the variable delay circuit.

Abstract: A two-way communication network for routing communications from and to a plurality of subscriber units at various geographic locations. The network includes a plurality of low power local subscriber units adapted to transmit and receive digital data messages of variable lengths and a central transmitter station (CTS). The CTS includes data transmission and data reception facilities. The transmission facilities transmit messages to the local subscriber units and include a synchronization unit that synchronizes the transmission facilities with a precision clock signal. The data reception facilities receive and process messages from the subscriber units. Remote receiver units are dispersed over the geographic area served by the CTS and relay digital messages transmitted from the subscriber units to the CTS. Each subscriber unit communicates with the CTS by way of digital data signals synchronously related to said precision clock signal and timed for multiplexed message transmission.

Abstract: A method and apparatus for adaptively transferring a time varying signal over a bus. According to the method, data representing the time varying signal by a specified digital representation is requested. A first number of data elements are transferred during a first time period, and an allocated bandwidth value representing a data transfer rate achieved in the transfer is then determined. The requested digital representation is subsequently adjusted according to the allocated bandwidth value. An apparatus of the present invention includes a processor and a host controller coupled to a processor bus. A source of digital values representing a time varying signal is coupled to the host controller. A memory coupled to the processor bus contains a data request routine for requesting digital values representing the time varying signal at a selected quality level.

Abstract: An AAL1 processing method in a cell disassembly apparatus for performing pointer comparison processing on the assumption that a pointer is inserted in each ATM cell, in parallel with sequence number processing, to determine the validity of the result of the pointer comparison processing to control an output data stream. In this case, data associated with each connection required for each processing is read from a memory table based on connection information added to a received ATM cell each time the ATM cell is received, and set in corresponding processing units.

Abstract: A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.

Abstract: A synchronization determining method and circuit for determining a synchronization state of a multiplexed data stream derived by multiplexing a plurality of data streams having the same contents with a time lag provided therebetween, wherein the synchronization determining circuit establishes synchronization without decreasing transmission efficiency, generating incorrect code sequences, or increasing overall circuit scale. In each embodiment of the present invention, synchronization is established without using synchronization words. Because synchronization is achieved without feedback loop delay, incorrectly decoded sequences are not generated for a period of time before synchronization is established. Also, because no maximum pass metric state detecting circuit is required, circuit scale, power consumption, and operating speed can be improved.

Abstract: A transport decoder 110, for receiving and processing a transport data stream using MPEG-2 formats, includes connections to a physical layer channel interface (channel interface) 112, a buffer memory 114, a host microprocessor 116, audio and video decoders 118/120, and clock signal circuitry 122.

Abstract: A receive SONET line interface includes an elastic store which receives and stores incoming signals from a pointer tracking circuit and retrieves stored signals for providing to a pointer generating circuit wherein, for both the pointer tracking and pointer generating circuits, separate state memories are provided for keeping track of the state of previous state pointer tracking and generating signals in time slots of repetitive frames of an incoming SONET signal.

Abstract: A device for identifying input data by using a first clock signal includes a first identifying unit which identifies the input data by using the first clock signal to generate first identified data and generates a first phase-relation determination result by determining whether a phase relation between the input data and the first clock signal is appropriate, a delay unit for delaying the input data by a predetermined phase amount to generate delayed input data, a second identifying unit which identifies the delayed input data by using the first clock signal to generate second identified data and generates a second phase-relation determination result by determining whether a phase relation between the delayed input data and the first clock signal is appropriate, and a selection unit which selects one of the first identified data and the second identified data based on at least one of the first phase-relation determination result and the second phase-relation determination result.

Abstract: A network (10) includes a broadband customer service module (B-CSM) (20). The B-CSM (20) includes a plurality of feeder interface cards (FICs) (36) and optical line cards (OLCS) (38) which are coupled together through a midplane assembly (34) so that each FIC (36) couples to all OLCs (38) and each OLC (38) couples to all FICs (36) through junctor groups (68). The B-CSM (20) interfaces many OC-12 SONET feeders to many OC-12 SONET lines. Within the B-CSM (20) circuit switching is performed electrically at an STS-1 rate. A reference clock which oscillates at a frequency lower than the data rate is routed with payload data so that it receives delays similar to those imposed on the payload data due to processing. At second stage switching fabrics (50) where data need to be extracted from signals flowing within the B-CSM (20), a clock regeneration circuit (32) generates a master clock signal oscillating at twice the data rate and phase synchronized to a delayed reference clock.

Abstract: An arrangement (apparatus and method) for detecting jitter caused during transport of digitally-coded information, such as MPEG-encoded data packets, and for correcting time stamp reference values in accordance with the detected jitter. The disclosed arrangement detects program clock reference (PCR) values from an MPEG-encoded transport stream, whereby each pair of PCR values represents an expected interarrival time of a corresponding stream segment. An actual interarrival time for the corresponding stream segment is determined in response to detection of the corresponding PCR values and an independent clock signal. The expected interarrival time of the stream segment is compared with the actual interarrival time in order to determine the jitter in the data packet stream. The jitter is corrected by a combination of adaptive buffering techniques and restamping the PCR value with corrected values coinciding with the actual interarrival time of the stream segments.

Abstract: A regulation apparatus for ATM cell delay variation includes a variation regulating buffer for temporarily storing cells transferred thereto, a variation waiting timer for controlling a waiting time which extends from reception of the first cell to read-out of cells from the buffer, a read-out timer for controlling intervals at which cells are read from the buffer, a latest cell preservation memory for storing the latest cell transferred from a VPI/VCI demultiplexing unit and, a selector for selecting a cell stored in the buffer or in the memory to transfer the selected cell to a cell reproduction unit.

Abstract: A digital phase adjustment circuit adjusts the phase between cell signals and a start-of-cell marker. The circuit relies on a known data pattern in unassigned cell signals in order to determine the phase. During a learning mode, the circuit samples an unassigned cell signal several times during a selected cell time to determine the location of the known data pattern. If the data pattern is not at the sampled position, the circuit increments the cell time during which it samples the next unassigned cell signal by one period, and decreases an amount of delay the circuit provides to a selected sample signal by one clock period. In this manner, the circuit can compensate for up to about two periods of delay before sampling the known data pattern. Thereafter, the circuit enters a tracking mode, and tracks phase variations between the cell signals and the start-of-cell marker. Additionally, the circuit selects a sample output signal which replicates the cell signals but is not subject to metastability.

Abstract: An ATM cell flow control apparatus includes interface sections for terminating transmission lines of two systems which constitute a redundant structure and to which identical cell sequences are supplied. Each interface section includes a cell synchronization section, a cell buffer, a policing section, and a delay control section. The cell synchronization section performs cell synchronization control of an input cell sequence and outputs the sequence in units of cells. The cell buffer performs delay adjustment of each cell output from the cell synchronization section. The policing section detects the cell interval between cells output from the cell buffer, and discards cells having a detected cell interval shorter than a predetermined cell interval. The delay control section detects the phase difference between a cell output from the cell buffer of a self-system and a cell output from the cell buffer of the other system, and controls the cell buffer in accordance with the detected phase difference.

Abstract: The disclosed device allows de-ceiling of ATM cells in structured data transmission according to ITU-Telecommunication Recommendation I. 363, reproduction of a plurality of STM frames represented at a speed of 64 kbps.times.n (n=any natural number), and moreover, discloses an architecture that allows a minimum of the buffer amount due to the de-ceiling.

Abstract: An apparatus for measuring transmission time is utilized for a data collection system including an observation station situated in a given wide-ranging region, and a collection station for collecting data from the observation station over a transmission line, and is designed for measuring the transmission time necessary for a signal to propagate through a transmission path.

Abstract: Provision is made of a phase-locked loop circuit including a voltage-controlled oscillator, a phase comparator, and a low-pass filter, a pulse-cancelling processing unit, a pulse-cancelling control unit, and a divider circuit. By dividing the pulse-cancelling request signal of the pointer-action into several bits by the divider circuit, the pulse-cancelling control unit gradually changes the input phase to the phase comparator or the control voltage to the voltage-controlled oscillator in several stages from the state before the 1-bit pulse-cancelling to the state of the 1-bit pulse-cancelling so that the phase of the output clock signal from the voltage-controlled oscillator matches the 1-bit pulse-cancelled input clock signal. By this, phase control of the output clock signal is performed in units of less than 1-bit and jitter is suppressed.

Abstract: A method for locating a frame position in an MPEG data stream within a computer system is disclosed. MPEG standard is a set of defined algorithms and techniques for the compression and decompression of moving pictures (video) and sound (audio), and the formation of a multiplexed data stream that includes the compressed video and audio data plus any associated ancillary service data. Although the MPEG standard is extremely flexible, there is a fundamental deficiency associated with the packet-oriented nature of the MPEG format, and that is there being no information about the position of each video frame encoded in the data stream. Even though such information can be deduced from the byte-rate, but because the calculation of a frame position depends on a constant byte-rate, a problem may still arise when the byte-rate is non-existent, incorrectly encoded, or constantly changed due to the presence of several packs with varying rates.

Abstract: A clock signal distribution system provides a set of synchronized, spatially distributed local clock signals. The system includes a source of periodic reference clock signal, a set of spatially distributed deskewing circuits and first and second transmission lines. The first transmission line routes the reference clock signal from the source to the deskewing circuits in a first order of succession. The second transmission line routes the reference clock signal from the source to the deskewing circuits in a second order of succession that is reverse to the first order of succession. The two transmission lines are of similar length and velocity of signal propagation between adjacent deskewing circuits. Each deskewing circuit produces an output local clock signal having a phase that is midway between phases of the clock signal arriving at the deskewing circuit via the first and second transmission lines.

Abstract: To reduce memory space of a speech path memory in a switching circuit for a multi-slot time division signal, only data in effective time slots of an input signal are stored one after another in a speech path memory to be switched into different time slot of an output signal in the present invention. Recording relations between time slot number of the input signal where data to be switched are carried and an address of the speech path memory where the data are stored, a conversion table converts switching control data indicating each time slot number of the input signal of data to be switched into each time slots of the output signal to address data of the speech path memory where the data to be switched are stored, and generates an idle bit pattern inserting signal when the data to be switched are not stored.

Abstract: Methods and apparatus for inserting data into an encoded data stream are disclosed. In accordance with the disclosed methods data is inserted into an encoded data stream while maintaining MPEG-2 compliance. The disclosed methods achieve data reduction required to make room for the data to be added by removing certain data elements of an encoded data stream, such as high frequency discrete cosine transform coefficients, which can be removed with minimal impact on picture quality and without disturbing the data stream's compliance with MPEG 2. In a first embodiment, data reduction to make room for the data to be inserted is performed by depacketizing the encoded data, performing a data reduction operation thereon, and then re-packetizing the encoded data. The reduced rate data stream is then multiplexed with the data to be inserted. In a second embodiment data reduction is performed by combining the contents of two or more consecutive transport data packets, e.g.

Abstract: In network applications that are distributed across more than two hosts in the network, a scheme capable of synchronizing and grouping packets into the so called fusion sets for playback is needed. Those packets arrive from different sources at a receiver, where they are "mixed" together for playback. The receiver can be one of the hosts/sources in the application, or a master host where packets from all the hosts arrive there first and subsequently are being forwarded back to all hosts. Basically, the apparatus and method operates as follows: the receiver accepts packets from other sources, and for each packet it computes its reference time (or expected arrival time). At the receiver, time is divided into reference intervals. Packets, one packet from each source, that their corresponding reference times are within the same reference interval at the receiver, they belong to the same fusion set for synchronization.

Abstract: A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

Abstract: A delay-in-frames correction system in a switch unit in a PCM transmission line is used for data communication. A channel data storage unit is provided to temporarily store data corresponding to each channel on the output side or the input side of the switch unit in each direction in the PCM transmission line. A data delay control unit delays data among the data corresponding to channels and stored in the channel data storage unit. The data corresponding to a plurality of channels is output in order in the same frame and delayed by the number of frames indicated by the most delayed data corresponding to channels to provide frame correction instruction information for outputting a data string in the same frame.

Abstract: A sharp phase variation of a clock is suppressed when master/slave status of a first and second communication device is changed over. The first and second communication devices respectively include clock selection circuits and clock production circuits for producing a synchronous clock from the selected clock, respectively, and supply the selected clock as the synchronous clock to the other communication device which is a mating-side device. One of the first and the second communication devices is a reference selection side and becomes a slave side, and the other device is a mating synchronous clock selection side and becomes a master side. Respective data signals from the communication devices are bit multiplexed in a multiplexing device on the basis of the synchronous clock.

Abstract: The circuit and method for detecting data collisions in a communication network, the circuit including: a data transition detecting section for receiving Manchester encoded data signals RXD, and detecting a transition at the center of the bit cell of the encoded data signals, and outputting a transition detecting signal Z having a certain pulse width; a delayer for delaying received clock signals RXC having a certain cycle synchronized with the received data signals RXD, and outputting delayed clock signals DRXC; and a data collision detecting section turning to an active mode in accordance with a data receiving status signal CRS illustrating the receiving status of the received data signals, and shifting the status of output signals in accordance with the transition detecting signal Z upon clocking of the delayed clock signal DRXC.

Abstract: An OFDM synchronization demodulation circuit includes a recovery circuit, an orthogonal axis demodulation circuit, a first and second delay circuit, a correlation calculation circuit, a guard timing detection circuit, and an OFDM signal demodulation circuit. The receiving circuit receives an orthogonal modulated wave based on an orthogonal frequency division multiplex (OFDM) modulated signal having an available symbol period and a guard period, where the guard period of the orthogonal modulated wave is based on a part of the available symbol period. The orthogonal axes demodulation circuit demodulates an in-phase axis detection signal and an orthogonal axis detection signal for the OFDM modulated wave from the receiving circuit using orthogonal detection. The first delay circuit delays the in-phase axis detection signal by the available symbol period, and the second delay circuit delays the orthogonal axis detection signal by the available symbol period.

Abstract: A time switching device and method having identical frame delay in a full-electronic exchange allows respective channels to have identical frame delay after switching multichannel in the full-electronic exchange by using only one time memory within the time switching device for providing data service of channel capacity larger than 64[Kbps], in which a time memory having a capacity four times larger than time switch capacity is divided into four areas to maintain a difference between the memory write and read operations by at least one frame period (125 .mu.s), thereby simplifying the structure of the time switching device and occupying a small area of a printed circuit board to accomplish small-sized system while decreasing the number of components required for constructing the system, thereby reducing system construction cost.