Abstract: Systems and techniques are disclosed for establishing a reference corresponding to the timing of a received signal from the first source, determining the timing for each received signal from a plurality of second sources, adjusting the reference to the timing of the received signal from one of the second sources, the timing of the received signal used to adjust the reference being closest in time to the unadjusted reference, and synchronizing a signal to the reference for transmission. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A switching arrangement for switching plesiochronous hierarchical digital traffic signals is provided. The arrangement includes a synchronous switching matrix with a number of input ports and output ports. Each input port may be connected to anyone of the output ports. The switching matrix uses a unitary reference clock with a frequency for synchronizing and clocking the traffic signals such that signals of at least two different hierarchical levels can be switched. Also presented is a system and a method for switching plesiochronous hierarchical digital traffic signals using a synchronous switching matrix for switching signals having at least two different hierarchical levels. An asynchronous switching means is provided for switching higher hierarchical level signals.

Abstract: A method of extracting a clock signal from a data stream, by generating a plurality of multiphase clock signals, creating error signals for each of the multiphase clock signals using the data stream, selecting at least one of the error signals based on retime state signals, correcting the multiphase clock signals using the error signal to produce corrected multiphase clock signals, and sampling the data stream using one of the corrected multiphase signals to produce a retimed data signal. The multiphase clock signals may be subharmonics of the data stream. In one embodiment, an UP error signal and a DN error signal are created for each of the multiphase clock signals, wherein the selecting step selects one of the UP error signals and one of the DN error signals, and the selected UP error signal and the selected DN error signal are applied to inputs of a charge pump to correct the clock signals. A multiphase voltage-controlled oscillator may be used to provide the multiphase clock signals.

Abstract: Methods and apparatus are disclosed for propagating timestamp floors throughout a packet switching system and using the timestamp floors received at a first component of the packet switching system to determine when a packet may be sent from a packet switching system. Each input of a first stage of a packet switching system maintains a floor register which is updated by copying the timestamp from each arriving packet. In some systems, if a packet is not received during a packet time, the timestamp is automatically updated, typically by adding a fixed time value. Periodically, the first stage switching element forwards a timestamp floor to the next stage switching elements. In one implementation, this distributed timestamp floor is the lesser of the earliest timestamp in one of the floor registers in the input queues, and the earliest timestamp in an output queue for the particular next stage switching element.

Abstract: Group-wise testing of the clocks arriving at a switching office is undertaken by multiplexing the clocks onto a single line and developing a signal therefrom that is indicative of a problem, if it exists, in any of the component signals that were multiplexed. In one embodiment, the developed signal is a gated portion of the multiplexed signal. That signal is integrated over an integration frame and compared to the integrated signal of another integration frame. A difference between the two compared signals indicates that at least one of the clocks is out of frequency synch. Subsequent tests identify the offending clock, or clocks.

Abstract: A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transported to the receiver domain. Circuitry is provided for detecting an edge in a global framework clock (GFC) signal that is supplied to the transmitter domain. A common alignment signal is manufactured that is based at least in part upon the GFC signal. A multiplexer and register arrangement is operable to output the second clock signal in response to the common alignment signal which is also used for gating the data transfer operations clocked by the first clock signal.

Abstract: A method and apparatus for precision time interval measurement in a time-of-flight mass spectrometer (TOF-MS). The method and apparatus produces an instrument capable of measuring bursts of data occurring at rates much higher than the average data rate. An asynchronous serial stream of data, consisting of a start pulse followed by an arbitrary number of stop pulses, repeated an arbitrary number of times, is converted into a digital stream of data synchronized to a precision master clock. Conversion of the asynchronous, analog data to synchronous digital data simplifies the measurement task by allowing the use of powerful, low-cost digital logic in the measurement.

Abstract: A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs.

Abstract: The present invention includes a method for clock recovery in a packet network. The method includes a network which receives data packets at a destination node. Then the data packets are stored in a buffer. The data packets are read out of the buffer by using a locally generated clock. The fill level of the buffer is monitored over a first period of time. A relative maximum fill level for the buffer is identified during the first period of time. Further, the relative maximum fill level is used to control the frequency of the locally generated clock so as to control the rate at which data is read out of the buffer.

Abstract: Techniques relating to aligning data bits in frequency synchronous data channels are disclosed. The techniques include determining a phase relationship between clock signals in a pair of data channels. If the clock signals are determined to be out-of-phase, the data bits in a particular one of the data channels may be reordered.

Abstract: An asymmetrical digital subscriber line (ADSL) downstream high speed cell bus interface protocol allows ADSL cell packets to be transmitted downstream from an ADSL bank control unit (ABCU) to a plurality of ADSL line units at a high rate of downstream throughput with flexible and efficient allocation of bandwidths and reduced error probability. The frame boundaries of an ADSL frame are derived from a conventional subscriber bus interface (SBI) frame for carrying conventional narrowband plain old telephone service (POTS) traffic, thereby allowing the ABCU and the ADSL line units to be implemented in existing channel banks with standard channel bank backplane traces.

Abstract: A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.

Abstract: An input circuit, in particular for a multiplexer, for phase controlling of a data input signal with a clock signal, comprises a flip-flop, wherein the data signal is fed to a clock input of the flip-flop and the clock signal is fed to the data input of the flip-flop, and wherein the data output of the flip-flop is used as a control signal of a locked loop. An advantage of the invention is, that it is of simple design which makes the invention especially useful for high frequencies. The data output of the flip-flop is dependent on the phase relationship of the data input signal with respect to the clock signal.

Abstract: A system receives a multiplexed input signal having a plurality of channels for data. The system includes a finite state machine which performs a predetermined logic operation on data in each of the channels of the multiplexed input signal. A memory, coupled to the finite state machine, stores at least one context of the finite state machine for each of the channels of the multiplexed input signal.

Abstract: The present invention relates to a method for ensuring access to a transmission medium at a predetermined point in time, for transmission of a data packet. This is achieved by making one or more communication pons on which the packet is to be transmitted unavailable for conflicting traffic for a period of time that is set to expire at the desired point in time, and preparing the data packet to be transmitted as soon as said communication port again is made available. Also described is a time server for distributing time information packets utilizing the method.

Abstract: A multi-sectored, multiple access communication system provides for low-skew sector transceiver clocks by novelly utilizing a multi-tap digital Phase-Locked Loop (PLL) in the delay match circuitry of each transceiver to efficiently and inexpensively generate clock signals for each transceiver that are temporally aligned within acceptable limits of the other transceivers. The inventive system and method obviate the need for matching the lengths of all of the cables connecting the base station (“master sector equipment”) to the transceivers (“slave sector equipment”), and also reduces the power requirement as a byproduct.

Abstract: A method for recovering clock signals includes generating a media sync signal to synchronize processing of digital media, and generating a transmission reference clock signal to define a duration of a transaction through a packet-based data network. The media sync and transmission clock signals may have different frequency and phase. The media is sent to a slave node of the network. The media sync and transmission clock signals are correlated to generate phase correlation information, and the phase correlation information is also sent to the slave node. Accordingly, a relatively low cost and reliable clock recovery technique suitable for synchronizing media streams across a packet-based data network is disclosed.

Abstract: A burst synchronizing circuit synchronizes a received data signal in a burst fashion and sampling phases with which the received data signal is sampled. A first part samples a data pattern with different sampling phases. A second part selects the received data signal sampled with an optimal sampling phase based on sampling phases with which the data pattern is detected.

Abstract: A data transmission/reception system made up of a transmission device for transmitting data according to a transmission clock signal and a reception device for receiving the data according to a reception clock signal. On receiving synchronization data representing the transmission clock signal from the transmission device, the reception device generates the reception clock signal which is synchronous to the transmission clock signal using a PLL circuit, and notifies the transmission device of an input voltage applied to a VCO in the PLL circuit on completing PLL processing. The transmission device adjusts a frequency of the transmission clock signal based on the notified input voltage so that the reception clock signal will be synchronized to the transmission clock signal at a median frequency in a synchronous range of the VCO in the PLL circuit.

Abstract: An input data signal is digitally sampled by a data sampling section using an N-phase clock signal including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle, and thereby a parallel sample data signal including N sample data signals is obtained. An edge point detection operation section detects edge points in the N sample data signals in one cycle of an extracted clock signal and outputs an edge point operation output signal. A clock signal extraction section selects a clock signal from the N-phase clock signal based on the information of the edge point operation output signal and outputs the selected clock signal as the extracted clock signal. A delay section delays the N sample data signals of the parallel sample data signal and thereby outputs a parallel delayed sample data signal including N delayed sample data signals.

Abstract: An apparatus and method for automatically detecting the port type of a remote device are disclosed. One embodiment of the apparatus includes a data rate detection unit to sample a data rate from an incoming data signal. A first frequency configuration unit is operatively coupled with the data rate detection unit to receive a detected data rate from the data rate detection unit. The apparatus also includes an oscillator to generate a plurality of reference clock frequencies. A frequency selector unit is coupled with the oscillator to select one of the reference clock frequencies. A phase lock unit to phase lock the incoming data signal is coupled with the first frequency configuration unit. A data rate select output is coupled with the first frequency configuration unit to operatively link the first frequency configuration unit with a second frequency configuration unit of a remote device.

Abstract: A communication system is provided for use in processing systems and the like for carrying out data transfer operations between a first data bus and a peripheral device associated with a second data bus, wherein the first data bus operates at a first clock speed and wherein the second data bus operates. at a second clock speed which is different from the first clock speed and a 1/N integer multiple of the first clock speed. A sample signal associated with the second clock speed is received and the speed of operation of a state machine of a peripheral controller is dynamically adjusted in response to the sample signal such that the state machine of the peripheral controller operates at the second clock speed and causes operations on the second data bus to occur synchronously at the second clock speed.

Abstract: Disclosed is a transmission system comprising a transmitter, a receiver and a transport network coupling the transmitter and the receiver. The transmitter is provided with time stamp means for generating respective transmission time stamps (TTS) representing a local clock based counting value included in a respective transport data stream (TS). The receiver is provided with a clock generator having a clock frequency control input. The receiver further comprises a time base regenerator coupled to the transport network for calculating a time difference between received successive transmission time stamps. The time base regenerator is coupled to the frequency control input for influencing the clock frequency based on said calculated time difference.

Abstract: A Method for initializing an asynchronous latch chain is described, wherein data are taken over through a latch stage at the beginning of the latch chain upon a request signal, the method comprising starting of a clock creation means, like for example a DLL (DLL=delay locket loop), for creating an internal clock on the basis of an external clock, resetting the asynchronous latch chain and applying a start signal to a request signal generation circuit whereupon the creation of a first request signal is enabled on the basis of the internal clock after the clock creation means is settled and after the asynchronous latch chain is reset.

Abstract: A redundant changeover apparatus causing no frame synchronization loss even upon occurrence of changeover between working system and protection system. In case of an in-apparatus synchronization system, when two input signals which are mutually asynchronous in phase are changed over by a changeover switch, a changeover switch, a clock extractor, a PLL circuit, and a clock changing portion transmit signals with clocks before the changeover being gradually changed to clocks after the changeover. Alternatively, in case of an in-apparatus synchronize system, data are separated from clocks so that the data are once changed to data with reference clocks, and then for the data, clocks before the changeover are gradually changed to clocks after the changeover.

Abstract: An apparatus supplying a clock in a multiline radio transmission system. The apparatus includes a clock generator for generating a clock from a reference signal, a clock branching module for receiving the clock generated from the clock generator and branching the clock, at least one clock patching module for receiving the branched clock from the clock branching module and patching the clock, and a clock distribution module for receiving the patched clock from the clock patching module and distributing the clock to each unit for receiving a clock of the multiline radio transmission system.

Abstract: The present invention presents an anti-meta trap (AMT) circuit for maintaining the data integrity of transmitted bit data in various applications. The anti-meta trap (AMT) circuit implement bit data integrity checks to prevent bit data from being misinterpreted at the bit level, that is, from being sampled at a data transition state. The invention also presents an anti-meta circuit combined with an auto-synchronization circuit to synchronize the phase of complete, bit-data verified cells, e.g., ATM data cells. The combined AMT-ASC is therefore able to verify the integrity of the data at the bit level, and synchronizing fixed-length data cells.

Abstract: The method is for transmitting data between two devices via a clock wire or line and at least one data wire or line. The clock wire is maintained by default on a logic value A, and each device is capable of tying the clock wire to an electric potential representing a logic value B that is the opposite of A. According to the method, both devices tie the clock wire to B when a datum is transmitted, the device to which the datum is sent does not release the clock wire while it has not read the datum, and the device sending the datum maintains the datum on the data wire at least until an instant when the clock wire is released by the device to which the datum is sent. The method is particularly applicable to communication between a microcomputer and a microprocessor.

Abstract: Information can be transferred while ensuring real-time characteristics without increasing the circuit size of an apparatus. A high-order layer packet is divided into a plurality of fragmented packets of fragment numbers, and these are transmitted via a wireless network. When an error occurs, if within a maximum permissible transmission process time, the fragmented packet of the same fragment number is retransmitted. For the high-order packet, since all the fragmented packets thereof could not be transmitted within that time due to the error, a halt flag is written into the fragmented packet of the next high-order packet.

Abstract: A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

Abstract: The invention relates to phase detectors that integrate a portion of a transition between adjacent or consecutive bits of a serial bitstream in a relatively fixed window by switching currents as opposed to voltages. The phase detector can be used to synchronize a VCO clock in a PLL to a fast data bitstream used in an optical network, such as SONET. Advantageously, embodiments of a current mode phase detector switch currents, rather than voltages, to integrate the window of the serial bitstream. The current switching allows devices to operate at frequencies approaching the device's fT and can advantageously extend the phase detector's bandwidth and allow an associated transceiver to operate at higher data rates. By contrast, the conventional switching of voltage results in a delay induced by the charging of related capacitances, such as parasitic substrate capacitances, which in turn results in actual performance far below the fT of the devices.

Abstract: The invention relates to methods and apparatus that compare the frequencies of a first clock signal and a second clock signal and reliably provide an indication of whether the frequency relationship between the first clock signal and the second clock signal is within a predetermined range. In one embodiment, the first clock signal is a reference clock signal and the second clock signal is generated from a serial bitstream. The indication can be used to synchronize a voltage controlled oscillator within a phase locked loop to the reference clock signal to thereby keep the phase locked loop within a lock range of a serial bitstream from which the second clock is generated. Embodiments of the invention digitally generate a beat frequency related to a difference in speed between the first clock signal and the second clock signal. The beat frequency is synchronized, advantageously obviating the need to synchronize asynchronous counters as is conventionally done.

Abstract: An elastic store circuit includes a set/reset flip-flop circuit corresponding to plural pieces of input data and an AND circuit for receiving the output of each flip-flop circuit. Upon receipt of a frame pulse indicating the head of each piece of input data, the flip-flop circuit outputs a signal to the AND circuit. The AND circuit outputs an H signal when it receives signals from all flip-flop circuits, and detects the receipt of the data having the longest delay time. According to the output signal of the AND circuit, data is read from each unit of elastic store memory.

Abstract: A glitchless delay line using a Gray code multiplexer is provided. The glitchless delay line combines a multi-tap delay circuit with the Gray code multiplexer. Specifically, the multi-tap delay circuit provides a plurality-of sequentially ordered delayed output signals on a plurality of sequentially ordered output terminals. The Gray code multiplexer has a plurality of input terminals coupled to the sequentially ordered delayed output terminals. The Gray code multiplexer is controlled by driving a Gray code value onto the control terminals of the Gray code multiplexer to select a specific delayed output terminal of the multi-tap delay circuit. The delay provided by the delay line is increased by incrementing the Gray code value on the control terminals of the Gray code multiplexer and decreased by decrementing the Gray code value on the control terminals. Race conditions on the control lines are eliminated when incrementing or decrementing the Gray code value by one.

Abstract: A desynchronizer for desynchronizing one or multiple channels of SONET/SDH data signals, which includes a first in first out (FIFO) buffer having an input coupled to said data signals and an output for outputting asynchronous data obtained from one or more of said SONET/SDH data channels. An arithmetic unit coupled to the FIFO performs all operations required for single or multi-channel desynchronization. An endless phase modulator is coupled to the arithmetic unit and to the FIFO and is operative, in response to input from the arithmetic unit, to produce a single output desynchronized clock or multiple output desynchronized clocks.

Abstract: A hybrid data parallel/serial data transfer system with phase adjustment and symbol coding for switching digital data packets in order to facilitate massive high speed, high capacity transfer of information with a limited number of signal lines. The transfer of information is processed over cross-bar networks. Much higher data transfer speed is possible than in a conventional serial data transfer. Moreover, the bits or Tera bits can be transferred easily over long distances. Data is transmitted over a communication link or trunk consisting of one of more cross-bar networks. Each message is transmitted as a sequence of groups of data bits, the bits in each group are transmitted in parallel over the trunk wherein each line or path carries a signal and each message is preceded by a serial start pattern. The receiver comprises a plurality of decoders for receiving data signals from the trunk. The arrangement overcomes the problem of data skew due to different transmission times over the lines of the trunk.

Abstract: A clock driver providing a clock signal, from an input clock signal, that has instantaneously selectable phase and methods for synchronizing data transfers in a multi-signal bus communication system. A clock driver of the present invention generates an output clock signal from an input clock signal having a periodic wave form and provides the flexibility for selecting or changing the magnitude of the phase-offset of the output clock signal, in relationship to the input clock signal, for desired clock periods and optionally desired half-clock periods. A method is provided for the self-calibration of critical delay elements. The present invention also includes a method for synchronizing data transfers between a bus master device that is clocked by a system clock and a plurality of synchronous DRAM devices (SDRAM) that are clocked by a local clock; the local clock has, in relationship to the system clock signal, a first phase-offset for read cycles and a second phase-offset for write cycles.

Abstract: A clock reproduction circuit capable of accurately reproducing a clock with a simple circuit structure and a data transmission apparatus capable of handling a wide range of transfer rates, having a reproduced clock signal which can quickly track a transmission clock, and not requiring an increase of the transmission media, wherein provision is made of a reception unit (clock reproduction circuit) having a clock generation circuit for generating a clock signal based on transmission data when a switch signal is not input and generating a clock signal locked to a frequency of a reference clock signal based on the reference clock signal when a switch signal is input; and an error detection circuit for defining a difference of input data sampled at a plurality of points having different phases of the clock signal generated at the clock generation circuit as an error, detecting whether the related error is a chance error or an error due to a deviation of the frequency between the generated clock signal and the inpu

Abstract: A timing signal supplying device in a doubled timing synchronous system includes: a timing signal adjusting portion which feeds back a timing signal of a timing signal receiving circuit and a frequency signal of a transmitting buffer to regenerate a timing signal and compares the timing signal with an external input timing signal to detect and correct an error of the timing signal; and a timing signal transmitting portion which sequentially transmits the corrected signal of the timing signal adjusting portion and the regenerated timing signal to the timing signal receiving circuit.

Abstract: 052440872 An existing synchronous residual time stamp (SRTS) algorithm (76, 78, 80, 82, 106, 104) is used in conjunction with adaptively filtered buffer fill information (74) to reconstruct an original constant bit rate (CBR) payload clock rate (102) for asynchronous transfer mode (ATM) CBR payloads (88, 96). The SRTS time stamp (96) is used as the primary factor used to recover the payload clock rate, but a secondary payload frequency correction factor (112) is generated by filtering (118, 120) the desynchronizer buffer fill position. This correction factor is determined as part of a feedback arrangement which adaptively (128) alters the filtering time constant based on the offset position of the buffer from its center. In this way, payload clock frequency (102) is corrected, even in the presence of loss of synchronization PRS traceability between mapping and desynchronizer nodes to keep the desynchronizer buffer from overflowing.

Abstract: An SRTS receiver for reproducing a user clock by applying combined pulses to phase synchronous oscillation unit, the SRTS receiver comprises a RTS information receiving unit for generating pulses in N-clock cycle of the user clock on average according to the received RTS information, an interpolation pulse generating unit for generating interpolation pulse signals to be inserted in the pulses generated by the RTS information receiving unit, and a pulse combining unit for combining the interpolation pulses supplied from the interpolation pulse generating unit and the pulses generated by the RTS information receiving unit and supplying the same.

Abstract: In the communication system using the binary phase shift keying (BPSK) modulation method, an erroneous data that might be caused by a carrier slip of carrier wave generated during coherent detection can be compensated. The modulation unit of the transmitter transmits identical data at differentiated timing through BPSK modulation, and the coherent detector circuit of the demodulation unit of the receiver detects waves upon receiving signals. The compensating circuit makes time differences in transmitted data equal and compares them to detect mismatch in order to compensate carrier slip found in the received signal and then the combination circuit realizes the combination.

Abstract: The fitting of boundary buffers on the exit from a telecommunications network can greatly reduce the relative wander. Adaptive boundary buffers have a phase adjusting circuit, for determining the phase error between a recovered line clock and a recovered return clock from receiving equipment of a telecommunications system, the phase of the recovered return clock being advanced or retarded by the value of the phase error and the phase of the recovered line clock being retarded or advanced respectively by less than the value of the phase error, so as to produce a phase adjusted Output Line Clock.

Abstract: A phase locked loop that enables highly precise tracking and phase locking of a synthesized clock signal to a reference clock signal. The phase locked loop has a memory that enables highly precise tracking and phase locking of a synthesized clock signal to its reference clock signal. The phase locked loop predicts the exact delay setting required for a frequency match, so that over-shoots and under-shoots around a desired frequency are minimized, and correction sizes are bounded to a relatively small region in the proximity of the desired frequency. The phase locked loop uses a dynamically programmable digital delay line to implement a variable frequency oscillator. The programmable delay line is used to produce a desired synthesized clock period. The phase locked loop provides an oscillator source whose period is determined by a delay derived from a clock distribution circuit plus a delay derived from the programmable delay line.

Abstract: A jitter detection method and apparatus for informing an adaptive equalizer that the correlated jitter of transmitted data exceeds a predetermined jitter value. In one embodiment of the present invention, a jitter detection circuit receives transmitted data symbol pulses and clock signal pulses. The jitter detection circuit then compares a specified edge (e.g., the falling edge) of an incoming data pulse with the corresponding specified edge (e.g., the falling edge) of a clock signal pulse to determine if an original phase error between the incoming data pulse and the clock pulse exists. Similarly, the jitter detection circuit detect subsequent phase errors between subsequent data pulses and subsequent clock pulses. The original detected phase error will then be compared against subsequently detected phase errors. Based on this comparison of the phase errors, the jitter detection circuit then informs the adaptive equalizer of the degree of phase and amplitude compensation that it needs to provide.

Abstract: A clocking mechanism with improved fault tolerance for synchronizing a distributed processing system includes a plurality of distributed clock sources. Each clock source may operate as a master clock for synchronizing the operations of the entire system or as a slave to an external clock while remaining available, in a backup capacity, to operate as a master clock in the event of a failure in the previous master clock. A clock selection mechanism is provided in each distributed switch element for selecting the best clock available to each switch element for synchronization. A failure recovery mechanism is provided with fast and automatic recovery in the event of a failure in a master clock. A data extraction mechanism is also provided capable of sampling a bit stream that is not phase-aligned, even in the presence of timing jitter and pulse width distortion, and having provisions for detecting a bit slip.

Abstract: A port circuit (108) for a time-division multiplexed (TDM) switching system (100) is designed to effect sub-time-slot operation without external support, as well as to effect conventional, time-slot operation. A clock-frequency multiplier, such as a frequency-multiplexed phase-lock loop (PLL 202), and a multiplier-driven sub-time-slot operation circuit, such as a PLL-driven finite state machine (203), are incorporated into the port circuit. The clock-frequency multiplier and the sub-time-slot operation circuit generate all the additional control signals that are necessary to define sub-time slots and to effect multiple information transfers in a single time slot. The port circuit engages in conventional time-slot transfers with conventional port circuits, whereby it is compatible therewith, and engages in sub-time-slot transfers with other sub-time-slot enabled port circuits, whereby it increases the transfer throughput of the TDM switching fabric.

Abstract: A method of recovering a clock signal which is embedded in an incoming data stream. The method includes the steps of providing the incoming data stream to a data sampler circuit, first operating the data sampler circuit to select one of a plurality of clock phases wherein the selected clock phase is indicative of the embedded clock signal, generating a recovered clock signal based on the selected clock phase, second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal, and disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode. An apparatus for recovering a clock signal which is embedded in an incoming data stream is also disclosed.

Abstract: A system and method for provides a generating a plurality of clock phases from a clock signal in a telecommunications cross connect system. The digital delay circuit includes a plurality of delay elements connected in series, each delay element connected to a sampling element, the output of the sampling elements sent to a multiplexor. The total number of delay elements comprises a number that produces a worst case delay equal to or greater than the period of the clock signal. The delay elements receive the rising edge of the clock signal. The delayed rising edges are sent to the sampling elements. The sampling elements send outputs to the multiplexor for determining the number of delay elements transitions by one cycle of the clock signal. A programming device can be coupled to the multiplexor to request from the multiplexor a particular phase of the clock signal. The multiplexor can select the appropriate delay device to generate the particular phase of the clock signal.

Abstract: A serial data signal is synchronized to a clock signal in a synchronization circuit (10). Synchronization is accomplished by generating a plurality of delayed versions of the serial data signal using serially connected delay elements (21-27). The delayed versions of the serial data signal are sampled using a set of flip-flops (11-18). The sampled delayed data signals appearing at the outputs of each flip-flop of the set of flip-flops (11-18) are used to determine which delayed data signal is most closely aligned to the clock signal. The output of the multiplexer (40) is an aligned serial data signal. In addition, a drift correction circuit (50) continuously monitors and corrects the alignment between the clock signal and the aligned serial data signal.