Abstract: A signal processor comprises a first circuit for extracting a PDH (plesiochronous digital hierarchy) signal from an incoming SDH (synchronous digital hierarchy) signal and a second circuit for adding an overhead to an incoming pure SDH signal to produce a synchronous transport module (STM) output signal. The output of the first circuit is selected when the incoming signal contains the PDH signal and the output of the second circuit is selected when the pure SDH signal is received. A local oscillator produces a first clock signal when the incoming signal contains the PDH signal or a second clock signal when the pure SDH signal is received. A read/write circuit is provided for storing the selected signal into a buffer at a first rate and reading the stored signal from the buffer at a second rate. The difference between the first and second rates is detected by a comparator.

Abstract: A device for identifying input data by using a first clock signal includes a first identifying unit which identifies the input data by using the first clock signal to generate first identified data and generates a first phase-relation determination result by determining whether a phase relation between the input data and the first clock signal is appropriate, a delay unit for delaying the input data by a predetermined phase amount to generate delayed input data, a second identifying unit which identifies the delayed input data by using the first clock signal to generate second identified data and generates a second phase-relation determination result by determining whether a phase relation between the delayed input data and the first clock signal is appropriate, and a selection unit which selects one of the first identified data and the second identified data based on at least one of the first phase-relation determination result and the second phase-relation determination result.

Abstract: A programmable data link module is used on a time division multiplex data bus having a repetitive time frame, each time frame having a plurality of time slots. The module receives data from the data bus during a selected time slot for a selected number of frames. The data link module includes a data verifier for storing the received data during the selected frames and inhibits outputting of data signals to the data bus until a repetitive occurrence of the received data over the selected number of frames has been verified.

Abstract: A linear phase detector used with half-speed quadrature clock architecture is provided. The linear phase detector includes a first circuit receiving a data signal, a first half-speed quadrature clock signal and a second half-speed quadrature clock signal. The first circuit generates an adjusted data signal and a polarity representing signal of the first half-speed quadrature clock signal. A high speed phase detector is coupled to the first circuit for generating a linear phase correction signal.

Abstract: A programmable data link module for use with a time division multiplex data bus includes a word extender module. The module can receive, send, or receive and send data over the data bus during a preselectable time period. The time period is defined by a programmable starting address and an ending address. The data can be single or multibit and variable length as determined by the time period selected.

Abstract: A microwave multiphase detector for demultiplexing and regenerating data from an incoming data stream includes N data channels and has a data rate R. For recovering data corresponding to a channel M, a detecting unit receives the data stream, detects a sampling phase corresponding to a data transition on channel M and generates a phase width modulated (pwm) pulse, phase modulated with the sampling phase. A digital to analog (D/A) conversion unit converts the pwm pulse to a contributing control voltage and a data regeneration unit provides a recovered data bit for channel (M). The detector is supplied with N variants of a local clock signal with a rate R/N, each variant being phase displaced with .+-.360.degree./N from the adjacent variants. A counterbalancing unit is also provided for each channel, such that if a pwm pulse is indeed generated, the contributing voltage for that pulse is compensated for with a balance pulse of opposed amplitude.

Abstract: A clocking converter for asynchronous data capable of performing bit synchronization processes of asynchronous data of different patterns by the same circuit, requiring virtually no change made therein, and shortening the processing time while achieving downscaling of the circuit structure.

Abstract: A receiver for NRZ data does not require a separate transmission media for the clock. Rather, a clock recovery circuit is included in the receiver capable of recovering the clock based on transitions detected in the NRZ data alone. The clock recovery circuit comprises an edge detection circuit which receives the data stream and generates edge detection signals indicating transitions in the data stream. Reference clock generation circuity generates a plurality of reference clock signals shifted in phase with respect to one another. Phase quantizing circuitry is responsive to the edge detection signals and the plurality of reference clock signals. The phase quantizing circuitry generates a quantization signal indicating one of the plurality of reference clock signals having a particular phase relationship to the edge detection signals.

Abstract: A plurality of data streams time-division multiplexed into a single stream are concurrently processed. State vectors characteristic of each data stream are stored in unique read-write memory locations having known addresses. During an initial clock cycle the next sequential data word is received from the single data stream and an input state vector characteristic of the data stream in which the received data originated is retrieved from the memory. The data word and the input state vector are passed to state machine logic which, during one or more intermediate clock cycles, processes the data word and the input state vector to produce an output data word and an output state vector. During a final clock cycle the output data word is transferred to an outgoing data stream and the output state vector is stored in the memory location from which the input state vector was retrieved.

Abstract: An SRTS clock recovery apparatus and method are provided. The apparatus broadly includes a controllable destination node clock generator such as a digitally controllable oscillator, a block for generating a local RTS-related value from the destination node clock and the system reference clock, and a comparator which compares the incoming RTS-related value to the local RTS related value to provide a feedback error or control signal which is used to adjust the controllable clock generator. If desired, a filter which filters the error signal can be provided in the loop. With the feedback loop as provided, when the destination node clock is faster than the source clock, the error signal will cause the destination node clock to slow, and vice versa.

Abstract: A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks.