Abstract: Systems and techniques are disclosed wherein a gated pilot signal can be re-acquired faster by searching a last known pilot offset and/or searching a last coset in which the last pilot signal was found.

Abstract: A business model of satellite digital audio broadcasting, also referred to as multicasting, teaches computer improvements in business operations for the determination of the number of listeners and listeners' preferences of multicast satellite transmissions and more particularly to the detection of signals from a multitude of individual client radios that simultaneously respond to a polling signal with a radio frequency chirp. A response to a polling signal instruction is synchronized utilizing an instruction embedded within a digital audio broadcast. Further embodiments teach a determination of listener count derived from signal strength, single chirp signal strength contribution derived from reception delay, and media prioritization derived from changes in user preferences.

Abstract: A synchronization pulse representing a symbol boundary in a signal such as an OFDM signal is obtained by deriving a first signal representing the difference between the amplitudes of samples separated by the useful part of an OFDM symbol, a second signal representing the phase difference between the samples, and combining the first and second signals to derive a resultant signal. The resultant signal is examined and the synchronization pulse generated in response to the signal changing in a predetermined manner.

Abstract: Disclosed is a variable-length image compression arrangement which represents successive distinct image data values (220, 221) of an image using corresponding non-decreasing Palette values (215, 222), and which incorporates (915, 1025) into the encoded data stream information recording the position in the encoded data stream at which each Palette value bit representation length increase occurs.

Abstract: A method for synchronizing a clock signal with a reference signal is disclosed. One embodiment has a first synchronization part which has a bit pattern having a particular clock period, a pause whose length is a multiple of this clock period plus a fraction of the clock period, and a second synchronization part having the particular clock period. The method includes generating a phase difference signal which is proportional to a phase difference between the clock signal and the reference signal, filtering the phase difference signal and providing a filtered phase difference signal, driving a digital oscillator in such a manner that the frequency of the clock signal is changed on the basis of the filtered phase difference signal, the phase of the clock signal within a clock period being corrected by a value corresponding to the fraction of the clock period at an end of the pause in the reference signal.

Abstract: A method and a system provide access to a communications medium that is suitable for allowing use of a plurality of Home Phoneline Network Association (HPNA) v2 frames in a centralized manner. Each HPNA v2 frame is timed to allow an Inter-Frame Gap (IFG) portion having a duration that is substantially a duration defined by an HPNA v2 protocol specification for an IFG portion of an HPNA v2 frame. A plurality of frames are generated in the communications medium with at least one frame of the plurality of frames having timing to allow a Shortened Inter-Frame Gap (SIFG) portion and a contention-free portion. The SIFG portion is less than about 17 ?sec in duration. Access to the communications medium is then provided for at least one station (STA) during the contention-free portion of a frame having timing to allow the SIFG portion.

Abstract: In a method for adaptive transmission timing control, the overlooking of a base path at the side of the base station that occurs when the transmission timing offset amount changes to the extent of falling outside the current delay-profile calculation range, and the side of the mobile station fails to demodulate the control information that contains the transmission timing offset amount, is prevented. A limit is put on the transmission timing offset amount applied in a single transmission timing control iteration. Together with setting the transmission timing offset value such that the main component of the delay profile calculated from the pilot signal transmitted with offset transmission timing falls within the time range of when the current delay profile was calculated, the time range for calculating the next delay profile is shifted such that a delay profile calculated from the pilot signal transmitted with offset transmission timing falls within the shifted range, starting at the earliest component.

Abstract: A method and system to synchronize a first device and a second device includes generating a first tone by the first device, the first tone one of including an identity of the second device and generated at a predefined time, receiving the first tone by the second device, setting a clock of the second device based on the received first time, and sending an acknowledgment by the second device to the first device.

Abstract: Method of adjustment of a receiver of signals transmitted in bursts in a system where the communications are set up within the context of successive frames comprising slots allocatable to the transmitters for their communications with the receivers. The adjustment of at least one characteristic of the receiver allows it to adapt upon the arrival of the bursts, by taking account of at least one reinitialization parameter for a first burst or adjustment parameter computed by a computation unit (4) from the preamble of the burst currently being received. At least one specified adjustment parameter is determined by a computation unit (4), for a new burst of a communication, by taking into account the part of the signal corresponding to the payload of the burst previously received for this communication, if the new is separated from this previously received burst only by a time which is less than a silence threshold value.

Abstract: A microcontroller having digital to frequency converter and pulse frequency modulator capabilities. The digital to frequency converter (DFC) generates a 50 percent duty cycle square wave signal that may be varied in frequency, wherein the 50 percent duty cycle square wave signal is directly proportional and linear with a count value put into an increment register. The pulse to frequency modulator (PFM) generates pulses having pulse widths of the input clock for each rollover of a counter. The frequency of these pulses is directly proportional and linear with the count value put into the increment register.

Abstract: A method and apparatus for processing packetized data spanning multiple clock cycles includes at least one comparator, for comparing a present clock cycle count to a reference clock cycle count, wherein the reference clock cycle values may be anywhere within the packet and may be non-contiguous with other reference clock cycle values. At least one word recognizer, compares a presently clocked word to a reference word, and an output circuit provides an indication of a favorable word comparison that occurred in response to a favorable clock cycle count comparison.

Abstract: This invention describes a false sync code protection (FSP) decoding technique by software for removing padding binary numbers from video data signals in electronic devices such as camera-phones. These padding binary numbers (e.g., a byte 101001012) are encoded in the video data signal. The invention describes a fast method for carrying out the decoding process using a predetermined criterion without need for separately comparing the received data using bit-by-bit process, and thus significantly reducing the number of processor instructions compared to the conventional bit-by-bit method. For the presented example these instructions are executed for every stand-alone zero byte found within e.g. JPEG data, which leads to considerable savings in execution time, especially if several JPEG images are taken and processed consecutively.

Abstract: In a wavelength division multiplexing transmission system having an optical transmission path which transmits wavelength division multiplexed light that is main signal light, supervisory control light is transmitted through the optical transmission path in the direction opposite to the direction of the main signal light. As a result, it is possible to restrain attenuation of the supervisory control light due to a Raman scattering phenomenon, thereby increasing a relay distance.

Abstract: A network component comprising at least one processor configured to implement a method comprising adding a clock synchronization data to a data stream comprising a plurality of Ethernet packets, wherein the clock synchronization data is located in a gap between two of the Ethernet packets. Also disclosed is a method comprising adding a clock synchronization data to a gap between a plurality of Ethernet packets in a data stream, wherein the clock synchronization data comprises a timestamp, a first bit that indicates whether the clock synchronization data is a request or an acknowledgement, and a second bit that indicates a requested operational mode.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhead processor may be synchronized with (i) an overhead generator and (ii) an overhead extractor.

Abstract: A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.

Abstract: A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control signal indicating an optimum phase data train, an output data selector for selectively passing optimum phase data train indicated by the control signal, and a data synchronization unit for converting the optimum phase data train to a data train in synchronization with a reference clock. The phase determination unit repeatedly detecting the optimum phase data train during the same burst data set is received. When optimum phase varies, the output data selector dynamically switches the optimum phase data train to be supplied to the data synchronization unit.

Abstract: A system receives input data frames that are configured according to a SONET or an SDH standard. The input data is converted to parallel data. The system provides groups of bits along parallel signal lines. In each group of bits, N contiguous bits in the group form a complete word of input data. The system identifies the boundary between complete words in the input data by comparing subsets of the bits to predefined framing patterns. The system then aligns the input data based on the location of each word using the boundary information. The output data of the system includes data that is word aligned. The system can also detect boundaries between the frames.

Abstract: An integrated services digital network private branch exchange, which is capable of automatically choosing a synchronization clock source. The integrated services digital network private branch exchange comprises a plurality of trunk chips, a plurality of subscribe chips, and a plurality of priority selection circuits. Wherein, the trunk chips connect to the network terminal via the trunk interface, and then connect to the central office via the network terminal to receive the frame synchronization clock output signal and the data clock output signal. Whereas, the subscribe chips connect to the terminal equipment via the subscribe interface. The priority selection circuits that are connected to each other in a daisy chain circuit manner are connected to the trunk chips to send out the frame synchronization clock output signal and the data clock output signal.

Abstract: Techniques to search for pilots over code space in a CDMA system. In one aspect, the pilot search is performed using a number of substages, and the search windows for each substage are selected such that the relevant code space is searched while reducing search time. In one specific implementation, two substages are used to search for pilots. The detect substage searches through (e.g., fixed-size) search windows to detect for peaks in the received signal. The dwell substage then searches through (e.g., variable-size) search windows to re-evaluate the detected peaks and remove noise peaks. The dwell windows may be formed such that a code space as small as possible is searched (to reduce search time) but large enough to account for possible drift in the detected peaks. Variable number of peaks may be provided by the dwell substage for the variable-size dwell windows.

Abstract: A method of synchronizing nodes of a telecommunication network in which a master node is coupled to a Primary Reference Clock (PRC) and a plurality of slave nodes are each arranged to synchronize their internal clocks to the PRC using data received on incoming data links. The method includes propagating Synchronization Status Messages through the network from the master node, with each node through which a message passes incorporating into the message its own identity, thereby generating in each message a node path which has been followed by the message. For each incoming link of each node, the path or path length of a Synchronization Status Message received on that link is registered as an attribute for that link.

Abstract: A splicing system includes a splicer for seamlessly splicing togther digitally encoded data streams. In a preferred embodiment, the splicer preferably parses successive splice buffers of data stream data for a splice-out point and a splice-in point, closing an initial group of pictures GOP if needed. The preferred splicer further finds a new data stream real-time program clock reference PCR value for aligning new data stream decode/presentation, and aligns the new data stream start time. Concurrently, the splicer preferably uses a frame table to detect overflow and corrects such overflow by adding null packets, thereby delaying portions of data stream data. The splicer also preferably restores data stream encoding by deleting null packets, and thereby accelerating a portion of data stream data. In a further preferred embodiment, the splicer preferably uses a bit-clock schedule offset to delay or accelerate portions of data stream data.

Abstract: Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between controllers in a distributed or localized control system, which is employed in order to allow operation of such controllers to be synchronized with respect to time. Also disclosed are synchronization protocols and hardware apparatus employed in synchronizing control operations in a control system.

Abstract: The synchronization signal generating section generates a packet synchronization signal PSYNC such that it is synchronized with the cycle of packets received from the master device. The interface control section generates a transfer clock PCMCLK used in transferring the data in the packets, from the internal clock. The interface control section measures the cycle of the packet synchronization signal PSYNC, and if the actual cycle of PSYNC is longer than the designated value, it makes the cycle of the transfer clock corresponding to the last data element in the packet longer than the cycle of the transfer clock corresponding to the other data elements, whereas if the actual cycle of PSYNC is shorter than the designated value, it makes the cycle of the transfer clock corresponding to the last data element in the packet shorter than the cycle of the transfer clock corresponding to the other data elements.

Abstract: A method and system for aggregating a plurality of links to simulate a unitary connection among one or more nodes in a fibre channel system includes means for striping data frames across the links. One or more programmable hardware mechanisms, operatively connectable to the links and to nodes in the fabric, also are provided. A program for collecting information about variable link characteristics is included. Programmable hardware mechanisms provide in-order delivery of data frames across the links despite the variable link characteristics.

Abstract: A unit for receiving and re-transmitting data signals comprising multi-byte packets separated by multi-byte inter-packet gaps includes a FIFO store, a first, write, state machine for controlling the writing of packets into the FIFO and a second, read, state machine for controlling read-out of packets from the FIFO. The first state machine is controlled by a recovered clock and the second state machine is controlled by a local system clock. The first state machine is operative in a writing sequence to write into the FIFO the words of each received packet in successive locations and thereafter to cause the writing into the FIFO of a succession of idle bytes representing a selected inter-packet gap; and the second state machine is operative in response to maintain a reading sequence in arrears of the writing sequence by a selected number of said locations. The arrangement maintains the inter-packet gap despite slight differences between the recovered clock and the system clock.

Abstract: The present invention relates to the field of communications. The method includes generating a sequence of symbols, the sequence of symbols including preamble symbols and a data symbol. The method further includes receiving the sequence of symbols generated by the transmitter, the receiver including a frame synchronizer logic to perform frame synchronization.

Abstract: One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip. This apparatus includes an I/O pin, for coupling a signal line within the semiconductor chip to a signal line outside of the semiconductor chip. A transmitting circuit is configured to selectively multiplex the plurality of signal lines onto the I/O pin. A receiving circuit is configured to receive multiplexed data from the I/O pin, and to reverse the multiplexing so that values originally from the multiplexed signal lines are separated into distinct signals in the receiving circuit. Note that the transmitting circuit and the receiving circuit are driven by a common clock signal. The apparatus additionally includes an initialization circuit that selectively configures the transmitting circuit and the receiving circuit to multiplex at least one of the plurality of signal lines through the I/O pin.

Abstract: A method for locating a synchronization sequence S having a length s in a serial bit stream, and an arrangement for the implementation of such a method make use of the fact that the synchronization sequence S is composed of a plurality of individual words A, B, C having respective lengths a, b, c. The search in the serial bit stream relates only to a word length a, b, c and not to the entire length s of the synchronization sequence S. When a word A, B, C has been recognized, the expected value for the search for the next word A, B, C is set by a controller. The expected values for the words A, B, C to be searched are programmable and thus can be freely defined for each application, so they can be selected in an application-specific manner. The words A, B, C to be searched can be characterized by two auxiliary bits Z whose formation is exactly inverted relative to that of normal data words A, B, C. This guarantees an unambiguous and dependable recognition of these words A, B, C.

Abstract: A computer system has a communication link that includes a control signal and data lines. A first control packet having a-plurality of bytes is transferred over the data lines from a first to a second node on the communication link. The control line is asserted to indicate transfer of a control packet. After transfer of the first control packet, a first portion of a multi-byte data packet associated with the first control packet is transferred with the control line deasserted. During transfer of the data packet the control line is asserted and transfer of the data packet is suspended. A second control packet is then transferred over the data lines. Subsequent to transferring the second control packet, the remainder of the data packet is transferred with the control line deasserted.

Abstract: A radio receiver in which the length of time that it takes to synchronize with a burst to be received is used as a measure of the quality of the channel over which the burst is transmitted.

Abstract: Using the 1st derivative ultra-narrow Gaussian monocycle pulse passed through a digital shaping multi-band FIR filter may generate a digital ultra-narrow shaped Gaussian monocycle pulse. The spectrum output of the shaped Gaussian monocycle pulse directly meets the FCC's mask restrictions of the emission limits for indoor UWB system. The digital system of generating shaping Gaussian monocycle pulse may be implemented in the off-line operation to save the processing power. The pulse generator in the UWB transceiver has flexibility and scalability of selecting only one shaped pulse out of the data memory banks in which allocate all of the shaped Gaussian monocycle pulses with the different center frequencies. With a shaped pulse generator, an UWB transceiver does not need either a digital shaping transmission filter or an analog shaping transmission filter, with coupling to a D/A converter before or after, during a real-time operation.

Abstract: A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.

Abstract: Method and apparatus for synchronizing communication between a battery and an electronic device are disclosed. Bytes consisting of a number of bits are transmitted between the electronic device and the battery. A predetermined bit sequence is appended to at least some of the bytes prior to transmission. The time interval between given shifts in the predetermined bit sequence is used to synchronize the communication.

Abstract: A chirp waveform is employed in establishing timing synchronization between nodes of a data communication network. In one embodiment, the chirp waveform is combined with a waveform modulated with data to form a synchronization waveform. The receiver of the synchronization waveform determines an alignment of the chirp waveform to a template chirp waveform to synchronize timing between nodes.

Abstract: Streams of data packets and timing pulses are received from a source. Time stamping of the data packets is carried out largely independent of individual timing pulses. A normalised pulse time of arrival is calculated, preferably as a running average over the most recent arrivals. Times of applicability for the content of the packets can then be calculated according to a predetermined relationship between the order of arrival and of corresponding pulses and packets. Data acquisition may take place from an external or internal data source. An example external source is a GPS receiver.

Abstract: A device for detecting a predetermined waveform in a received signal and synchronizing the detected waveform to the predetermined waveform is disclosed. The device includes a memory element for storing a reference set of encoded values. The reference set representing an encoded version of the predetermined waveform. An encoder is used to PCM encode the signal to obtain sets of encoded values representing the received signal. A processor calculates the statistical correlation coefficient of the reference set and the signal sets. The processor then determines the maximum statistical correlation coefficient. The predetermined waveform is detected in the signal if the maximum statistical correlation coefficient is greater than or equal to a predetermined threshold value. The device provides a compact, inexpensive, and fast method for detecting a known reference waveform in a received signal.

Abstract: A distributed method and apparatus for assigning a unique identifier number to devices connected in a sequential fashion and determining a total device count is presented. Additionally, a method and apparatus for enabling the support of a variable number and type of time slots within a time division multiplexed serial protocol is presented.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhead processor may be synchronized with (i) an overhead generator and (ii) an overhead extractor.

Abstract: An adjusting method for a synchronous signal in an optical storage device is disclosed. The optical storage device produces a predetermined synchronous signal, and the predetermined synchronous signal normally is matched with the data synchronous signal of the data on the optical disc. The predetermined synchronous signal includes a number of predetermined synchronous impulses, and the data synchronous signal includes a number of data synchronous impulses. In the method, when the data synchronous signal is not matched to the predetermined synchronous signal, it is searched that whether or not a data synchronous impulse is outside of the predetermined window and another consecutive data synchronous impulse detected later by a distance of an image frame is detected. Also and, according to the data synchronous impulse, the predetermined synchronous impulse is adjusted, so that the data synchronous impulse is matched with the predetermined synchronous impulse.

Abstract: A data recovery device for precisely recovering a transmission signal even if the signal having phase variations is provided. The device comprises a demodulator for demodulating a transmission signal, a plurality of symbol recovery units, each generating a corresponding synchronous signal and a lock signal, wherein the lock signals are selectively enabled to select one of the synchronous signals, based on pattern variations of the transmission signal detected by the symbol recovery units, and a data decision unit for performing a data recovery operation using the selected synchronous signal to recover original data of the transmission signal.

Abstract: A waveform to be transmitted as a burst within a channel that is used for the synchronization of unsynchronized wireless communications terminals in a wireless communications system, and a method of synchronization involving the waveform, that consists of a composite waveform. The composite waveform comprises two or more component waveforms, wherein each of the two or more component waveforms has a known frequency variation throughout the burst. The composite waveform has a composite bandwidth on an order of an available channel bandwidth and each of said two or more component waveforms have a component bandwidth on the order of the available channel bandwidth. Furthermore, a range of values for the differences between the instantaneous frequencies of two of said two or more component waveforms is on an order of twice of said available channel bandwidth.

Abstract: Methods and systems are provided which utilize pilots in an information sequence to periodically retrain a channel estimator. Thus, a channel tracker may be synchronized using a synchronization sequence and then periodically retrained using known pilot symbols. Furthermore, the utilization of pilots may allow for the detection of errors in previous channel estimates. When errors are detected, a new channel estimate may be used based on the retraining using the pilot symbols and, optionally, previous errors in symbol estimation may be corrected. Thus, by retraining based on pilot symbols, the propagation of errors may be reduced.

Abstract: Described herein is a system and method of disabling D bits in a CT2 MUX signaling channel. When the bit count equals the bit location of where the D bits are typically located in the signaling channel of a CT2 MUX, circuitry of the present invention disables a D bit enable signal from being processed. The D bit enable signal would typically allow a transmitter and receiver to, respectively, send a bit as a D bit, or process a received bit as a D bit. The suffix of the CT2 MUX, consisting of D bits, is unaffected by the present invention.

Abstract: A data transmission apparatus using a digital modulation system wherein a transmitting side inserts a group of predetermined synchronization symbols into a transmission signal at predetermined intervals to be transmitted. A receiving side calculates an electric power value of a received transmission signal. When a no-signal period (null section) in the synchronization symbol group is to be detected and decided from a magnitude of the received signal electric power value, a threshold for reference of decision for detecting the null section is calculated on the basis of an average electric power value for a predetermined period in the received signal electric power value and the threshold calculated in accordance with the received signal level of the transmission signal is used to detect synchronization stably.

Abstract: In base station side equipment, a control channel for transmitting control information and a communication channel for transmitting information to each mobile station are spread with different synchronizing codes before being superposed by operating a switch to switch the output of an adder over to the output of a synchronizing code generator. Further, a synchronizing code is periodically inserted in a signal by one symbol length and the signal is transmitted over the superposed channel. In a plurality of base station side equipment, moreover, the synchronizing code and its transmission period are equal and the transmission timing is asynchronous and independent.

Abstract: A state dependent synchronization circuit synchronizes an asynchronous input signal to a clock signal to generate a synchronous output signal. The circuit synchronizes both the leading edge and the trailing edge of the input signal and also maintains the state of the output signal at a level corresponding to the input signal when the input signal does not change. The circuit includes an input signal latch which receives the input signal and provides a latched signal which does not charge state even if the input signal subsequently changes state until the latched signal is synchronized to the clock signal. The circuit further includes a synchronizer which synchronizes the latched signal with the clock signal. The synchronizer provides feedback signals to the input signal latch to permit the input signal latch to recognize a change in the state of the input signal only after the synchronizer has synchronized the previous state of the input signal.

Abstract: A demodulator suitable for implementation in a single chip for demodulating digital video broadcast signals including data modulated on a multiplicity of spaced carrier frequencies, wherein an input broadcast signal is converted to a frequency sufficiently low to enable analog digital conversion of the signal. The demodulator includes an analog to digital converter for converting the broadcast signal to a series of digital samples; a real to complex converter for converting each digital sample to a complex number value; Fourier transformer for analyzing the complex number values to provide a series of data symbol values for each carrier frequency; a signal processor for receiving the data symbol values and providing an output for decoding; and a timing synchronizer for synchronizing the Fourier transformer with the symbol periods of the broadcast signal.

Abstract: The present invention relates to a method and arrangement in an ad-hoc network for synchronizing a multiple of radio transceiver arrangements with different characteristics that make use of a common air interface. Each transceiver arrangement comprises at least two transceivers which mutually communicate via a radio transmission link. All transceivers synchronize to a common synchronization signal comprising two staggered beacon pulse series signals (TX.sub.1, TX.sub.2) which have the same repetition rate. The transceivers synchronize their internal timers which control the signal transmission from the transceivers, to the strongest one of the two beacon pulse series signals (TX.sub.1, TX.sub.2) by listening during one of the corresponding sets of time windows (RX.sub.1, RX.sub.2). Between the reception of two beacon pulses, each transceiver transmits beacon pulses itself, thus contributing to the generation of the other beacon pulse series signal, on which other transceivers can lock.

Abstract: The process of synchronizing matching circuits of a communication system having modules connected with each other by serial data lines includes providing a transmitter and a receiver in each module as an interface between the serial data lines and a matching circuit; synchronizing at least one other matching circuit with a synchronizing matching circuit and transmitting the required synchronizing signals over the serial data lines; supplying parallel signals from the synchronizing matching circuit to the transmitter connected thereto and converting those parallel signals into serial signals in that transmitter; feeding the serial signals over the serial data lines to the receivers connected with the at least one other matching circuit, converting the serial signals into other parallel signals in those receivers and supplying the other parallel signals to the at least one other matching circuit connected with the receivers; generating an error signal in each receiver on detection of a transmission error; and r