Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

Abstract: A routing method for a multiplex system implements the following operations: For the data, multiplexing N input channels each having M multiplexed packets to generate an aggregate multiplex signal comprising all data packets representing the N input multiplexes. For each of N? outputs, providing the inputs of M+L parallel selection chains with access to the aggregate multiplexed signal. For input headers, performing demodulation and decoding. For output headers, performing encoding and modulation on the basis of the demodulated and decoded input headers. For the headers and the data, selecting from n of M+L selection chains corresponding to the kth output on the basis of the input headers corresponding to n packets that are to be routed to the kth of the N? outputs, the corresponding n data packets in the aggregate multiplexed signal and multiplexing these n data packets with an output header to generate the kth output multiplex.

Abstract: A system for transporting a high speed data stream over a plurality of relatively low bandwidth unshielded twisted copper pairs within the local loop plant or in any environment having a plurality of copper lines. A transmit data processor may perform scrambling, FEC encoding, and interleaving on the data before it is divided and dispatched to the plurality of modem elements for transmission over the local loop plant, either bidirectionally or unidirectionally. On the receiving side, the individual data streams are collected, aggregated, and a receive data processor performs de-interleaving, FEC decoding and de-interleaving, resulting in the high speed data stream originally transmitted. The system also may include crosstalk cancellation, power and PSD control, data raze control and optimal routing of the transmitted signals within the twisted pair binders. The system may optionally multiplex a plurality of low bandwidth telephony services over the high speed link using either TDM or FDM techniques.

Abstract: The present invention is directed to a system and method for demultiplexing video signals that have been combined using a time division multiplexing approach. The system includes synchronizers, parsers, demultiplexers, and an input buffer. Each demultiplexer within the system includes a header detect module, a slot map module, a frame sync module and a packet accept module. The method includes the steps of receiving an input stream that contains data packets for more than one program channel that have been combined in which packet identification (PID) information is used and a time division multiplexing scheme, such as transport stream multiplexing format (TSMF) is used. The PID and slot location for each packet is analyzed. Based on the PID and slot location a packet is either accepted or rejected.

Abstract: A multiplexed audio data decoder apparatus is provided in which integration of an audio decoder is easy, and has a high flexibility when the number of the formats to be processed is increased or when the specification is changed. In an external ROM 60 there are accumulated a plurality of decoding program codes corresponding to respective plural methods for compressing and encoding. A controller means 50 transfers the decoding program code corresponding to the method for compressing and encoding after changing thereof, from the external ROM 60 to an internal RAM 25. A DSP 22 starts decoding processing by using the decoding program code which is transmitted into the internal RAM 25.

Abstract: A method for simultaneously transmitting data bits using multiple channels. The method may include receiving a plurality of source data bits, arranging the plurality of source data bits so that adjacent source data bits are to be transmitted on a different channel and transmitting the plurality of source data bits on a plurality of channels.

Abstract: A read port for selectively coupling one of a plurality of inputs to an output is disclosed. The read port comprises: a plurality of inputs; an output; a plurality of multiplexers operable to selectively couple a selected input to said output; and a multiplexer control signal input for inputting a multiplexer control signal, the multiplexer control signal comprising a plurality of control parameters and being operable to control switching of the plurality of multiplexers. The plurality of multiplexers are arranged in a plurality of layers, the layers being arranged between the inputs and output, such that a selected input is operable to be coupled to the output via a multiplexer from each of the different layers.

Abstract: An alignment logic together with an MFI extractor are adapted to compensate for differential delays. The MFI extractor extracts the MFI disposed in the path overhead of each constituent time-slot. The alignment logic uses the extracted MFI to align corresponding data words (i.e., data words that are transmitted during the same time period) at the receiving end of virtually concatenated channels and that occupy different time-slots of the same channel. To perform alignment, the alignment logic stores each data word in a RAM location that is defined by an associated MFI. The data words so stored are aligned when read sequentially from their stored locations. The synchronization logic in the alignment logic synchronizes all the constituent time-slots.

Abstract: A demultiplexer apparatus has a plurality of integrating circuits which operate in parallel. The plurality of integrating circuits receive in parallel an input time-series binary data. One of the plurality of integrating circuits in a current stage converts the input binary data into multi-value data in the current stage, and generates recovery data in the current stage based on the multi-value data and recovery data from one of the plurality of integrating circuits in a stage immediately or more previous to the current stage integrating circuit. The plurality of integrating circuits output the generated recovery data as parallel data to the input binary data. In this way, the demultiplexer apparatus which can read the input binary data with a frequency component exceeding a maximum operation frequency is provided.

Abstract: A playback system in a digital cinema network synchronizes the presentation of visual and aural content by deriving timing information for packets of information that are conveyed in video and audio data streams, examining the timing information to determine if any misalignment between the two data streams is likely to be perceptible and, if the misalignment is deemed to be perceptible, introducing delays into one or both data streams to correct the misalignment. If the audio data stream precedes the video data stream, the audio data stream is delayed by an integer number of audio sample periods. If the video data stream precedes the audio data stream, the video data stream is delayed by an integer number of video frames and the audio data stream is delayed by an integer number of audio sample periods.

Abstract: Described is a transmission system (10) for transmitting an information signal (21) via a plurality of subchannels from a transmitter (12) to a receiver (16). The transmitter (12) comprises a demultiplexer (20) for demultiplexing the information signal (21) into a plurality of information subsignals (23). The transmitter (12) further comprises a channel encoder (8) for encoding the information subsignals (23) into encoded information subsignals (25). Each encoded information subsignal (25) is transmitted via one of the subchannels to the receiver (16). The receiver (16) comprises a channel decoder for successively decoding the received encoded information subsignals. The transmission system (10) is characterized in that the demultiplexer (20) is arranged for demultiplexing the information signal (21) into a plurality of partly overlapping information subsignals (23) comprising shared and non-shared information elements.

Abstract: A method, apparatus, and system are provided for multi-link extensions and bundle skew management. According to one embodiment, multiple parallel links between a central processing unit (CPU) and a peripheral device are combined into a single channel, and cells on the various links are received in a round-robin order, and variations in flight time between the various links are compensated through a timer at each receive port of the bundle.

Abstract: A Microsoft Windows BDA digital signal processing system includes a multimedia-processing device for processing a plurality of analog data packets and outputting a digital stream. A splitter receives and duplicates the digital stream to output a first digital stream and a second digital stream. A demultiplexer receives the first digital stream. When the first digital stream is a transport stream, then the demultiplexer demutlitplexes the first digital stream. A non-transport stream controller receives the second digital stream. When the second digital stream is a non-transport stream, then the non-transport stream controller processes the second digital stream. A processing method using the foregoing Microsoft Windows BDA digital signal processing system is also provided.

Abstract: A termination device for use in a WDM-SCM PON system can effectively support a multi-channel integration function of a WDM/SCM PON system.

Abstract: An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.

Abstract: A data communication system includes a rotating deinterleaver that reformats incoming data frames into a plurality of data subframes. The data contained in the incoming data frames is deinterleaved according to a protocol that distributes frame alignment signals periodically within the individual data subframes. The distribution of the frame alignment signals in the data subframes facilitates subframe alignment and subsequent recreation of the data frames from the data contained in the data subframes.

Abstract: There is provided a serial compressed bus interface having a reduced pin count. The interface includes a serial-to-parallel converter having a single serial data input line adapted to receive time-division multiplexed serial data from a plurality of data sources. Enable logic is adapted to input at least one data valid signal that identifies each of a plurality of data consumers for which the time-division multiplexed serial data is valid.

Abstract: A method for fast and economic handling of overhead bytes of an incoming high order data stream to form a corresponding outgoing high order data stream, the method comprising a) presenting the incoming high order data stream as a plurality of N component data streams transmitted in parallel, b) providing a common overhead processing unit (COHPU) capable of handling overhead bytes of a single one of the component data streams, c) forwarding overhead bytes of the component data streams to the COHPU in a circular order, while keeping docketing (ID) information for each particular overhead byte; d) processing each of the overhead bytes in the COHPU, and e) modifying the N component data streams to obtain an outgoing high order data stream based on results of the processing and the ID information with respect to each of the processed overhead bytes.

Abstract: The system of a content head end of a distribution system includes a program multiplexer, a multi-channel modulating module, a channel multiplexer, a digital-to-analog converter and a frequency block-up converter, all arranged in a sequential configuration. Packets representing respective content programs are fed to the program multiplexer. The program multiplexer multiplexes the packets into an output queue. Packets from the output queue are then fed to the multi-channel modulating module. The multi-channel modulating module receives the packets and routes them to various modulators representing corresponding RF channels. The various modulators then modulate the respective packets to generate corresponding RF signals. These RF signals are then multiplexed by the channel multiplexer into a multi-channel RF signal. The multi-channel RF signal is then forwarded to the digital-to-analog converter for conversion into an analog, multi-channel RF signal.

Abstract: Systems and methods are described for deploying bonded G.shdsl links for ATM backhaul applications. A method includes transporting digital data including: coupling a first end of a plurality of unbundled network elements to a first modem; coupling a second end of the plurality of unbundled network elements to a second modem; providing the first modem with a first single stream of asynchronous transfer mode cells; sequence-cell division multiplexing to divide the first single stream of asynchronous transfer mode cells into a plurality of streams of cells at the first modem; transmitting the plurality of streams of cells to the second modem via the plurality of unbundled network elements; and sequence-cell division demultiplexing to bond the plurality of streams of cells into a second single stream of asynchronous transfer mode cells at the second modem.

Abstract: Disclosed are interface buses that facilitate communications among two or more electronic devices in standard mode and burst mode, and bus bridges from such buses to a memory unit of such a device. In one aspect, interface buses group the data lines according to groups of bits, and include group-enable lines to convey a representation of which groups of data lines are active for each data transfer operation. In another aspect, exemplary interface buses include burst-length lines to convey a representation of the number of data bursts in a burst sequence, thereby obviating the need to provide sequential addresses over the bus. Exemplary bus bridges are capable of interpreting the signals on the interface bus and transferring data bursts between the interface bus and one or more memory units within the device.

Abstract: The invention relates to a method for synchronizing a plurality of digital input signals which are formed by sampling with the aid of a dedicated operating clock in each case. In order to be able to carry out such a method reliably with a relatively low outlay, according to the invention digital auxiliary signals (xd(nk+j), (yd(nk+j)) are formed by sampling the digital input signals (x(k)) with the aid of a common postprocessing clock, use being made of a postprocessing clock which is at least twice as fast as the fastest operating clock; synchronized digital output signals (x(m), y(m)) which correspond to the digital input signals (x(k)) are formed by means of interpolating each digital auxiliary signal (xd(nk+j), yd(nk+j)).

Abstract: To send a connection control message associated with a first set of attributes, only a difference of the first set of attributes from a second set of attributes associated with an already active virtual circuit (to a common destination) may be sent (contained in the connection control message). The devices receiving the message may create the necessary configuration for the new virtual circuit by modifying a copy of the configuration of the active virtual circuit. Processing requirements may be minimized as the devices may not need to parse and decode long list of information element. The feature may be particularly important in setting up a virtual circuit for voice calls, as a long list of attributes may be associated with each virtual circuit, but the difference of attributes being only minimal.

Abstract: A method and apparatus for multiplexing and demultiplexing communication signals are described herein. In one embodiment, an apparatus includes first sample logic to sample a plurality of communication signals each including a clock component and a non-clock component. The first sample logic includes a first multiplexer to receive the clock components and a second multiplexer to receive the non-clock components. In addition, a first counter is coupled to a control input of the first multiplexer and the second multiplexer. A capture unit including a non-clock component storage element coupled to an output of the second multiplexer and edge detection logic is coupled to an output of the first multiplexer to detect a transition of a clock component and coupled to a control input of the non-clock component storage element.

Abstract: A data transmission system that detects fiber faults receives a plurality of data packets carried on a plurality of Gigabit Ethernet links at a plurality of Gigabit Ethernet input/output ports. The system then multiplexes, on a bit by bit basis, the data packets onto an optical link. When the system detects a loss of signal in one of the Gigabit Ethernet links, a signal loss code insert is generated. The system then multiplexes the signal loss code insert with the data packets.

Abstract: A MAC master apparatus for executing a multi-point control protocol (MPCP) data in an optical line termination (OLT) of an Ethernet passive optical network (PON) is provided. The MPCP master apparatus includes a CPU interface unit, two or more memory arbitration control units, a SGA table memory, a RTT table memory, a static grant generation unit, a dynamic grant generation unit, a static grant queue, a dynamic grant queue, a sending message queue, a sending multiplexing unit, a time setting unit, a receiving window generation unit, an upstream grant queue, a received demultiplexing unit, a report queue and a received message queue. Therefore, any frame, including MPCP frames from/to the CPU can be sent or received, and a grant can be allocated statically according to a setting or dynamically according to a report from the ONUs.

Abstract: A demultiplexer for channel interleaving in communications systems with multiple carriers and/or transmitter diversity includes a distribution module that distributes data bits in succession to successive transmitter antennas, and a switching module coupled to the distribution module. The distribution module routes one data bit to each antenna such that no data bit is routed to the same antenna as the previous data bit. The switching module controls the distribution module to skip an antenna in the routing process once each time a predefined number of data bits have been routed. Alternatively, the switching module may control the distribution module to repeat an antenna in the routing process once each time a predefined number of data bits have been routed. The transmitter antennas may, in the alternative, be different carrier frequency bands.

Abstract: The present invention relates to methods and systems for transferring SONET/SDH frames between nodes by mapping the SONET/SDH frames onto individual channels of data and transferring the SONET/SDH frames over parallel transmission links. More particularly, the methods for transferring SONET/SDH frames includes transmitting SONET/SDH frames and receiving SONET/SDH frames using a transceiver module.

Abstract: Apparatus for transmitting a data stream between cards connected by a midplane breaks the data stream into a plurality of channels. The apparatus comprises a serializer for each channel. Serialized data is transmitted across the midplane to a deserializer at the destination. Sequential cells are sent in different channels. Cell ordering is preserved by staggering the start of cell transmission in the channels. The invention permits data to be transmitted across a mid plane using a reduced number of data lines. The data stream on each card may be carried in a wide bus at a relatively low clock rate. Apparatus according to the invention may be used to transmit an OC-192 data stream across a pin-limited interface.

Abstract: In a transmitter of a wireless communications system having M transmit antennas (10), each transmit antenna is supplied with a respective combined signal comprising a respective one of M groups each of N data sub-streams, orthogonally spread by N Walsh code sequences (W1 to WN). The N orthogonal code sequences used for each of the M groups comprise a respective one of M different combinations of N from Nw orthogonal code sequences, where Nw>N. M and N are integers greater than one. The combined signals can also include orthogonally spread pilot signals (WP) for channel estimation at a receiver. Orthogonality of the signals transmitted from the transmit antennas is increased, so that transmit signal power can be decreased and/or the receiver can have fewer than M receive antennas.

Abstract: The present invention provides an Ethernet switching apparatus using frame multiplexing and demultiplexing. The Ethernet switching apparatus has a plurality of frame demultiplexers, a plurality of frame multiplexers and a switch fabric chip set. The frame demultiplexers convert at least one 10 gigabits Ethernet frame into a plurality of gigabit Ethernet frames. The frame multiplexers convert a plurality of gigabit Ethernet frames into at least one 10 gigabits Ethernet frame. The switch fabric chip set is provided with input and output interfaces using the GMII, and is connected to the frame demultiplexers and the frame multiplexers in the GMII format. The switch fabric chip set outputs frames through an arbitrary usable one of a plurality of GMII ports connected to a corresponding frame multiplexer if the frames are transmitted to the corresponding frame multiplexer.

Abstract: A method and apparatus in which a plurality of demux processors propagates respective received sample streams to adjacent demux processors via an inter-demux bus; and wherein a final one of the plurality of demux processors propagates all of the respective received sample streams toward a next processing element such as a multi-drop bus (MDB) or system processor within a data acquisition device.

Abstract: A method for transmitting a stream of data over a channel made up of a plurality of subchannels having respective subchannel rates. The method includes partitioning the data among the subchannels, such that successive words of the data are mapped to the subchannels in alternation responsive to the respective subchannel rates. The words of the data are transmitted over the subchannels to which they are mapped, and are then received and processed to recover the stream of data.

Abstract: There is provided a method and apparatus for the ordered release of connections from a network entity in a signalling communications network upon the detection of the failure of a signalling link or a port corresponding to such connections. A priority indicator is associated with each of the connections. Each priority indicator is selected from a priority hierarchy having several priority levels which varies from highest priority to lowest priority. Upon detection of the failure of a signalling link or port, every connection associated with the failed signalling link or port is released. The release of the connections takes place at the network entity in a sequence which corresponds to the priority hierarchy. A method and device are also provided for the ordered release of connections carried on a logical truck having a variable capacity, for example an IMA trunk, upon the detection of a reduction in capacity. The IMA trunk may be provided on several physical links.

Abstract: A serial data stream is mapped through a cross-connect via two or more parallel independent shelves. The serial data stream is split into at least two sub-streams. If the lead frame of a sub-stream contains a concatenation indicator, it is replaced by a valid payload pointer, and a spilt indicator is inserted into the frame. Each of the sub-streams is then mapped through the cross-connect via a respective parallel independent shelf. Finally, the sub-streams are recombined to form an output serial data stream equivalent to the original serial data stream. If the lead frame of a sub-stream contains a split indicator, a concatenation indicator is inserted into the corresponding frame of the output serial data stream to restore the concatenation of the original serial data stream. Otherwise, a payload pointer within the lead frame is replaced by a valid payload pointer in the corresponding frame of the output data stream.

Abstract: In a first aspect, a stream of data is transmitted by dividing the stream of data into a first substream and a second substream, transmitting the first substream in a first data channel, and transmitting the second substream in a second data channel. Before transmitting the first and second substreams, a first marker signal is inserted in the first substream and/or a second marker signal is inserted in the second substream. A receiver circuit receives the substreams, detects at least one marker signal, and reassembles the data stream from the substreams based on at least one detected marker signal. Numerous other aspects are provided.

Abstract: The inverse multiplexer device for inverse multiplexing of a broadband data stream received via a broadband data line (7) comprising measuring means (3a–6a) for measuring connection parameters of data transmission lines (3–6) connected in parallel to each other, selection means for selecting a subset of the data transmission lines (3–6) depending from the measured connection parameters and activation means (15a) for activating he selected subset of data transmission lines (3–6) to transmit the received data transmission stream over the selected subset of data transmission lines (3–6).

Abstract: Data frames are converted to a format suitable for transparent, flexible concatenated transport such that a network element not supporting flexible concatenation may transparently pass the data frames. Flexible concatenation involves nonstandard data frames such as an STS-4c or an STS-Nc in which the time slots do not occupy rigidly defined contiguous time slots. In transparent flexible concatenation, the pointer from the parent time slot is used for each of the child time slots and the concatenation identifier is set to indicate no concatenation. In this way, the concatenated data appears to be a series of conventional STS-1s such that pointer processing may be successfully accomplished even by a network element not capable of handling non-standard concatenations. A downstream receive framer reconstructs the original STS-Nc based on the N STS-1s and a concatenation table the contents of which are shared between the transmit framer and the downstream receive framer.

Abstract: A system, method, and article of manufacture suitable for transmitting a programmable message in place of or intermixed into a streaming media data stream to a receiving device upon receipt of an event is disclosed.

Abstract: A source selection system for a communication switch for selecting a primary datasource from a plurality of datasources is provided. The system includes a validation module associated with the plurality of datasources adapted to monitor each datasource of the plurality of datasources for transmission errors in output originating from each datasource and adapted to provide information relating to the transmission errors. The system also includes a source selector associated with the validation module and the plurality of datasources, the source selector adapted to select an output datasource from the plurality of datasources. The system further includes an assessment module associated with the validation module adapted to identify the primary datasource from the plurality of datasources utilizing the information provided by the validation module and adapted to cause the source selector to select the output datasource associated with the primary datasource.

Abstract: A processing apparatus for processing multiple video programs from one or more transport streams. The processing apparatus has a transport processing circuit that includes multiple transport processor units. The transport processor units utilize a common transport processor memory unit having demux context entries containing processing and hardware state information for packet types. Each transport processor unit includes a transport interface for identifying data packets to be acquired from the transport stream, a demultiplexing processor for processing the acquired data packets, and a demultiplexing DMA unit for memory handling operations of the processed data packets. Index chaining allows the transport processor units to access information from the transport processor memory unit. The method uses indices to access demux context entries from the transport processor memory unit. Related DMA indices are used to access memory handling information from the transport processor memory unit.

Abstract: An asynchronous data pipe (ADP) automatically generates transactions necessary to complete asynchronous data transfer operations for an application over a bus structure. The ADP includes a register file which is programmed and initiated by the application. The register file includes the bus speed, transaction label, transaction code, destination node identifier, destination offset address, length of each data packet, packet counter, packet counter bump field, control field and a status field. During a data transfer operation, the ADP generates the transactions necessary to complete the operation over the appropriate range of addresses, using the information in the register file as a template. The ADP increments the value in the destination offset address field for each transaction according to the length of each data packet, unless the incrementing feature has been disabled and the transactions are to take place at a fixed address.

Abstract: A method for transmitting a data stream from a circuit unit to a memory cell array includes receiving the data stream and demultiplexing it in response to a control signal, thereby dividing the data stream into a storage data stream and a mask data stream. The storage data stream is then buffered into a register unit, where it is divided into data stream components buffered in corresponding data register components on the basis of a clock signal and an address signal provided to the register unit. Meanwhile, the mask data stream is buffered in a mask register of the register unit. A composite data stream is then formed by combining selected data stream components in response to information provided by a data mask unit from the mask data stream buffered in the mask register. Data corresponding to this composite data stream is then provided to the memory cell array for storage therein.

Abstract: Multiple single-channel links are employed as a single high-bandwidth link for packetized data having a single packet delineator. The single high-bandwidth link may typically be employed for transfer of data in intra- and inter-frame/rack back-planes. A transmitter forms the packetized data including the single packet delineator. The packet delineator is used by, for example, a framer of a receiver to enable reconstruction of packetized data from the multiple single-channel links. The transmitter forms the packetized data such that a beginning portion of each packet is transferred to a particular one of the single-channel links. Thus, the packet delineator is associated with that particular single-channel link, regardless of the number of other single-channel links that are bonded together with that particular single-channel link to form the single high-bandwidth link.

Abstract: A system for transporting a high speed data stream over a plurality of relatively low bandwidth unshielded twisted copper pairs within the local loop plant or in any environment having a plurality of copper lines, such as on campuses, within large buildings, etc. The copper twisted pairs are transformed from a plurality of low bandwidth, low reliability links into a high reliability, very high bandwidth long range communication channel utilizing optimized xDSL transmission technologies over the plurality of copper pairs. A transmit data processor perform scrambling, FEC encoding and interleaving on the data before it is divided and dispatched to the plurality of modem elements for transmission over the local loop plant, either bidirectionally or unidirectionally. On the receiving side, the individual data streams are collected, aggregated and a receive data processor performs de-interleaving, FEC decoding and de-interleaving, resulting in the high speed data stream originally transmitted.

Abstract: A method and apparatus for interfacing a parallel connection, the parallel connection transmitting high bit-rate signals for a short distance. The method comprises: receiving a synchronous N-bits input data flow at a first input frequency; inserting said input data flow into parallel packets having a given length; and outputting said packets having a given length at a second output frequency onto a M-wires parallel connection.

Abstract: Techniques for carrying out multi-pair mode transmission in a DSL system are disclosed. A data stream is transmitted to a receiving node on two or more bonded channels. At the receiving node, the bonded channels are processed to yield the original data stream. Differential delay between the two or more channels of the bond group is dynamically neutralized by keying on the channel having the greatest latency, although static mechanisms for neutralizing the differential delay can also be used.

Abstract: A virtual concatenation method for optical channels in WDM networks. In transmission, the method includes providing for a plurality of frames, each frame including a byte reserved for a concatenation flag; writing the same predefined value in the concatenation byte of n frames (n=1, 2, 3, . . . ); and transmitting the n frames via n respective channels (?1, ?2, . . . ?n). In reception, it includes receiving the first reference frame at one instant; reading the concatenation byte value of the reference frame; receiving the remaining signal frames after a respective determined time; reading the value of the concatenation byte of the remaining signal frames; and identifying and aligning all the signal frames with the same concatenation byte value compensating the reception times.

Abstract: A method and apparatus for extending existing fiber and local area networks across digital subscriber lines, at matching data rates is disclosed. A DSL transceiver system is disclosed with one or more gateways coupled to at least one digital signal processor (DSP). The DSP in turn couples to a plurality of analog-front-ends (AFE's). Each AFE is coupled via associated hybrid front ends (HFE's) to corresponding subscriber lines. The transceiver or a controller coupled thereto maintains a table of bandwidth requirements and frame types for a variety of sessions. Individual sessions include bandwidth requirements beyond existing XDSL capabilities. The system determines frametype, e.g. 802 and bandwidth requirements, e.g. 100 Mbps for each session and allocates more than one subscriber line accordingly. For each session the divergent bandwidth availability of each of the subscriber lines to which the DSP may be coupled is determined and all or a portion of that bandwidth is allocated to the selected session.

Abstract: A system that can be dynamically configured to achieve an optimal routing path for an end-to-end data link connection is disclosed. An optimal data path can be determined by a digital subscriber loop (DSL) user based on particular bandwidth requirements, data rate cost constraints, and/or data delay requirements. The data path can be set up to include one or more data routes, including the regular digital public switching telephone network (PSTN), a wide area networks (WAN), or virtual permanent circuit links via digital cross-connects (DCS).