Abstract: A multicarrier transmission system (100) routes data symbols from a data source (142) to a multicarrier modulator (145). Each modulator (201, 202, 203) within the multicarrier modulator (145) is coupled to a corresponding gain adjuster (211, 212, 213) that distributes the available transmit power across various subcarriers. Power distribution, is determined in part, upon the noise sensitivity of the transmitted information. In accordance, data stream symbols of like sensitivity are grouped (520) and transmitted during defined time intervals. Each such group is assigned a unique transmission power level (530). At any given moment in time, all subcarrier transmission power levels will have an identical amplitude, thereby mitigating the impact of subchannel-to-subchannel interference.

Abstract: The invention has the object of offering a channel-selection-type demultiplexing circuit which is capable of interchanging the time slots of demultiplexed signals when demultiplexing ultra-high-speed multi-channel multiplexed signal stream without expanding the scale of the circuits, and does not require the scale of the circuits to be expanded even if the speed of the transmission path increases. The invention is a channel-selection-type demultiplexing circuit capable of demultiplexing signals to a desired output port during bit demultiplexing, instead of simply demultiplexing the bits as in conventional devices, which performs bit demultiplexing based on a frequency division clock after selecting the bit signals to be demultiplexed to the desired output port from the N-channel multiplexed signal stream based on channel selection information.

Abstract: An adaptive multiplexing/demultiplexing method, and a multiplexer/demultiplexer (MUX/DEMUX) using the same in an H.324 system, are provided. The adaptive MUX/DEMUX in the H.324 system includes one or more MUX/DEMUXs having different complexities, between an H.223/Annex A MUX/DEMUX and an H.223 MUX/DEMUX.

Abstract: In ATM networks, digital data in ATM cells are sent to a destination node over a connection made up of more than one transmission link in round robin fashion. This is called inverse multiplexing. Suitable transmission links are selected among a plurality of provisionable transmission links according to some selection criteria. According to some embodiments of the invention, the selection criteria are minimum delay and maximum bandwidth.

Abstract: An asynchronous transfer mode inverse multiplexed communication system is disclosed wherein a series of communication cells are multiplexed over a set of communication links. Each communication cell includes a framing bit of a predetermined framing bit stream for each communication link and a control channel bit of a control message for each communication link. Inbound communication cells from each communication link are aligned according to the corresponding framing bit stream. The control message specifies an ordered list of logical identifiers to indicate a multiplexed sequence of transfer of the communication cells over the communication links.

Abstract: A method and apparatus are disclosed which permit multipoint trunking among a plurality of network devices connected by a trunk comprising at least two physical links. A trunk control message protocol (TCMP) is described which assures that message traffic may be delivered to the respective devices over the individual links of the trunk prior to inclusion of the respective links as active links in the trunk. The trunk acts as a single network port for each of the devices utilizing the trunk and is layered over a plurality of media access control (MAC) ports which interface to the respective links. The disclosed trunking technique and apparatus permit the bandwidth of the trunk to be increased in increments through the addition of links to the trunk.

Abstract: A system and method for converting data between a multi-bit time division multiplexed (TDM) bus and a faster single-bit TDM bus, wherein each TDM bus communicates data by means of frames, each frame comprising a fixed number of slots and each slot comprising a fixed number of bits, the system comprising digital circuitry for establishing a clock rate R.sub.SB for the faster single-bit TDM bus that has the following relationship to a clock rate R.sub.MB for the multi-bit TDM bus: R.sub.SB =R.sub.MB *((slots per frame)*(bits per slot)+1).div.(slots per frame).

Abstract: The transmission distance for DDS subscriber lines over a repeaterless four-wire link is extended to customer premises beyond the standard four-wire loop range of approximately 18 kft (56 kbps, 56 kbps with secondary channel capability, and 64 kbps) by employing commercially available ISDN transceiver chip hardware to multiplex a DDS data channel into quarter-rate (2B1Q) ISDN channels. At least one of a signalling channel and an out-of-band maintenance channel is used to convey differential delay compensation information, without modifying the framing structure of the transported channels, or requiring additional bandwidth for a separate framing channel.

Abstract: Apparatus for linking multiple baseband telephone lines to provide broadband communication. The apparatus comprises a broadband port, a plurality of baseband ports, and a controller. The broadband port provides connection to a broadband device or broadband communication line. The baseband ports provide connection to baseband communication lines. The controller integrates baseband data streams accepted at the baseband ports into a broadband data stream for transmission at the broadband port, and/or demultiplexes a broadband data stream received at the broadband port into baseband streams for transmission at the baseband ports. The baseband data include message data corresponding to the message data of the broadband stream, and control data describing an interrelationship among the message data, for controlling integrating of said baseband message data. The telephone numbers of baseband communication lines for use by the controller are automatically determined.

Abstract: An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.

Abstract: A communication system featuring a plurality of nodes in which at least one node is implemented with adaptive driver software following a load balancing scheme that takes into account packet characteristics associated with the data traffic load before dynamically distributing the data traffic among multiple communication channels. Of these communication channels, only one channel is allowed to receive data requests and all of the channels are allowed to transfer data packet(s) to the data requesting node.

Abstract: A pulse shaping filter for the .pi./4-shift QPSK modulator employed in IS-54 and JDC. The pulse shaping filter includes symbol determining circuits of the I-channel and the Q-channel, demultiplexers for inverse multiplexing each of the input signal value from the symbol determining circuits, a plurality of shift registers for shifting data from each of the demultiplexers according to odd and even symbol clock, a multiplexer for multiplexing each data from the shift registers to produce the corresponding address values, a plurality of ROM tables for storing the multiplexed address value, and a multiplexing and adding unit for multiplexing the address value stored in the ROM tables and adding the resulting multiplexed value.

Abstract: A multi-rate transmission system (10) includes a receive section (12) and a transmit section (14). The receive section includes a receiver (16), a clock recovery unit (18), and a serial to parallel converter (20) all operating at a first clock rate (M). The receiver (16) also has a frame recovery unit (22) that operates at any of a plurality of clock rates, including the first clock rate (M) and a second clock rate (M/n). When the frame recovery unit operates at the first clock rate (M), frame information received by the receiver section (12) has unique bits occupying each bit position associated with each clock pulse of the first clock rate (M). When the frame recovery unit (22) operates at the second clock rate (M/n), each unique bit of the frame information occupies a number of bit positions according to a ratio of the first clock rate (M) to the second clock rate (M/n). Similar operation occurs with respect to a frame formatter (30) in the transmit section (14) of the multi-rate transmission system (10).

Abstract: A method for formatting broadcast data for transmission on an uplink carrier to a satellite is provided which combines data streams from a number of service providers into parallel streams on uplink carriers to allow for efficient and economic use of the space segment. Bits in a program are assembled into a first number of prime rate increments having uniform and predetermined rates. A frame having a predetermined duration is generated which comprises each of the prime rate increments and a frame header. The frame is divided into symbols, each of the symbols comprising a predetermined and consecutive number of the program bits. The symbols are demultiplexed into a second number of parallel prime rate channels, with the symbols being provided in ascending order across the prime rate channels so as to separate consecutive symbols. The prime rate channels each comprise a prime rate channel synchronization header for recovering the prime rate channels at said remote receiver units.

Abstract: A method for connecting a local and a remote device using a plurality of telephone lines is disclosed. The remote device calls the local device on one of the telephone lines to establish a first telephone connection. The local device sends the other telephone numbers to the remote device on the first telephone connection. The remote device can then establish additional telephone connections. Once connections are established, the two devices can divide a data stream into smaller components. These components are sent via these telephone connections. These components are received by the receiving devices and combined to recover the original data stream. One of the application of the present invention is videophone.

Abstract: A channelized protection circuit for protecting the front-end of a receiver rom the detrimental effects of interference signals within the bandwidth of received signals is disclosed.

Abstract: A multicarrier transmission system (100) supports different desired error rates within a data symbol stream by manipulating subcarrier transmission characteristics for multiple subcarriers. A data symbol stream obtained for transmission is segmented into multiple substreams, and assigned to subcarriers based on error protection requirements (310, 320, 330). The transmission characteristics of the subcarriers are manipulated, according to a selected transmission configuration, to effect the combined error protection requirements (350, 360). Preferably, the subcarriers are modulated by allocating available power based on the relative error protection required for the substreams (360).

Abstract: A time division switching matrix capable of effecting rate conversion comprises a plurality of serial inputs for connection to respective serial input links, each capable of carrying time division multiplexed PCM channels, a plurality of serial outputs for connection to respective serial output links, each capable of carrying time division multiplexed PCM channels, and a serial-to-parallel converter associated with each input for converting a serial input stream to parallel format, each said serial-to-parallel converter being independently configurable to produce the same net parallel throughput regardless of the bit rate of the associated input link. The serial-to-parallel converters are staggered length shift registers. The output side of the switching matrix can be similarly configured.

Abstract: A digital signal transmission system operates in a mode for transmitting multiplexed signals as a serial digital signal and in a mode for transmitting only a predetermined signal. A transmitter of the system includes a first control circuit which, in a particular signal transmission mode, places only a particular signal processing circuit block for transmitting a particular signal in an operative state and places in an inoperative state a multiplexer circuit block for multiplexing the predetermined signal with at least one other signal. In a multiplexed transmission mode, the first control circuit places in an operative state only the multiplexer circuit block and places in an inoperative state the particular signal processing circuit block.

Abstract: A digital mobile communication system comprises a mobile station(MS) with a facsimile adapter(2), a first telefax terminal(1) connected to the adapter, a mobile network(BSS, MSC), an interworking unit(32) with a second facsimile adapter(33). A high-speed transparent rate-adapted facsimile connection is set up between the telefax terminals. The number of parallel traffic channels(ch0-chn) allocated to the high-speed data connection is such that the maximum data rate of the data connection is higher than the allowed maximum 10 data rate of the telefax terminals(1,10). The telefax terminals may negotiate the facsimile data rate. The second facsimile adapter(33) monitors the negotiation and selects, on the basis of the negotiated facsimile data rate, the most effective channel coding available for the data connection.

Abstract: A communications network (10) includes nodes (18) in which switched channelizers (32) decompose wideband signals into narrowband signals and route the narrowband signals to specified demodulators (34). The switched channelizers (32) serve as building blocks which may be coupled together in parallel and in series. Switch portions (28) of switched channelizers (32) may couple together so that the switched channelizers (32) form interconnected switched channelizer groups (54). Within an interconnected switched channelizer group (54), any channel from any wideband signal may be routed to any demodulator (34).

Abstract: A system adaptively determines the number of spread codes to use and a type of multi-valued modulation system based on the station of the system. Transmission information is divided into a number of sequences equal to the number of used spread codes. These sequences are error correction encoded, primarily modulated according to a selected one of a plurality of types of multi-valued modulation schemes, secondarily modulated by the selected spread codes, and transmitted.

Abstract: The system operates in a wireless communication system (200) which has a plurality of wireless communication channels (501, 502) controlled by a switching center (212) and the system includes an intelligent peripheral (30) in communication with the switching center (212) and an inverse multiplexer (38) responsive to the intelligent peripheral (30). The inverse multiplexer (38) separates a broadband communication signal (100) into a plurality of portions (301, 302) and the intelligent peripheral (30) causes the switching center (212) to transmit a first portion (301) of the broadband communication signal (100) over a first wireless communication channel (501) and to transmit a second portion of the broadband communication signal (302) over a second wireless communication channel (502). The switching center (212) controls the first wireless communication channel (501) independently of the second wireless communication channel (502).

Abstract: A method of transmitting digital signals which allows transmission of signals at a different transmission speed from that of composite serial digital signals, without any changes in the internal configurations of transmitting systems based on time division multiplexing, and a transmitter and a receiver used therefor. Dummy data is added to component serial digital signals inputted through an input terminal 10, with a decoder 21, a dummy data add circuit 22 and a 35/33 multiply circuit 23, to convert them into redundant component parallel digital signals of a sampling frequency twice the frequency of the composite parallel digital signals. The signals are converted into two series of pseudo composite serial signals with an encoder 24, a ten-fold multiply circuit 25 and a switching circuit 26, and then sent to a time division multiplexer for a plurality of composite serial digital signals.

Abstract: The present invention discloses a distributed data transfer system for transferring data among several processing units and an integrated data storage means, e.g., a memory sub-system. The distributed data transfer system includes a plurality of distributed data transfer means for connecting to the processing units. The distributed data transfer system further includes a distribution control means connected to the distributed data transfer means and the integrated data storage means. The distributed data transfer means, under the control of the distribution control means, is capable of transferring the data in divisible portions over a plurality of scheduled time periods. In a preferred embodiment, the distributed data transfer means further includes a plurality of data bus branches and a bus trunk connecting to the data bus branches. The distribution control means further includes a programmable control means for down-loading of control programs for controlling the distributed data transfers.

Abstract: A data communication device (500) which is capable of providing inverse multiplexing, avoids having to perform address offset calculations by storing the incoming data from each of its incoming data channels in corresponding data buffers having predefined data structures which eliminate the need for offset calculations during data transfers and protocol processing. The communication device (500) compares the actual address location that a particular byte, such as a frame count byte, is presently stored in the data buffer and the address location it should be stored in order to avoid using offset calculations. If the actual location the frame count (FC) byte is located in is not the desired location the frame count byte should be located, the communication device (500) programs its SCCs (508, 510) to commence storing subsequent data bytes in the appropriate address locations in each of the data buffers found in memory (538) so as to avoid having to perform offset calculations during memory accesses.

Abstract: 057517104An efficient connection technique maximizes the rate at which data are transferred among source and destination network cards of a distributed network switch. Such maximum data rates are achieved by interconnecting the network cards through a mesh backplane comprising a novel arrangement of direct and indirect paths between the cards and thereafter transferring the data over those paths. In accordance with the invention, the indirect data path utilizes an additional network card of the switch as a 2-hop relay to provide transfer rate efficiency between the source and destination cards.

Abstract: A demultiplexer (10) includes an input stage (12) that receives a serial data stream having a plurality of m-bit sections at a first clock rate. The input stage converts successive n-bit portions of each m-bit section into a first n-bit parallel output at a second clock rate. An intermediary stage (14) receives the first n-bit parallel output and generates a second n-bit parallel output at the second clock rate. The first n-bit parallel output corresponds to a different portion of an m-bit section than the second n-bit parallel output. An output stage (16) receives the first n-bit parallel output from the input stage (12) and the second n-bit parallel output from the intermediary stage (14). The output stage (10) places the first n-bit parallel output onto an output bus (36) having a width of m-bitlines at an earlier instance in time than the placement of the second n-bit parallel output.

Abstract: The invention relates to a signal processing apparatus and a signal processing method. The channel unit of the apparatus includes a plurality of channel data sending units to transmit a plurality of sets of channel data to a multiplexing unit. Part of the channel data sending units are connected to the timing signal line so that channel data from these channel data sending units are inserted into empty slots of the timing signals and are transmitted to the multiplexing unit through the timing signal line. The multiplexing unit of the apparatus includes a channel data separating unit for separating the channel data from the timing signals, and a channel data multiplexing unit for multiplexing the channel data transmitted through the data signal line and the channel data separated by the channel data separating unit. With this structure, data can be superposed on the timing signals used for data insertion and data extraction, thereby greatly increasing the number of channels included in the channel unit.

Abstract: A multiplexer includes an n-th stage as a final output stage (n=integer, 2.ltoreq.n); j stages (j=integer, 1.ltoreq.j.ltoreq.n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the clock signal with the serial data; and a j-th stage including m.sup.n-j-1 (m=integer, 2.ltoreq.m) multiplexer blocks, each multiplexer block including D flip-flops and having data input terminals for receiving m parallel data inputs and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, and converting the parallel data into serial data in response to the second clock signal. The multiplexer further includes a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages for delaying the data input by a variable delay time.

Abstract: An interface unit having a digital hierarchy interface function for a communication device has parts disposed on a printed-wiring board in a Layout to maintain desired interface unit characteristics. The interface unit includes a plurality of parallel B/U converter blocks for converting bipolar signals in a plurality of channels into a plurality of unipolar signals, respectively, a plurality of parallel U/B converter blocks for converting unipolar signals in a plurality of channels into a plurality of bipolar signals, respectively, a connector disposed near the B/U converter blocks for connecting the B/U converter blocks to an external device, a shared processor LSI circuit connected to the B/U converter blocks and the U/B converter blocks and disposed near the U/B converter blocks, for interfacing the signals in the channels at a low speed, and a printed-wiring board supporting the B/U converter blocks, the U/B converter blocks, the connector, and the shared processor LSI circuit.

Abstract: In a method of routing cells in an asynchronous time-division multiplex switching network interconnecting input switches and output switches via switches, each input switch can be connected to each output switch via at least two paths. The transmission of a sequence of cells of a given call between one input switch, called the call input switch, and one output switch, called the call output switch, comprises the following steps:determining the set of N possible paths between the call input switch and the call output switch,setting up N sub-connections corresponding to the N possible paths,in the call input switch, systematically and equitably distributing the cells of the sequence to the N sub-connections, andin the call output switch, assembling the cells of the sequence to reconstitute the sequence.

Abstract: Methods and apparatus for inserting data into an encoded data stream are disclosed. In accordance with the disclosed methods data is inserted into an encoded data stream while maintaining MPEG-2 compliance. The disclosed methods achieve data reduction required to make room for the data to be added by removing certain data elements of an encoded data stream, such as high frequency discrete cosine transform coefficients, which can be removed with minimal impact on picture quality and without disturbing the data stream's compliance with MPEG 2. In a first embodiment, data reduction to make room for the data to be inserted is performed by depacketizing the encoded data, performing a data reduction operation thereon, and then re-packetizing the encoded data. The reduced rate data stream is then multiplexed with the data to be inserted. In a second embodiment data reduction is performed by combining the contents of two or more consecutive transport data packets, e.g.

Abstract: The invention relates to a method and an arrangement for dynamic allocation of multiple carrier wave channels for multiple access by frequency division multiplexing. the invention provides a number of mobile units with the possibility of flexible data speed and continuous transmission. On the fixed side, the number of transmitters and receivers can be minimized by utilizing broadband receivers which serve a number of mobiles. According to the invention, a wider frequency band is divided into a number of subbands with a modulated carrier wave in each subband. To vary the transmission speed, such a number of subbands is allocated as is needed by each user in order to cover the data clock requirement. Broadband transmitters/receivers handle the transmission over the entire accessible band. Oversampling is preferably carried out in the frequency demultiplexing in order to permit the best sampling time to be selected for the different frequency gaps (FIG. 2).

Abstract: A high speed data transfer mechanism for transferring files from a transmission host across a data link to a receiver host. First, data is presented to a data splitter. The data splitter separates the input data stream into N separate substreams by packaging data into packets, which may be of different sizes. As data is packetized, each packet is sent and presented to a separate data transmitter. Data is sent to the array of transmitter in round-robin fashion such that the data is first presented to the first transmitter, then to the second transmitter, and so on until each transmitter has been sent a packet, then the first transmitter is sent another, and so on, until all data packets have been sent to a transmitter. A receiving side of the mechanism then initializes as many receivers as needed, or as many data receive substreams as are required using as many receivers as are available, ideally an equal number to the transmitters.

Abstract: The method allows performing the multiplexing of audio-visual streams, coded according to standard MPEG1, to be sent to remote equipment where demultiplexing and decoding occur. The method takes into account the trend of the occupancy of the input buffers of the remote decoders in order to avoid possible underflow or overflow conditions. For this purpose a multiplexed stream is constructed, composed of packets of variable sizes, by choosing the streams on the basis of the urgency to receive data that the demultiplexing buffers BDi have in order not to become empty.

Abstract: A signal multiplexing apparatus using multiconnection, comprising an input signal interface circuit for inputting a DS1 (or DS1E) signal, a video signal and an ATM cell signal, an input signal processing multiport RAM having a plurality of ports for receiving data from the input signal interface circuit, an input signal control circuit for controlling the input signal processing multiport RAM, and an output signal address generation/multiplexing circuit connected to the input signal processing multiport RAM. The output signal address generation/multiplexing circuit reads data from the input signal processing multiport RAM and multiplexes the read data into a desired format.

Abstract: A signal receiving and a signal transmitting unit converts an information carrying signal received at a first transmission rate to an information carrying signal transmitted at a second transmission rate that differs from the first transmission rate. Several inputs and outputs are available, each input structured for a transmission rate that is different from the transmission rates of remaining inputs, and each output structured for a transmission rate that is different from the transmission rates of remaining outputs. One signal receiving input can be connected to one signal transmitting output depending on signals occurring on one or more control conductors, wherein a selected control conductor and/or selected signal information selects and initiates a conversion mode having a selected conversion index.

Abstract: To extend the transmission distance for basic rate integrated services digital network (ISDN) communications between a first site and a second site, the basic rate ISDN channel is demultiplexed onto a pair of half-rate digital subscriber loop channels, which employ an out of band maintenance channel to convey differential delay compensation information, but without modifying the framing structure of the transported channels, or requiring additional bandwidth for a separate framing channel. Halving the data rate, to increase the distance over which the basic rate ISDN channel may be transported, operates as a trade-off against loop loss, while still complying with ANSI standards.

Abstract: A LAN-WAN-LAN communication method and apparatus for performing communication between a LAN on a transmitting side and a LAN on a receiving side via a wide area network within limits of an allocated band includes a demultiplexer/multiplexer unit for demultiplexing data, which has been received from the LAN on the transmitting side, into data constituting the smallest units of information and transmitting this data via a plurality of lines. Then, data, which is sent to the receiving side via each line, is multiplexed on the receiving side and the multiplexed data is sent to the LAN on the receiving side. A traffic monitoring unit is provided for monitoring traffic between LANS. A band is obtained, which is required for communication between LANs based upon the traffic. Communication between LANs is performed by increasing, decreasing or maintaining the number of lines, which are used in communication between LANS, based upon the obtained band.

Abstract: A video data transmitter includes: chrominance-data multiplexer which multiplexes parallel data obtained by digitizing a chrominance signal Pb, which is a component signal of an analog HDTV video signal, with parallel data obtained by digitizing a chrominance signal Pr; a word multiplexer which multiplexes parallel data obtained by digitizing a luminance signal Y, which is a component signal of analog HDTV video signal, with the output data of the chrominance-data multiplexer, and a parallel-to-serial converter which converts the parallel data output from the word multiplexer. A video data receiver includes a serial-to-parallel converter which converts received serial data into parallel data and a word separator which separates the output data of the serial-to-parallel converter into parallel data in the Y channel and parallel data in the Pb/Pr channel.