Abstract: Methods and systems are described for sampling a data signal using a data sampler operating in a data signal processing path having a decision threshold associated with a decision feedback equalization (DFE) correction factor, measuring an eye opening of the data signal by adjusting a decision threshold of a spare sampler operating outside of the data signal processing path to determine a center-of-eye value for the decision threshold of the spare sampler, initializing the decision threshold of the spare sampler based on the center-of-eye value and the DFE correction factor, generating respective sets of phase-error signals for the spare sampler and the data sampler responsive to a detection of a predetermined data pattern, and updating the decision threshold of the data sampler based on an accumulation of differences in phase-error signals of the respective sets of phase-error signals.

Abstract: Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error.

Abstract: A clock recovery circuit includes a multi-phase sampling circuit, a phase comparison circuit, a recovery clock generation circuit, and a phase shifter. The multi-phase sampling circuit includes edge samplers and data samplers. A data signal is input to each of the edge samplers and each of the data samplers. The phase comparison circuit is disposed at an output side of the multi-phase sampling circuit. The recovery clock generation circuit is configured to output multi-phase clock signals. The phase shifter is disposed between the recovery clock generation circuit and the multi-phase sampling circuit and configured to generate a plurality of clock signals to be supplied to the multi-phase sampling circuit by shifting a phase of a first one of the multi-phase clock signals output from the recovery clock generation circuit by a shift amount different from a shift amount of a second one of the multi-phase clock signals.

Abstract: A terminal apparatus (1) is provided with a coding unit (7), a decoding unit (2), and a control unit (5) for controlling the coding unit and the decoding unit individually. Under control of the control unit, the coding unit codes a payload, a first number of error corrections (3), and identification information (6) that are to be transmitted, on the basis of a method indicated by the already-transmitted identification information to thereby generate first coded data. The decoding unit decodes newly-received second coded data on the basis of a method indicated by the identification information included in a decoding result of the already-received second coded data.

Abstract: A backhaul radio is disclosed that operates in multipath propagation environments such as obstructed LOS conditions with uncoordinated interference sources in the same operating band. Such a backhaul radio may use adaptive beamforming and sample alignment at the transmitter to enhance the link performance. Such backhaul radios may communicate with each other to compute and apply optimal beamforming parameters for a particular propagation environment through a closed-loop feedback mechanism.

Abstract: An apparatus and method is provided that compensates for the supply droops to minimize strobe shifts and to regain eye margin. The apparatus includes a droop detector to detect voltage droops at one or more trip (or threshold) levels and these detected voltage droops are translated to a shift in clock phase setting. For example, propagation delay of a delay locked loop (DLL) and/or clock edge selection from a phase interpolator (PI) is adjusted according to the detected voltage droop levels to maintain a trained relationship between the sampling clock strobe and data eye. A lookup table is used to determine a PI code or a DLL propagation delay code corresponding to a voltage droop level.

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract: An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.

Abstract: A phase lock loop circuit includes a phase frequency detector, a voltage controlled oscillator, a phase interpolator, a clock signal selector, a selection module, a multiplexer, and a divider. The phase frequency detector compares phases of a reference clock and frequency divided output signals and generates an error signal. The voltage controlled oscillator, based on the error signal, generates a phase lock loop output signal and output clock signals. The phase interpolator phase interpolates the output clock signals to generate an interpolator output signal. The clock signal selector selects one of the output clock signals. The selection module generates a selection signal based on states of the interpolator output and selected output clock signals. The multiplexer, based on the selection signal, selects the interpolator output signal or the selected output clock signal. The divider frequency divides an output of the multiplexer to provide the frequency divided output signal.

Abstract: A radar device comprises a data communication input interface configured to receive a data clock signal for a data bus and an analog to digital converter configured to sample a signal at time instants given by a sampling clock signal. In an implementation, a sampling clock generation circuit is configured to generate the sampling clock signal based on the data clock signal.

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

Abstract: An apparatus for performing decision feedback equalizer (DFE) adaptation control is provided. The apparatus includes arithmetic circuits, slicers, sample and hold circuits, a phase detector and a control circuit for related operations. The control circuit generates parameters at least according to an error sample value and data sample values, and dynamically updates the parameters based on at least one predetermined rule to perform the DFE adaptation control. The parameters include a first parameter, another parameter and a factor adjustment parameter. Regarding at least one data pattern, the control circuit selectively replaces the error sample value with a predetermined value according to whether a temporary storage value of the error sample value conforms to a predetermined condition to control the other parameter and the first parameter, in order to prevent triggering an unstable effect and thereby prevent abnormal operations.

Abstract: Embodiments of the present invention may provide a device for monitoring electric power at the distribution level. The device may include an analog-to-digital converter (ADC) to convert an input signal into digital samples at time intervals, a receiver to generate a pulse-per-second (PPS) signal, an oscillator to generate an oscillator signal, and a data processor coupled to the ADC, the receiver, and the oscillator. The data processor may include a counter to measure an oscillator frequency of the oscillator signal at each pulse of the PPS signal, an adjuster to adjust a timer period register value, and a timer to adjust the time intervals based on the adjusted timer period register value. Based on the digital samples, the data processor may generate a plurality of metrics, which may include one or more measurements of frequency, magnitude, phase, harmonic level, signal-to-noise ratio, sag, and swell of the input signal.

Abstract: Embodiments of a clock synchronization unit of an All Digital Phase-Locked Loop (ADPLL), a successive approximation register (SAR) Time-to-Digital Converter (TDC) of an ADPLL and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, a clock synchronization unit of an ADPLL includes a two-flop synchronizer, a phase frequency detector (PFD) connected to the two-flop synchronizer, and a synchronization control circuit configured to control the two-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal and to control the two-flop synchronizer and the PFD to replace a performance of the clock synchronization between the reference clock input signal and the divided clock input signal with a PFD operation. Other embodiments are also described.

Abstract: A data receiver circuit may include: a delay circuit suitable for delaying first and second strobe signals and generating delayed first and second strobe signals; a first receiver circuit suitable for sampling data in synchronization with the delayed first strobe signal; a second receiver circuit suitable for sampling the data in synchronization with the delayed second strobe signal; an enable signal generation circuit suitable for generating an enable signal indicating whether the data transitioned; a transition level generation circuit suitable for generating a transition level signal indicating a transition direction of the data; a phase shift circuit suitable for shifting the phase of the delayed first strobe signal by a set degree and generating a shifted first strobe signal; a sampling circuit suitable for sampling the data in synchronization with the shifted first strobe signal and generating a sampling result; and a control logic suitable for changing a delay value of the delay circuit in response to

Abstract: Disclosed is the delta-sigma amplitude modulation system. Operation of amplitude modulator is based on the use of the second-order delta-sigma modulator. Polar delta-sigma bit-stream is nonlinearly processed in the negative feedback of delta-sigma modulator to produce an amplitude modulated signal. All information about modulating signal is contained in both envelope and carrier of the modulated signal. Thus, because of a dual nature of modulated signal, one can detect zero-crossings of a carrier, using sign detector, to obtain a polar delta-sigma bit stream. By demodulation (low-pass filtering) this polar bit-stream modulating signal is obtained. The main advantages of a proposed system are: simple digital amplitude modulator and simple demodulator which can be integrated in one IC chip. Because of non-positional nature of delta-sigma bit stream, proposed system is robust to channel errors.

Abstract: According to one embodiment, an equalizer circuit includes a nonlinear equalizer including: a determination circuit configured to generate a second signal indicating a digital value of a first signal, based on a first clock signal; a clock generation circuit configured to generate a second clock signal having a time constant of a falling edge larger than a time constant of a rising edge, based on the first clock signal; and a feedback circuit configured to generate a third signal by feeding back the second signal to the first signal, based on the second clock signal.

Abstract: A method allowing a receiver device of a wireless communication system to receive a useful signal emitted by an emitter device. The useful signal corresponding to a signal, the phase or frequency of which is modulated by a sequence of two-state symbols corresponding to a sequence of binary data. A temporal envelope of the useful signal is detected and compared to a preset threshold value. Transitions between consecutive useful-signal symbols are detected, on the basis of the result of the comparison. A sequence of binary data is extracted from the useful signal depending on the detected transitions.

Abstract: A method for efficient generation of a narrowband IoT uplink signal includes generating an under-sampled sequence of samples of a narrowband IoT uplink signal, identifying symbol boundaries in the sequence of samples that do not correspond to sample times, for each symbol boundary that does not correspond to one of the sample times: extrapolating, from a signal phase value for a sample at a last sample time before the symbol boundary, a signal phase value for a sample at a first sample time after the symbol boundary; calculating and applying a phase jump to the sample at the first sample time after the symbol boundary to generate a new phase value for the sample at the first sample time after the symbol boundary, wherein the phase jump is applied from the phase value extrapolated from the last sample time before the symbol boundary; and using the new phase value for the first sample time after the symbol boundary to calculate amplitude of the sample at the first sample time after the symbol boundary.

Abstract: A data recovery circuit adjusts skew between a first and second clock signals when a signal level of recovered data changes relative to first reference level between a first timing of the first clock signal and a second timing of the second clock signal. Prior to adjusting the skew, a first signal level of the recovered data at the first timing is compared to a second and/or a third reference level. A second signal level at the second timing is compared to the second and/or the third reference level. The skew is adjusted based on a first sign of an error of the first signal level relative to one of the second and third reference levels. The first sign is opposite to a second sign of an error of the second signal level relative to another one of the second and third reference levels.

Abstract: An example circuit includes: a transmitter configured to transmit a clock pattern based on a transmit clock; a receiver, coupled to the transmitter, configured to sample the clock pattern based on a receive clock to generate a bit pattern, where there is a non-zero frequency difference between the transmit clock and the receive clock; a phase interpolator (PI) configured to add a phase shift to a source clock to supply one of the transmit clock or the receive clock; and a test circuit configured to apply adjustments to the phase shift over a time period and determine a phase distribution of the PI based on changes in the bit pattern over the time period.

Abstract: A terminal device, useable in a wireless telecommunications system, including: a transceiver operable to perform radio signalling with a base station using a predetermined narrowband of bandwidth of the wireless telecommunications system; a controller operable to: control the transceiver to receive control information from the base station in a coverage extension mode. The control information schedules radio resources for radio signalling with the base station. In the coverage extension mode, transmission of the control information to the terminal device is repeated plural times. The control information is coded according to the number of times transmission of the control information is repeated. The control information is decoded to determine the number of times transmission of the control information is repeated.

Abstract: Methods and systems are described for receiving, at a data-driven phase comparator circuit, a plurality of data signals in parallel and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators, generating a plurality of partial phase-error signals using the partial phase comparators, each partial phase-error signal generated by receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals and responsive to a determination that a transition occurred in the corresponding data signal, generating the partial phase-error signal based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal, and generating a composite phase-error signal by summing the plurality of partial phase error signals for setting a local oscillator in a lock condition.

Abstract: A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals based. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

Abstract: Methods and systems are described for generating, using a voltage-controlled oscillator (VCO), a plurality of phases of a local clock signal, generating a phase-error signal using a phase comparator receive a phase of the local clock signal and a reference clock signal, and configured to output the phase-error signal, generating a frequency-lock assist (FLA) signal using a FLA circuit receiving one or more phases of the local clock signal and the reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal, and generating a VCO control signal using an error accumulator circuit receiving the phase-error signal and the FLA signal, and responsively providing the VCO control signal to the VCO to lock the local clock signal to the reference clock signal.

Abstract: A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract: A clock and data recovery (CDR) device is disclosed. The CDR device comprises a sensing unit and an interpolator. The sensing unit is configured to detect a data center, a left data edge and a right data edge of a data on a data stream in a communication system, using a set of thresholds, in response to a first clock signal for sampling the data center, a second clock signal for sampling the left data edge and a third clock signal for sampling the right data edge. Each of the thresholds is related to a different level among data levels of the data. The interpolator is configured to generate the first clock signal based on information on the data center, and generate the second clock signal and the third clock signal based on information on the left and right data edges.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal.

Abstract: Methods, apparatuses, and systems are described related a data receiver circuit having a pair of offset edge samplers to sample a data signal, at an edge sampling time between data samples, with respect to different reference levels. A clock-data recovery (CDR) circuit of the receiver circuit may determine an A-count that corresponds to a number of times the signal level of the data signal at the edge sampling time is between the reference levels of the offset edge samples to provide a signal integrity metric for the receiver circuit. The CDR circuit may dynamically update its settings based on the A-count.

Abstract: In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one Nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the clock signal other than the fundamental frequency. A digital-to-analog converter (DAC) digitizes an analog input signal based on the filtered clock signal. Attenuating noise in the Nyquist zones reduces jitter of the filtered clock signal, and passing at least one harmonic frequency of the clock signal other than the fundamental frequency limits the degradation of the slew rate of the clock signal. As a result, the filtered clock signal increases the signal-to-noise ratio of the output of the DAC.

Abstract: A receiving circuit includes a deserializer circuit configured to convert serial data to parallel data in accordance with an operating clock, a phase difference detection circuit configured to detect a phase difference between the operating clock and the serial data on the basis of the parallel data, a control circuit configured to determine a phase adjustment amount for shifting a phase of the operating clock by 1 bit of the serial data in accordance with a result of integration of the phase difference when a separation of the parallel data output from the deserializer circuit is not logically correct, and a phase interpolator circuit configured to cause the phase of the operating clock to shift by the 1 bit of the serial data by using the phase adjustment amount in accordance with the result of the integration of the phase difference.

Abstract: A reference voltage block integrated in a programmable logic device (PLD) includes: an accumulator comprising an adder and a register and configured to receive a digital reference value and generate a carry out signal; a low-pass filter configured to receive the carry out signal from the accumulator and generate a filtered signal; and a variable analog gain amplifier configured to amplify the filtered signal using a gain selected from a predetermined set of gains and generate a reference voltage output signal. The PLD includes a programmable fabric and a signal wrapper that is configured to provide signals between the reference voltage block and the programmable fabric. The digital reference value and the predetermined set of gains of the reference voltage block are programmably using the programmable fabric and fed to the reference voltage block via the signal wrapper.

Abstract: An eye pattern measurement apparatus includes: an eye pattern monitoring device, performing first sampling on a data signal by sequentially using scan clock signals having different phases to obtain a plurality of scan data signals; and a data aligning device, connected to the eye pattern monitoring device, receiving the scan data signals outputted by the eye pattern monitoring device, performing phase-shift on the first clock signal to generate a synchronization clock signal, synchronizing the scan data signals with the synchronization clock signal, and outputting the synchronized scan data signals.

Abstract: A transceiver comprises: a sampling phase optimization stage comprising: a first interpolator; a first equalizer coupled to the first interpolator; a first optimizer coupled to the first equalizer; and an output; and an equalization stage coupled to the output and comprising: a buffer; a second interpolator coupled to the buffer; and a second equalizer coupled to the second interpolator. A method comprising: receiving an optical burst signal; determining an optimum sampling phase based on a portion of a digital signal representing the optical burst signal; and equalizing all of the digital signal using the optimum sampling phase.

Abstract: A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals based. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

Abstract: A method includes, in a transceiver (24), receiving from a repeater (32) a received signal, which includes a desired signal for reception and an undesired replica of a transmitted signal that was transmitted from the transceiver and retransmitted by the repeater. A local copy of the transmitted signal is generated in the transceiver. A filter response that, when applied to the transmitted signal before transmission, compensates for a difference in spectral response between the local copy and the undesired replica, is estimated in the transceiver. The undesired replica of the transmitted signal, which is received in the received signal, is matched with the local copy of the transmitted signal, by at least pre-filtering the transmitted signal before transmission with the estimated filter response. Interference caused by the undesired replica to the desired signal is canceled, by combining the local copy and the received signal.

Abstract: An apparatus is provided which comprises: a data slicer to receive first data sampled by a data clock; an edge slicer to receive second data sampled by an edge clock; and a Least Mean Square (LMS) circuitry coupled to the data and edge slicers, wherein the LSM circuitry is to generate a code to adjust a phase of one of data clock and/or edge clock relative to one another.

Abstract: This invention discloses a multicarrier communication system that includes a transmitter equipment and a receiver equipment. According to a timing scheme, the transmitter equipment processes multiple original symbols for transmission on multiple subcarrier channels, and the receiver equipment processes and detects multiple received symbols from the multiple subcarrier channels. During a time frame of data transmission, the initial three of the original symbols for each of the subcarrier channels are three pilot symbols, forming a preamble. The three preambles of every consecutive three of the subcarrier channels form a preamble unit. All the pilot symbols of the preamble unit are expressed as a 3×3 matrix. When the center pilot symbol of the preamble unit is normalized to 1 or j (i.e., the imaginary unit), the matrix is [ - j - j - j j 1 - j - j j - j ] ? ? or ? [ 1 1 1 - 1 j 1 1 - 1 1 ] .

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract: A parallel transfer rate converter inputs first parallel data with number of samples being S1 pieces in synchronism with a first clock, and outputs second parallel data with number of samples being S2=S1×(m/p) pieces (p is an integer equal to or larger than 1) in synchronism with a second clock having a frequency which is p/m times of a frequency of the first clock. A convolution operation device inputs the second parallel data in synchronism with the second clock, generates third parallel data with number of samples being S3=S2×(n/m) pieces (S3 is an integer equal to or larger than 1) by executing a convolution operation with a coefficient indicating a transmission characteristic to the second parallel data, and outputs the third parallel data in synchronism with the second clock.

Abstract: Embodiments include systems and methods for calibrating clocking circuits for improved jitter performance. Embodiments operate in context of a clocking circuit coupled with a transceiver system that has a receiver that tracks a recovered clock phase according to a tracking code. For example, candidate configurations can be identified, each corresponding to a different respective combination of parameter values for programmable clocking circuit parameters. For each candidate configuration, embodiments can configure the clocking system accordingly, and can sample the tracking code over a sample window to measure a tracking code spread for the candidate configuration. The clocking circuit can be programmed according to which of the candidate configurations manifested a minimum tracking code spread, thereby effectively configuring the clocking circuit for minimum jitter generation and optimizing jitter performance of the transceiver.

Abstract: A master unit for use within a distributed antenna system includes: re-sampling devices configured to output re-sampled digital downlink signals by re-sampling digital downlink signals at customized resample rates based on at least one factor, the re-sampled digital downlink signals having a smaller bandwidth than the digital downlink signals; and a framer configured to multiplex the re-sampled digital downlink signals and to generate a first frame that includes the re-sampled digital downlink signals as framed data for transport to one or more remote units of the distributed antenna system, wherein the one or more remote units of the distributed antenna system are configured to transmit radio frequency signals using at least one antenna, wherein the transmitted radio frequency signals are derived from the framed data of the first frame received from the master unit.

Abstract: A method of digital signal processing includes modeling a digitally-modulated radio frequency (RF) communication stream using a set of incoming samples of the stream collected from a single antenna. The stream includes a first signal, the first signal including a sequence of first digital symbols having a previous symbol and a current symbol. Each first digital symbol is chosen from a plurality of first possible values. The first signal is modulated by a first known RF communication protocol having unknown time-varying parameters, the parameters having estimated previous values from modeling the previous symbol using a previous interval of the samples corresponding to the previous symbol. The method further includes collecting a current interval of the samples, predicting current values of the parameters, deciding a value of the current symbol using maximum likelihood estimation, and estimating the current values of the parameters using maximum likelihood estimation.

Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

Abstract: Provided is an information processing apparatus including a sensor data obtaining unit configured to obtain predetermined information from a sensor, the sensor obtaining the predetermined information by sensing, and a key generation unit configured to generate key information for use in an authentication process, based on the information which is obtained by the sensor data obtaining unit during a predetermined period of time.

Abstract: The present disclosure is directed to waveform synchronization in multi-modal sensor networks. An example method includes providing a reference signal to a translation circuit. The method also includes generating, by the translation circuit, (i) a first synchronization signal capable of exciting a first emitter to produce a first wave in a first modality and (ii) a second synchronization signal capable of exciting a second emitter to produce a second wave in a second modality, wherein a modality is a domain within a form of energy. The method further includes producing, by the first emitter, first wave in the first modality and, by the second emitter, the second wave in the second modality, wherein the first wave is substantially directed toward a first sensor capable of interacting with the first wave, and wherein the second wave substantially directed toward a second sensor capable of interacting with the second wave.

Abstract: Various aspects of this disclosure describe measuring timing slack using an endpoint criticality sensor on a chip. A sensor circuit is attached to sensitive endpoints on the chip (e.g., logical gates in a timing critical path) so that the sensor circuit receives the endpoint's data signal and clock signal. The sensor circuit introduces skew between the data signal and the clock signal by delaying the data signal more than the clock signal, and compares skewed data signals to determine if an error occurs because of the induced skew. By delaying the data signal with different delay amounts and monitoring what delays cause errors, an amount of timing slack in the data signal and clock signal (e.g., margin to criticality) is measured during operation of the chip for relevant circuitry to the system implemented on the chip, compared to test circuitry operating while the chip is in a test mode.

Abstract: An encoder (250) comprises a core encoder (252) for encoding a low frequency component of the audio signal at the signal sampling rate (fs_in) and a spectral band replication-referred to as SBR-encoding unit (153, 254) for determining a plurality of SBR parameters. A plurality of the SBR parameters is determined such that a high frequency component of the audio signal can be approximated based on the low frequency component of the audio signal and the plurality of SBR parameters. A multiplexer (155) is adapted to generate an overall bitstream comprising the core encoded bitstream, the plurality of SBR parameters and an indication of one or more SBR encoder settings applied by the SBR encoder (153, 254); wherein the generated overall bitstream does not indicate that the core encoded bitstream has been determined by encoding the low frequency component at the signal sampling rate (fs_in).