Abstract: Certain aspects of the present disclosure relate to a method for compressed sensing (CS). The CS is a signal processing concept wherein significantly fewer sensor measurements than that suggested by Shannon/Nyquist sampling theorem can be used to recover signals with arbitrarily fine resolution. In this disclosure, the CS framework is applied for sensor signal processing in order to support low power robust sensors and reliable communication in Body Area Networks (BANs) for healthcare and fitness applications.

Abstract: An Ethernet physical layer circuit and a clock recovery method are provided. An analog-to-digital converter samples an analog input signal with a sampling clock to generate a digital input signal. A clock generator is coupled to the analog-to-digital converter, outputs the sampling clock to the analog-to-digital converter, and adjusts a phase of the sampling clock according to a phase control signal. The clock recovery circuit is coupled to the analog-to-digital converter and the clock generator, detects a timing error of the digital input signal at refresh stages in a lower energy consumption idle mode to obtain phase adjustment information, and generates the phase control signal based on the phase adjustment information at quiet stages in the low power idle mode. The clock generator correspondingly receives the phase control signal in the quiet stages to adjust the phase of the sampling clock.

Abstract: A hybrid clock data recovery circuit includes a linear phase detector configured to generate a recovered data signal by sampling an input data signal in response to a clock signal, and to generate up and down signals having a pulse width difference that is linearly proportional to a phase difference between the input data signal and the clock signal. An arbiter is configured to generate a bang-bang up signal representing that a phase of the input data signal leads a phase of the clock signal and a bang-bang down signal representing that the phase of the clock signal leads the phase of the input data signal based on the up and down signals. A digital loop filter is configured to generate a digital control code based on the bang-bang up and down signals. A digitally controlled oscillator is configured to generate an oscillating frequency of the clock signal in response to the digital control code, and to adjust the oscillating frequency of the clock signal in response to the up and down signals.

Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal; a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each receiver of the plurality of receivers receives the first reference signal and a corresponding control signal of the plurality of control signals, and further provides an output signal.

Abstract: Representative implementations of devices and techniques provide non-linearity detection and mitigation for a phase interpolator of a controlled oscillator circuit, such as a PLL. A bit stream output of a phase detector of the oscillator circuit is segmented according to multiple phase positions of the phase interpolator, forming a bit stream for each of the multiple phase positions. Each bit stream of each phase position is analyzed, and phase position errors may be detected and mitigated based on the contents of the bit streams.

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Abstract: A method is disclosed for relative positioning performed by a first mobile device that is one of a plurality of mobile devices. The method determines a first probe signal parameter that is indicative for a distance between the first mobile device and a second mobile device. The method obtains one or more further probe signal parameters. Each further probe signal parameter is indicative for a distance between two of the plurality of mobile devices. The method selects probe signal parameters of the first probe signal parameter and the further probe signal parameters for determining one or more relative positions between two or more of the plurality of mobile devices. The method determines one or more relative positions between two or more of the plurality of mobile devices at least based on the selected probe signal parameters. A corresponding apparatus, system and computer readable medium are also disclosed.

Abstract: A reference voltage block integrated in a programmable logic device (PLD) includes: an accumulator comprising an adder and a register and configured to receive a digital reference value and generate a carry out signal; a low-pass filter configured to receive the carry out signal from the accumulator and generate a filtered signal; and a variable analog gain amplifier configured to amplify the filtered signal using a gain selected from a predetermined set of gains and generate a reference voltage output signal. The PLD includes a programmable fabric and a signal wrapper that is configured to provide signals between the reference voltage block and the programmable fabric. The digital reference value and the predetermined set of gains of the reference voltage block are programmably using the programmable fabric and fed to the reference voltage block via the signal wrapper.

Abstract: Some embodiments include apparatuses and methods having a receiver unit included in a die and a measurement unit included in the die. The receiver unit includes a sampler to sample a first signal based on timing of a first clock signal to generate a second signal. The measurement unit is arranged to sample the first signal based on timing of a second clock signal to provide information for generation of a graph presenting an eye scan of the first signal. The second clock signal has a frequency asynchronous with a frequency of the first clock signal.

Abstract: Systems, methods, and apparatus for generating a clock signal using re-timer circuitry, including receiving an input data signal transmitted without a reference clock signal; comparing the input data signal with a re-timer clock signal to determine a frequency difference between the input data signal and the re-timer clock signal; determining a data rate of the input data signal based on the frequency difference between the input data signal and the re-timer clock signal; and generating, based on the data rate of the input data signal, a control signal for adjusting a frequency of the re-timer clock signal to frequency-lock the re-timer clock signal with the input data signal.

Abstract: An interference estimation method and a communication device configured to estimate interference. The interference estimation method can include determining a first communication channel of a first uplink communication signal of a first communication protocol and determining a second communication channel of a second downlink communication signal of a second communication protocol. The method can further include: determining frequency spacing between the first uplink communication signal and the second downlink communication signal; determining the PSD of the transmit signal within the receiver bandwidth of the second downlink communication signal; and determining the transmit noise floor from the first uplink communication signal in the receiver bandwidth. Power integration terms can be determined based on the overall PSD of the transmit signal from first uplink communication signal within the second downlink communication channel.

Abstract: A transmission/reception system 1 includes a transmission device 10 configured to transmit image data and a reception device 20 configured to receive the image data transmitted from the transmission device 10. The transmission device 10 includes a serializer 11, an encoding unit 12, a data buffering unit 13, a data selection unit 14, a counter 15, and a synchronization signal generation unit 16. The data buffering unit 13 buffers data every n bits in synchronization with the clock. The data selection unit 14 outputs m-bit data selected from the data buffered by the data buffering unit 13 on the basis of a count value from the counter 15.

Abstract: Embodiments disclose a method and an apparatus for detecting power of an uplink optical signal, an optical line terminal, and an optical network system. The method includes: separately generating a triggering signal that is used for detecting optical power for each uplink optical signal among multiple uplink optical signals to be detected, where the triggering signal of each uplink optical signal has same duration. The method also includes separately detecting power of each uplink optical signal in the duration of the triggering signal of each uplink optical signal.

Abstract: Methods, an encoder and a decoder are configured for transition between frames with different internal sampling rates. Linear predictive (LP) filter parameters are converted from a sampling rate S1 to a sampling rate S2. A power spectrum of a LP synthesis filter is computed, at the sampling rate S1, using the LP filter parameters. The power spectrum of the LP synthesis filter is modified to convert it from the sampling rate S1 to the sampling rate S2. The modified power spectrum of the LP synthesis filter is inverse transformed to determine autocorrelations of the LP synthesis filter at the sampling rate S2. The autocorrelations are used to compute the LP filter parameters at the sampling rate S2.

Abstract: A clock and data recovery device includes a data sampling module, a phase detection circuit, a frequency estimator, a clock generation module, and a data recovery module. The data sampling module samples input data according to first clock signals to generate data values, in which phases of the first clock signals are different from one another. The phase detection circuit detects a phase error of the input data according to at least one second clock signal, to generate an error signal. The frequency estimator generates an adjustment signal according to the error signal, a phase threshold value, and a frequency threshold value. The clock generation module generates the first clock signals and the at least one second clock signal according to the adjustment signal and a reference clock signal. The data recovery module generates recovered data corresponding to the input data according to the data values.

Abstract: Provided is a spectrophotometer having a sample container 30, a light-source unit 10 for casting measurement light into the sample container 30, a photodetector 40 for detecting light obtained from the sample container 30 illuminated with the measurement light, a light separator 20 placed between the light-source unit 10 and the sample container 30, an A/D converter 50 for converting detection signals from the photodetector 40 into digital signals, and an A/D conversion time controller 65 for controlling an A/D conversion time in the A/D converter 50. The A/D converter 50 receives, for each A/D conversion time, detection signals sequentially produced by the photodetector 40, and sequentially outputs values corresponding to the amounts of signals received. The A/D conversion time controller 65 controls the A/D conversion time at five times (preferably, ten times) the cycle of commercial power supplies or longer during wavelength-correctness validation of the light separator 20.

Abstract: A telecommunications system is provided that can re-sample a digitized signal at a resample rate that is based on one or more factors to better utilize bandwidth. The factors can include the bandwidth of the signal that the digitized signal represents, the amount of bandwidth owned or used by the carrier, the full bandwidth of the designated RF band, the bandwidth of the serial link, the frame length of the serial link, the segmentation of the frames on the serial link, and the capability of the equipment at the receiving end of a serial link. The re-sampled signal can be transmitted to another unit that is remote to the unit transmitting the signal. The other unit can include a re-sampling device that restores the re-sampled signal to a digital signal that can be converted to an analog signal for wireless transmission.

Abstract: A symbol boundary in a data packet having a guard interval preceding a preamble having a predetermined sequence of symbols is detected by receiving a signal representing a data packet; sampling the received signal at a sampling rate; estimating channel impulse responses from a set of samples in dependence on the predetermined sequence of symbols of the preamble; determining an energy value for each of a plurality of windows of channel impulse responses, each of the windows corresponding to W number of consecutive samples, the energy value for each of the windows being indicative of the total energy associated with the channel impulse responses of that window; determining which of the windows has the greatest energy value; and identifying the earliest sample of the consecutive W samples in said determined greatest energy window, the earliest sample being indicative of a symbol boundary for the preamble.

Abstract: A method and apparatus for generating a sampling frequency are provided. A signal is generated, of which frequency is a predetermined multiple of a reference clock, and a frequency offset in a channel is extracted from the entire frequency offset. The amount of shift is calculated by dividing the extracted frequency offset by a predetermined value, and a final sampling frequency is obtained by shifting the frequency of the generated signal by the amount of shift.

Abstract: A transmission apparatus configured to extract reception data and a first clock from a received signal and transmit the reception data based on a second clock synchronized with the first clock, the transmission apparatus includes: a detector configured to detect a frequency difference between the first clock and the second clock; a selector configured to select parallel data according to the frequency difference from a plurality of parallel data obtained by shifting bit patterns formed by bits of continuing “0” and continuing “1” by different number of the bits with each other, and a converter configured to convert the parallel data selected by the selector into serial data so as to be the second clock.

Abstract: Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

Abstract: A method and corresponding apparatus for aligning a data signal with a corresponding clock signal include oversampling the data signal based on the corresponding clock signal and generating corresponding data samples. An indication of skew between the data signal and the corresponding clock signal is detected based on data samples. A variable delay line coupled to the data signal is then adjusted based on the indication of skew detected. According to at least one example implementation, the data signal is oversampled based on the corresponding clock signal and multiple time-shifted versions of the corresponding clock signal. At least one signal of the corresponding clock signal and the multiple time-shifted versions of the corresponding clock signal is employed in sampling the data signal at a potential transition edge of the data signal.

Abstract: A telecommunications system is provided that can re-sample a digitized signal at a resample rate that is based on one or more factors to better utilize bandwidth. The factors can include the bandwidth of the signal that the digitized signal represents, the amount of bandwidth owned or used by the carrier, the full bandwidth of the designated RF band, the bandwidth of the serial link, the frame length of the serial link, the segmentation of the frames on the serial link, and the capability of the equipment at the receiving end of a serial link. The re-sampled signal can be transmitted to another unit that is remote to the unit transmitting the signal. The other unit can include a re-sampling device that restores the re-sampled signal to a digital signal that can be converted to an analog signal for wireless transmission.

Abstract: Logic for spur estimation of a wireless communication packet. Logic may receive an input signal output by a set of analog-to-digital converters and determine means of sequences for each of the analog-to-digital converters. The sequences may be from a preamble of the wireless communication packet. The sequences may comprise a set of short training sequences with an average zero mean received after logic detects a boundary of the sequences. The set of short training sequences may comprise a Golay sequence Ga and a Golay sequence ?Ga. Logic may determine spur estimations for each of the analog-to-digital converters based upon a frequency offset estimation for the wireless communication packet. Logic may remove a mean of the spur estimations from the spur estimations. And logic may remove the spur estimations from the packet.

Abstract: An SoC integrated circuit package is provided in which the analog components of a SerDes for an SoC die in the SoC integrated circuit package are segregated into a SerDes interface die in the SoC integrated circuit package.

Abstract: A high resolution timing device is provided. The high resolution timing device includes a first and a second clock delay circuits. The first clock delay circuit receives an input reference clock signal to generate a first multiple frequency output clock signal, divide the first multiple frequency output clock signal to generate a first original frequency output clock signal and perform a clock-delaying process thereon according to the first multiple frequency output clock signal to generate first clock-delayed signals. The second clock delay circuit receives one of the first clock-delayed signals to generate a second multiple frequency output clock signal, divide the second multiple frequency output clock signal to generate a second original frequency output clock signal and perform the clock-delaying process thereon according to the second multiple frequency output clock signal to generate second clock-delayed signals.

Abstract: A synchronization apparatus between an AVN system and a digital clock of a vehicle may include: a clock driving unit configured to transmit a clock information signal; a microcomputer configured to analyze the clock information signal when the clock information signal is received from the clock driving unit, update clock information according to the analysis result, and transmit the updated clock information to an external clock module; and the external clock module configured to display the clock information transmitted from the microcomputer.

Abstract: A packet transmission device includes first and second clocks, a communication unit, and first and second synchronization processing units. The communication unit transmits and receives a synchronization packet to and from an external time source device. The first synchronization processing unit synchronizes the first clock with the external time source device in accordance with time information of the synchronization packet. The second synchronization processing unit synchronizes the second clock with the first clock.

Abstract: A clock generator for generating a clock equivalent to a target clock which is an input clock divided by a non-integer ratio is disclosed. The clock generator comprises a clock divider configured to receive the input clock and divide the input clock with a reconfigurable dividing ratio; and a control circuit controlling operations of the clock divider to divide the input clock by a first dividing ratio to generate a first number of cycles of a first clock in a frame, and divide the input clock by a second dividing ratio to generate a second number of cycles of a second clock in the frame, wherein a difference between a period of the frame and a cumulative time of the first number of cycles of the first clock and the second number of cycles of the second clock is less than a threshold value.

Abstract: Systems and methods are disclosed herein, such as those that operate to control a set of delays associated with one or more data clocks to clock a set of data bits into one or more transmit registers, one or more data strobes to transfer the set of data bits to at least one receive register, and/or a set of memory array timing signals to access a memory array on a die associated with a stacked-die memory vault. Systems and methods herein also include those that perform data eye training operations and/or memory array timing training operations associated with the stacked-die memory vault.

Abstract: Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators.

Abstract: Methods and systems are provided for enabling a base station to listen and receive signals from neighboring base stations over a frequency designated for transmission to mobile devices for the detection of a synchronization failure. Embodiments provided herein enable the base station to cancel out its own transmission signal(s), which overloads the base station's own antenna 816 due to proximity. By cancelling out the base station's own signal, the base station listens and receives synchronization signals from one or more neighboring base stations over the frequency designated for transmission in a wireless communications network. A synchronization signal may be used, by the base station or as relayed to a server, to determine if the base station or the neighboring base station has experienced a synchronization failure.

Abstract: A digitized signal is processed via an interpolator. The interpolator performs timing adjustment on the digitized signal. The error signal is determined based on a desired signal and the time-adjusted digitized signal. A corrective phase shift of the digitized signal is determined via a least-mean-squared processing block that uses the error and the derivative of a function used by the interpolator. The corrective phase shift is input to the interpolator to perform the timing adjustment.

Abstract: Method and system for optimally equalizing distortion of an optical data channel carrying coherent optical signals with a given analog bandwidth B. A receiving end with IQ paths receives signals and a balanced detector detects signals in each path. The bandwidth of the detected signals is reduced by a factor of N by filtering the output of each path using an AAF with a cutoff frequency optimized to the analog bandwidth 2B/N of each path, where the AAF has deterministic attributes and introducing Known ISI. The signal is sampled at the AAF output by an ADC, at a sampling rate of 2B/N. The samples of each path are post-processed by a digital processor operating at a data rate of 2B/N, where post-processing represents the compensation of the distortion and the input data stream is reconstructed by optimally decoding the output of the processor using a decoder, which compensates the ISI.

Abstract: An encoder (250) comprises a core encoder (252) for encoding a low frequency component of the audio signal at the signal sampling rate (fs_in) and a spectral band replication-referred to as SBR-encoding unit (153, 254) for determining a plurality of SBR parameters. A plurality of the SBR parameters is determined such that a high frequency component of the audio signal can be approximated based on the low frequency component of the audio signal and the plurality of SBR parameters. A multiplexer (155) is adapted to generate an overall bitstream comprising the core encoded bitstream, the plurality of SBR parameters and an indication of one or more SBR encoder settings applied by the SBR encoder (153, 254); wherein the generated overall bitstream does not indicate that the core encoded bitstream has been determined by encoding the low frequency component at the signal sampling rate (fs_in).

Abstract: A system and methods for resolving integer cycle ambiguity in medium wave carrier radio signals are presented. A satellite signal is received at a receiving location and a measured code phase of the satellite signal is measured. A satellite location estimate of the receiving location is computed based on the measured code phase. Medium wave radio carrier signals from medium wave radio transmitters are received at the receiving location. A number of wavelengths of the medium wave radio carrier signals from the satellite location estimate to each of the medium wave radio transmitters is determined respectively. A carrier phase of each of the medium wave radio carrier signals is measured. An improved position estimate of the receiving location is computed based on the number of wavelengths and the carrier phase of each of the medium wave radio carrier signals, and a location of each of the medium wave radio transmitters.

Abstract: A broadcast/multicast transmission format includes a data portion and a cyclic prefix (CP) coupled to the traffic data portion. A method and system for providing broadcast/multicast transmissions with the application to communication systems that perform broadcast or multicast transmission is also disclosed. The addition of a pilot to the data portion of the transmissions is also disclosed.

Abstract: Aspects of the present disclosure are directed toward receiver devices and methods of using receiver devices. One such method can include converting, using an analog-to-digital converter (ADC), and an analog input signal from power distribution lines that carry power using alternating current (AC) to a digital form. This input digital signal can be an oversampled digital signal, where the digital signal is oversampled relative to downstream processing (e.g., FFT-based processing). A processing circuit(s) can then be used to decimate the input digital signal according to a decimation rate. A reference signal can be generated by the processing circuit that is responsive to the decimation rate. The processing circuit can also be used to detect a change in a phase difference between the AC and reference signal and to modify, in response to detecting a change in the phase difference, the decimation rate to counteract the detected change in the phase difference.

Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a phase interpolator, a finite state machine, and a divisor-controllable frequency divider. The phase detector compares an input data signal with a frequency dividing signal and generates a phase indication signal to indicate a phase difference between the input data signal and the frequency dividing signal. The phase interpolator performs phase interpolation on first and second clock signals received by the phase interpolator, so as to generate a phase interpolation signal. The finite state machine coupled to the phase detector and the phase interpolator generates the control signal based on the phase indication signal and the phase interpolation signal. The divisor-controllable frequency divider coupled to the phase detector and the phase interpolator divides the second frequency of the phase interpolation signal by a divisor so as to generate the frequency dividing signal. A CDR method is also provided.

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Abstract: In an example, an apparatus for CDR includes at least one data register, at least one edge register having an input coupled to an output of the at least one data register, and a phase detector having inputs coupled to the output of the at least one data register and an output of the at least one edge register. The apparatus further includes a frequency accumulator coupled to an output of the phase detector, a dynamic gain circuit coupled to the output of the phase detector, and a phase accumulator and code generator circuit configured to generate codes to control a phase interpolator based on an output of the dynamic gain circuit and an output of the frequency accumulator.

Abstract: Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data (DQ) and data strobe (DQS) signals from system memory during read operations. The memory interface circuitry may include startup calibration circuitry and runtime calibration circuitry. The startup calibration circuitry may be used upon device startup to perform a one-time data de-skew and DQ/DQS centering. The runtime calibration circuitry may include at least two data sampling circuits, a first of which is used in active mode to latch incoming data and a second of which is used in redundant mode to obtain data eye boundary information on a continuous basis. The received DQS signal may be adjusted based on the obtained eye boundary information so that DQS properly positioned within the data eye periodically or on an as-needed basis.

Abstract: For re-timing sampled data, input data samples at an input data rate are stored in a FIFO buffer and output at an output data rate according to an output clock that is locked to the input data rate in dependence on a loop-filtered measure of the fill level of the said buffer. The frequency of the output clock is additionally controlled by an estimate of the input data rate.

Abstract: A phase interpolator circuit that includes an interpolator suitable for generating synthesized clocks through synthesizing two multi-phase clocks; and an interpolation code generator suitable for generating an interpolation code for controlling the interpolator in response to a shift request. The interpolation code generator generates the interpolation code so that a (K+1)-th multi-phase clock is output as the synthesized clock when a phase of the synthesized clock is to be changed from a phase between K-th and (K+1)-th multi-phase clocks to a phase between (K+1)-th and (K+2)-th multi-phase clocks in response to a multi-shift-up request.

Abstract: The problem was that the high-impedance state of the difference between signals DQS and DQSB cannot be prevented from being brought in. With this invention, a first comparator circuit outputs a signal DQSIN representing the difference between DQS and DQSB after the coupling of input terminals to a terminal potential and from before the start timing of a preamble of the two signals. A second comparator circuit compares the level of DQS or DQSB with a reference voltage Vref and outputs a signal ODT_DET representing the result of the comparison. A gate circuit masks the signal DQSIN with a signal EW in a masking state. A control circuit identifies the start timing of the preamble based on ODT_DET, and sets the signal EW to the masking state before the start of the preamble and to an unmasking state from the start timing of the preamble.

Abstract: The invention discloses a wideband receiver and a base station in a communication network. The wideband receiver comprises an Intermediate Frequency (IF) frequency control module, a frequency synthesizer, a mixer and an analog-to-digital converter (ADC). The IF frequency control module comprises an interference detector adapted to detect interference condition on at least one frequency band, and an IF frequency selector adapted to select an IF frequency based on the detected interference condition from the interference detector. The IF frequency is selected to avoid high interference mixed product of the mixer occurring in used channel. The frequency synthesizer generates an oscillator signal of the selected IF frequency, the mixer down converts a RF signal to an IF signal using the oscillator signal of the selected IF frequency, and the ADC converts the IF signal to baseband data.

Abstract: A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.

Abstract: Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.

Abstract: The present invention provides methods, apparatuses and a program relating to fast recovering for network listening schemes in synchronization over air for small cells. The present invention includes tracking, at a first base station, a reference signal of a second base station, determining, whether the reference signal can be tracked, if it is determined that the reference signal can be tracked, adjusting, at the first base station, a system clock of the first base station based on the reference signal of the second base station, and estimating and storing parameters relating to a frequency difference between the system clock of the first base station and a system clock of the second base station, and if it is determined that the reference signal cannot be reliably tracked, adjusting the system clock of the first base station based on the stored parameters.