Abstract: A non-linear distortion compensator includes: a non-linear distortion calculator that calculates non-linear distortion occurred in a received optical signal based on signal information after recovery of a carrier wave in a carrier wave phase recovery which recovers a phase of the carrier wave of the received optical signal; and a non-linear compensator that compensates the non-linear distortion of the received optical signal based on the non-linear distortion obtained by the non-linear distortion calculator.

Abstract: Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code or a crossing PI code in a clock and data recovery (CDR) circuit until one or more preset criteria are satisfied. One example method generally includes determining that a condition has been met; based on the determination, stepping, in a CDR circuit, at least one of a data PI code or a crossing PI code for each cycle of a clock; stopping the stepping based on one or more criteria to generate a predetermined state of the data PI code and the crossing PI code, wherein the predetermined state comprises an offset between the data PI code and the crossing PI code; receiving a data stream; and performing clock and data recovery on the data stream based on the offset between the data PI code and the crossing PI code.

Abstract: A method and system for communicating data between two devices are described herein. The method detects an electrical signal of a first protocol from a first device in a repeater, wherein the first protocol comprises single-ended signaling. The method also determines the speed of the electrical signal. Additionally, the method converts the electrical signal of the first protocol into an electrical signal of a second protocol based on the speed of the electrical signal. The second protocol comprises differential signaling. Furthermore, the method sends the electrical signal of the second protocol to a second device. In addition, the method stops the electrical signal of the second protocol to the second device when the electrical signal of the second protocol indicates an end of data flow.

Abstract: Embodiments are described for a method of continuously measuring the ratio of frequencies between the transmit and receive clock domains of a heterochronous system using an array of digital frequency measurement circuits that provide overlapping frequency and detection interval measurements within single counter periods required for a single frequency measurement circuit to complete a frequency measurement. Embodiments may be used in a predictive synchronizer to provide low latency, continuous frequency measurements for system-on-chip (SOC) devices that employ frequency drift or ramping to reduce power consumption and overheating conditions.

Abstract: A data interface enabling the calibration of input data comprises a first data receiver having a first plurality of input data lines coupled to receive a corresponding first plurality of data bits associated with a data bus, the first data receiver having a first control circuit enabling calibration of the first plurality of input data lines; and a second data receiver having a second plurality of input data lines coupled to receive a corresponding second plurality of data bits associated with the data bus, the second data receiver having a second control circuit enabling calibration of the second plurality of data lines. The first plurality of input data lines of the first data receiver are calibrated in parallel with the second plurality of input data lines of the second data receiver.

Abstract: An operating method of a human interface device includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data stream according to the oversampling signal; calculating a difference between the oversampling number and M times of the accumulated bit number when the accumulated bit number is larger than a predetermined value; and calibrating detected information obtained operating with the oversampling signal according to the correction parameter.

Abstract: Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.

Abstract: An orthogonal frequency division multiplexing (OFDM) signal transmission apparatus which transmits OFDM signals by using a plurality of transmission antennas includes a subcarrier setting device which sets signals for subcarriers so as to use some of the subcarriers of the OFDM signals as pilot subcarriers to transmit pilot signals and use the remaining subcarriers as data subcarriers to transmit data signals, the subcarrier setting device changing polarities of signals for the pilot subcarriers for each transmission antenna.

Abstract: Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.

Abstract: AC-coupled termination and equalization, including transmit equalization and/or receive equalization, are combined to create a high bandwidth channel that requires no special coding and consumes no or negligible DC current.

Abstract: Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

Abstract: A method and system for re-ordering bits in a memory system is disclosed. The memory system includes a system on a chip (SoC) coupled to a plurality of memory chips. Each of the memory chips including a memory array, multipurpose registers (MPRs) coupled to the memory array; and a data bus coupled between the SoC and the memory array. The method and system comprise utilizing the MPRs within each of the plurality of memory chips to determine bit ordering within each byte lane of memory array of the associated memory chip. The method and system further includes providing the determined bit ordering to the SoC.

Abstract: A signal reproduction circuit, includes: a clock reproduction circuit configured to reproduce a reception clock from a reception data signal; a data fetching circuit configured to fetch the reception data signal in response to a variation edge of the reception clock and output the reception data signal as first decision data; and a phase adjustment circuit configured to adjust a phase of the variation edge of the reception clock in response to a plurality of second decision data, the data fetching circuit fetching a plurality of second reception data in a plurality of periods immediately preceding to a period in which the reception data signal is fetched and outputting the plurality of second reception data as the plurality of second decision data.

Abstract: An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.

Abstract: A method for compensating an offset in a receiver is provided. The method includes receiving first data from a first sampler and receiving second data from a second sampler. The method also include determining a first average value from the boundary of the first data over a selected period of time; and sending an offset signal to the first sampler based on the first average value. The method may also include determining a second average value from the boundary of the second data over a selected period of time; and sending an offset signal to the second sampler based on the second average value of the boundary data.

Abstract: A synchronization method and device for transmit and receive symbols of an all-digital receiver. The method comprises the steps of: after receiving a sampling signal sent by a baseband processing chip, the clock signal of which is provided by a second clock source, a digital signal processor (DSP), the clock signal of which is provided by a first clock source, measuring a phase shift between a local sampling symbol and an air interface symbol, and acquiring the phase shift amount; according to the phase shift amount, adjusting a sampling opportunity for the sampling of a digital-analogue/analogue-digital converter; and when the sampling opportunity for the sampling of the digital-analogue/analogue-digital converter has been adjusted, adjusting an interface clock for data transmitting and receiving of the DSP so as to enable the data transmitting and receiving of the DSP to be synchronized with the sampling.

Abstract: System, methods and apparatus are described that facilitate tests and measurements related to multi-wire, multi-phase communications links. Information is transmitted in N-phase polarity encoded symbols and an eye pattern corresponding to the symbols may be generated such that the symbols are aligned with a trigger for each symbol that corresponds to a clock edge used to sample the symbols. The eye pattern may be used to determine sufficiency of setup times in the communication links and other such characteristics defining a communications channel capabilities.

Abstract: This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.

Abstract: The present invention is directed to data communication. More specifically, the present invention provides a mechanism for determining an adjustment delay that minimizes skew error due to poor alignment between edge samples and data samples. The adjustment delay is determined by sampling edge samples and data samples using different test delays at a calibration frequency that is different from the sampling frequency. The test delay associated with the least average position between the data samples and edge samples is selected as the adjustment delay. The adjustment delay is used as a parameter when sampling data at the sampling frequency. There are other embodiments as well.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multi-lane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link.

Abstract: A phase interpolator (PI) is provided to adjust the phase of a clock such that the phase is aligned to an incoming data pattern from a data stream. The data can be captured from a device such as a flip-flop or the like. The present technique uses a PI (digital to phase) and a digital state machine in a feedback loop to set the correct digital code to the PI inputs to achieve an appropriate clock phase. Of course, there can be variations.

Abstract: A device includes process mitigating timing (PMT) circuitry. The PMT circuitry allows for adjustment of a clock signal while compensating for process variation within the PMT circuitry. The PMT circuitry may include process mitigating buffer (PMB) circuitry. The PMB circuitry may utilize replica circuitry and a calibrated resistance to generate a calibrated bias voltage. The calibrated bias voltage may be used to drive component buffer circuits to create a calibrated current response. The calibrated current response may correspond to a selected output impedance for the component buffer circuits. The select output impedance may be used in concert with a variable capacitance to adjust a clock signal in manner that is independent of the process variation within the PMT circuitry.

Abstract: A delay line has at least four delay stages coupled together in a series, two multiplexers, and a phase interpolator. The first multiplexer has a first input coupled to an output of the first delay stage, and a second input coupled to an output of the third delay stage. Similarly, the second multiplexer has a first input coupled to an output of the second delay stage, and a second input coupled to an output of the fourth delay stage. The phase interpolator is coupled to outputs of the first and second multiplexers, and has an output.

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract: A dynamic and flexible architecture and methods for demodulation of high data-rate streams with high symbol-rates, such as in satellite communications systems or computer network communications systems, is provided. A data stream of a data transmission is received, the data stream corresponding to a plurality of data symbols. A plurality of data samples corresponding to each of the data symbols is generated. Further, one or more representative data samples, corresponding each of the data symbols, are generated based at least in part on timing control signals and the generated data samples for the respective data symbol. The generated data samples corresponding to each of the data symbols other than the representative data samples are dropped. The timing control signals are then adjusted based at least in part on the generated representative data samples.

Abstract: Methods and apparatus are provided for receiving packets on a channel of an Orthogonal Frequency Division Multiplexing (OFDM) system. A time shift value for a packet is estimated using a channel estimation and an FFT size. A synchronization position of the packet on a channel is adjusted using the estimated time shift value, and a filter is applied to the adjusted channel to generate a smoothed channel estimate. Alternatively, a channel with a corrected packet synchronization position is estimated, and a smoothed channel is estimated by applying a filter to the estimated channel. Packets are received on the channel, at a receiver of the OFDM receiving apparatus, in accordance with the estimated smoothed channel.

Abstract: A wireless communication device according to the present invention includes a standard signal holding unit for holding standard signals, a correlation value calculation unit for performing a correlation operation between a received signal and the standard signals, and a reference signal selection unit for determining a reference signal from among the standard signals on the basis of a correlation operation result obtained by the correlation value calculation unit. When a correlation value peak which provides a maximum value is not detected among a correlation values obtained by the correlation operation between the received signal and the standard signals, the reference signal selection unit repeats a predetermined number of times, a process of performing a correlation operation between a new standard signal which is generated so that a head of a data part is located at some midpoint in a predetermined symbol interval and the received signal.

Abstract: A digital signal processor (DSP) may receive samples of a signal from an analog-to-digital converter (ADC); convert the samples from a time domain to a frequency domain; determine a clock phase error of the samples while in the frequency domain; and provide a voltage corresponding to the clock phase error. The voltage may be provided to reduce timing errors associated with the samples.

Abstract: An eye diagram measuring circuit includes a reference signal generator, a clock data recovery circuit, a test signal generator, and a boundary determining unit. The reference signal generator generates a reference signal. The clock data recovery circuit generates a clock signal according to the reference signal. The test signal generator generates a first sampling signal according to the clock signal. The test signal generator discriminates logic levels of plural bits of the input signal according to the first sampling signal and a slicing voltage, thereby generating a test signal. The boundary determining unit generates a boundary of an eye diagram according to a relationship between the test signal and the reference signal. The test signal generator changes a phase of the first sampling signal and a magnitude of the slicing voltage according to plural conditions provided by the boundary determining unit.

Abstract: A data converting method includes counting for each bit pattern among bit patterns that a data segment of a specific number of bits can assume, the number of data segments that have the bit pattern, where the data segments are segments of write_data written to a storage medium storing two types of bit values among which a first value has a higher error occurrence rate than a second value; correlating a bit pattern selected as a conversion source pattern, from among the bit patterns in descending order of count results, with a bit pattern selected as a conversion target pattern, from among the bit patterns in descending order of quantities of the second value respectively included in the bit patterns; and converting for each conversion source bit pattern, data segments having the conversion source bit pattern, into converted data segments having the correlated conversion target bit pattern.

Abstract: A method of receiving data including receiving, on one or more carrier waveforms, signals representing a plurality of data elements of an original data frame wherein each of the data elements are represented by cyclically time shifted and cyclically frequency shifted versions of a known set of waveforms. The method further includes generating, based upon the signals, a received data frame and generating an equalized data frame by performing an equalization operation using elements of the received data frame, the equalization operation correcting for distortion introduced into the signals during propagation of the carrier waveforms through a channel.

Abstract: A CDR circuit includes an AD converter that converts an analog input signal to a digital output signal according to an operation clock signal; a phase adjuster that subtracts a first phase from a first clock signal having a first frequency equal to a frequency of the input signal to output a second clock signal having a second frequency as the operation clock signal to the AD converter; a phase detector that detects a second phase in the output signal of the AD converter; a filter that obtains a third phase by performing a filtering process based on the first phase, the second phase, and the third phase output from the filter; an adder that adds the first phase and the third phase to obtain a fourth phase; and a decision circuit that obtains recovered data from the output signal of the AD converter using the fourth phase.

Abstract: A reception circuit has: a phase detector that detects a phase code based on a phase of data in relation to a first clock signal; a calibration signal generator that, in a calibration mode, adjusts a frequency of the first clock signal or the data so that the phase code detected by the phase detector changes; a calibrator that, in the calibration mode, stores a difference between the phase code and an ideal value of the detected phase, and that, in a normal operation mode, outputs the ideal value in correspondence with the phase code detected by the phase detector; and a phase adjustor that, in the normal operation mode, adjusts a phase of the first clock signal based on the phase code detected by the phase detector and the ideal value, and that outputs to the phase detector.

Abstract: An apparatus for reducing spurs is described. The apparatus includes a coarse digital to analog converter (DAC). The apparatus also includes a correction term generator. The correction term generator generates a correction term. The correction term has an amplitude within a dynamic range of the coarse digital to analog converter (DAC). The apparatus also includes a baseband filter. The correction term is selected such that the baseband filter reduces the correction term to an amplitude approximating that of a spur in a transmit signal. The correction term is used to reduce a spur.

Abstract: One embodiment sets forth a technique for deterministic synchronization of signals that are transmitted between different clock domains. The relative phase difference between a source clock domain and a destination clock domain is characterized and the source clock and/or the destination clock are delayed as needed to generate phase-shifted versions of the source and destination clocks for use during a deterministic operating mode. The phase-shifted versions of the source and destination clocks are non-overlapping, meaning that the rising edge of the destination clock does not occur when the source clock is asserted. The non-overlapping source and destination clocks are used by a deterministic synchronization unit to ensure that signals being transmitting from the source clock domain to the destination clock domain are not sampled within a metastability window.

Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

Abstract: A method and system are disclosed which determine a frequency offset between a reference clock frequency of a receiver and a transmit clock frequency embedded in a received non-return to zero (NRZ) signal. A polarity of the frequency offset is determined based on a moving direction of a sampling clock edge relative to an edge of a signal eye of the received NRZ signal and a region of the signal eye containing the sampling clock edge. A magnitude of the frequency offset is determined based on a time taken by the sampling clock edge to sweep the signal eye.

Abstract: A method for providing a bit string on at least two electronic devices is provided. A sensor input is received by sensors in the electronic devices and recorded by the electronic devices. Data points are generated from the sensor input by each of the electronic devices. Each device samples its generated data points at a sampling frequency. A bit string is then generated by each device based on the sampled data points. The bit string of each device substantially matches one another, thereby allowing the electronic devices to share a secret, which may be used to allow secure communications between the at least two electronic devices.

Abstract: A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes monitoring movements of a valid data eye associated with a memory device of a plurality of memory devices of a memory system at a computing system. The monitoring may include initiating write commands during one or more refresh periods associated with the valid data eye. The method may include determining drifting in the movement of the data eye, and correcting the drifting based on adjusting one or more existing phase interpolator values associated with the movements of the data eye.

Abstract: Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock operating at a second frequency. A master phase-locked loop (PLL) comprising a first gated voltage controlled oscillator (GVCO) is configured to align the phases of reference clock and the input data, and provide phase error information and a recovered clock. A second GVCO is controlled by the recovered clock to sample the input data. A frequency alignment loop comprising a feedback path from the second GVCO to the master PLL is configured to use the phase error information to correct a frequency offset between the first frequency and the second frequency.

Abstract: A method to facilitate late entry of a late entrant node into an ad-hoc radio network involves accessing from a memory at the late entrant node an initial frequency hopping sequence for the ad-hoc radio network. The late entrant node uses at least the initial frequency hopping sequence to determine a first frequency to monitor during a communication epoch corresponding to one of the frequency hops. The late entrant node thereafter monitors the first frequency to detect the presence of a beacon signal transmitted by a participating node of the network. Subsequently, the late entrant node determines a second frequency included in the current hopping sequence of the network based on information contained in the beacon signal.

Abstract: Embodiments of the invention relate to methods and circuits for controlling the sampling phase of a signal that is to be regenerated by sampling, particularly a serial communication signal, having method steps or means for oversampling the signal in order to ascertain samples of the signal during predetermined sampling phases, for determining differential errors between the samples during different instances of the predetermined sampling phases, for determining a differential error rate between the samples to at least one first and at least one second sampling phase on the basis of the ascertained differential errors, and for comparing at least two differential error rates based on at least two different sampling phase pairs in order to ascertain a decision concerning which of the predetermined sampling phases can be selected as a reference sampling phase for correctly regenerating the signal.

Abstract: Methods and apparatus disclosed herein operate, for example, to derive a non-ideal received signal from an ideal signal, to compute, from the non-ideal received signal, at least one probability density function of amplitude and time values representing deviations from the ideal signal, to derive at least one amplitude noise component and at least one timing jitter component from the at least one probability density function, and to generate a non-ideal waveform by applying the at least one amplitude noise component and the at least one timing jitter component to an ideal waveform.

Abstract: A system for determining a unit time of a serial transmission protocol, wherein the serial transmission protocol defines a unit time (UT) by transmitting a calibration pulse having a predetermined length of N*UT and wherein a receiver is operated by system clock, includes: a clock divider for dividing the system dock by M, wherein M evenly divides N, and a detector for sampling a received data nibble length by using a dithered sampling clock.

Abstract: Clock recovery for a data receiving unit is disclosed. Clock recovery can include obtaining an early/late signal from an incoming data stream, wherein the early/late signal indicates if a set of one or more data samples of the incoming data stream tends to be earlier or later than an edge of a phase-rotated clock signal provided depending on a phase offset value. Clock recovery can include updating a phase rotation counter value in response to the early/late signal. Clock recovery can include determining the phase offset value depending on a rounded phase rotation counter value. The phase offset value can be further determined by selecting one of a set of options including maintaining, increasing, or decreasing the rounded phase rotation counter value, wherein the selecting is performed depending on the early/late signal and depending on the phase rotation counter value.

Abstract: A method is provided for suppressing interferences in a sampling process. The method includes the method step of sampling an analog useful signal at a sampling frequency f as well as determining whether an interference amplitude is present. In the presence of an interference amplitude, a stochastic shift of the chronologically equidistant sampling points in time, which are determined by the sampling frequency f, is carried out within a range [=?t; +?t] (21) around the equidistant sampling points in time, ?t being the maximum shift. Subsequently, a resampling of the analog useful signal is carried out. It is redetermined whether an interference amplitude is present. In the case of the continuous presence of an interference amplitude, a change in the absolute value of the maximum shift |?t| is carried out and the process is restarted with the method step of stochastically shifting the sampling points in time.

Abstract: In a data recovery circuit, a sampling circuit is configured to sample data using a plurality of sampling clock signals having different phases relative to one another and to output a plurality of sampled data. A recovery data generation circuit is configured to perform a logic operation on the plurality of sampled data and to generate a plurality of intermediate recovery data according to a result of the logic operation. A recovery circuit is configured to check the plurality of intermediate recovery data for existence of an error and to output intermediate recovery data that is error-free, among the plurality of intermediate recovery data, as recovery data.

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract: A transceiver with non-deterministic delay characteristics is analyzed and adjusted to provide a transceiver with deterministic delay characteristics. The transceiver may be implemented with a variety of device types to support high bandwidth operation over a wide range of frequencies. Deterministic behavior allows use of the transceiver in source synchronous interfaces. The transceiver may also be dynamically analyzed and adjusted during operation as operation frequency changes.

Abstract: A receiver includes a fixed delay unit configured to delay a first clock signal received from a clock channel by a predetermined time and output a second clock signal; a first delay unit configured to delay the first clock signal in response to a first control signal; a first data sampler configured to sample a data signal received from a data channel in response to an output signal of the first delay unit and output a first data signal; a second delay unit configured to delay the first data signal in response to a second control signal and output a second data signal; a second data sampler configured to sample the second data signal in response to the second clock signal; and a delay controller configured to output the first control signal and the second control signal.