Abstract: Embodiments include systems and methods for applying post-cursor locking point adjustment to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). In one embodiment, a training routine is used to determine an optimal post-cursor target level. Increasing or decreasing the post-cursor target level can cause the CDR clocking to shift right or left, which can be seen as a shift of the channel impulse response with respect to the CDR sampling locations. In some implementations, the post-cursor can be locked to the determined target level. In other implementations, the determined target level can be compared to a fully-adapted post-cursor to tune adaptations performed by transmitter and/or receiver equalizers.

Abstract: A method and apparatus for detecting an envelope are provided. The method and apparatus may detect an envelope of a modulating signal based on a low calculation complexity and a simple circuit configuration, by detecting an envelope for a plurality of sampling signals with equal time intervals.

Abstract: One aspect provides an optical communication system. The system includes an optical-to-digital converter, a frequency estimator and a symbol synchronizer. The optical-to-digital converter is configured to receive an optical OFDM bit stream including an OFDM symbol bearing payload data and a symbol header preceding the OFDM payload data. The frequency estimator is configured to determine a carrier frequency offset of the payload data from the symbol header. The symbol synchronizer is configured to determine a starting location of the payload data within the bit stream by cross-correlating a synchronization pattern within the symbol header with a model synchronization pattern stored by the symbol synchronizer.

Abstract: A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock generator by counting, in which the system clock generator is deactivated in a sleep mode, in which an output clock signal of a sleep clock generator is blanked as a function of an output signal of a modulo divider in the sleep mode, and the system time is determined by counting, wherein an output frequency of the output clock signal of the sleep clock generator is a non-integer multiple of a symbol frequency, in which the modulo divider divides the output clock signal of the sleep clock generator by a division factor, and in which the division factor of the modulo divider is produced by changing between at least two integer divisor values.

Abstract: There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with conventional receivers lowers power consumption. Quality metrics in receiving the data (e.g. packet error rate, etc) are not adversely affected by setting a programmable phase shift in the sampling frequency. The programmable shift can be selected through a calibration process using a known sequence of symbols, such as the short training field in 802.11 standards.

Abstract: A clock data recovery circuit includes a binary phase detector configured to receive an incoming data signal and a recovered clock, and output a phase offset signal and recovered data; a digital loop control circuit configured to receive the phase offset signal and output a control signal; and a digital frequency generator configured to receive the control signal and output the recovered clock. A method of clock recovery includes generating a digital phase offset signal from incoming data and feedback clock signals; generating a clock frequency control signal from the phase offset signal; generating a recovered clock in response to the control signal; slowing down the recovered clock when the digital phase offset signal has a first binary state; speeding up the recovered clock when the digital phase offset signal has a second binary state; and holding the recovered clock when the digital phase offset signal has a third binary state.

Abstract: This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.

Abstract: Embodiments include systems and methods for calibrating effective clock path mismatches in a receiver circuit. For example, a serializer/deserializer (SERDES) circuit includes a data slicer that generates data sampler decisions by sampling an input signal according to a clocking signal, and an error slicer that generates error slicer samples by sampling the input signal according to the clocking signal. Each of the data slicer and error slicer has an associated clock path delay, and the delays are typically different (e.g., due to manufacturing differences). A calibrator performs iteratively shifted sampling and comparing of the data sampler decisions and the error slicer samples over a plurality of clocking locations to determine an effective clock path mismatch. The calibrator can then determine and apply a clocking offset to the data slicer and/or the error slicer to effectively shift data and error sampling, thereby compensating for the effective clock path mismatch.

Abstract: A method for a first electronic device processing data based on information from a second electronic device may comprise: receiving a first signal from the second electronic device; extracting a first clock based on the first signal; adjusting an oscillator based on the first clock so as to generate a second clock; and selecting one from the first and second clocks. In an embodiment of the present invention, the first electronic device may be configured to be hot plugged into the second electronic device. The method may further comprise processing a data stream from the second electronic device based on said selecting said one from the first and second clocks. The method may further comprise transmitting a data stream to the second electronic device based on said selecting said one from the first and second clocks.

Abstract: A transmission protocol decoding method, device, and a transport protocol decoder chip are provided for generating an oscillation signal; detecting a frame start signal, and outputting a sampling control signal when the frame start signal is detected; counting an oscillation period of the oscillation signal within a time period of low level bits of a frame start byte to obtain a count value after receiving the control signal, and then processing a division operation to the count value to output a quotient and a remainder; determining a sampling period according to the quotient and the remainder to generate a sampling pulse, and then decoding a data byte of a transmission data according to the sampling pulse.

Abstract: A reception circuit includes: an equalizer; a comparator to compare an output signal of the equalizer with first, second, and third thresholds at a first-timing to output first, second, and third comparison-results, respectively; a selector to select any one of the first and second comparison-results based on a determination-result at a timing before the first-timing, and update the determination-result; a detector to detect a phase information based on the first or second comparison-result not selected; a shifter to adjust a sampling clock phase based on the phase information detected; and a controller to set a third threshold based on the first and second thresholds by either adjusting the first and second thresholds based on the output signal amplitude or adding/subtracting a first value to/from the output signal, detect an equalization-result based on the third comparison-result by the set third threshold, and adjust an equalization coefficient based on the detected equalization-result.

Abstract: Several different embodiments of a massively scalable object storage system are described. The object storage system is particularly useful for storage in a cloud computing installation whereby shared servers provide resources, software, and data to computers and other devices on demand. In several embodiments, the object storage system includes a ring implementation used to associate object storage commands with particular physical servers such that certain guarantees of consistency, availability, and performance can be met. In other embodiments, the object storage system includes a synchronization protocol used to order operations across a distributed system. In a third set of embodiments, the object storage system includes a metadata management system. In a fourth set of embodiments, the object storage system uses a structured information synchronization system. Features from each set of embodiments can be used to improve the performance and scalability of a cloud computing object storage system.

Abstract: The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal.

Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

Abstract: A method and apparatus for timing optimization are disclosed, which rely on information gathered from a timing detection circuit to find the optimal sampling point of a data recovery system. In an implementation, a timing shift is optimized based on Gardner detector data. In an example, a Gardner detector, or an early and late extraction portion thereof, is added to the data path, and the data path clock is shifted so that it is centered on the data transition mean. In an implementation, the sampling point of the data path is optimized for better horizontal eye opening using a Gardner detector's output for centering the average crossing point of different paths. In an example embodiment, an apparatus is provided with a second clock recovery that is not completely independent of a first clock recovery.

Abstract: A multichannel radio receiver may include a radio frequency (RF) subsystem and a digital subsystem. The RF subsystem may be configured to provide analog information associated with a radio band to an analog to digital converter (ADC). The ADC samples the analog input and sends digital output to the digital subsystem. The digital subsystem may be configured with one or more channelizers and one or more decoders. A channelizer within the digital subsystem may filter and re-sample the digital output to result in a channel plan having a desired bandwidth and a desired sample rate. The sample rate may be selected for compatibility with a decoder. The decoder may have design specifications based in part on a modulation scheme to be decoded. The design specifications may indicate the desired sample rate to be provided by the channelizer.

Abstract: There is provided a receiving device includes: a plurality of interpolation unit circuits, each interpolation unit circuit configured to perform interpolation processing of a sampling value obtained by asynchronously sampling input data, based on an interpolation ratio, so that sampling data synchronous with the input data and continuous in time is generated, wherein one of the interpolation unit circuits is provided in parallel with another of the interpolation unit circuits for a channel previous to a channel in which switching of the interpolation ratio is performed.

Abstract: A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each output signal. The number of clock cycles of the longest half-wave period is compared to multiple values representing frequency limits of various frequency bands to determine which frequency band to classify jitter the gain-controlled signal. The determined frequency band is used to select from a look-up table a set of gain values for use in the CDR.

Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Abstract: System, methods and apparatus are described that facilitate tests and measurements related to multi-wire, multi-phase communications links. Information is transmitted in N-phase polarity encoded symbols and an eye pattern corresponding to the symbols may be generated such that the symbols are aligned with a trigger for each symbol that corresponds to a clock edge used to sample the symbols. The eye pattern may be used to determine sufficiency of setup times in the communication links and other such characteristics defining a communications channel capabilities.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively.

Abstract: HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital communications protocol, the audio quality can be impaired by analog signal impairments and distortions even if there are no digital decoding errors. In particular, the very process by which the audio is converted from Digital (HDMI) to human audible “Analog Audio” can be prone to errors. This occurs when the Digital to Analog Converter (DAC) clock, which is derived from the HDMI TMDS clock or HDMI source, is “distorted” due to its jitter, resulting in erroneous sampling or outputting of vital audio samples, thereby reducing the audio quality of the experience. The present invention reduces the jitter on the TMDS clock, and hence the audio DAC clock, resulting in lower audio distortion.

Abstract: A method in a QAM receiver (100) for performing timing recovery. The QAM receiver (100) is configured to receive a sequence of symbols. Each symbol is represented by a respective IQ pair comprising a respective inphase component I and a respective quadrature component Q. The QAM receiver (100) samples the respective I component and the respective Q component with a relative timing offset between the sampling of the respective I component and the respective Q component. The QAM receiver (100) establishes a first value associated to a quality of the I component samples, and a second value associated to a quality of the Q component samples, and compares the first value and second value to determine if the sampling timing should be advanced or delayed to improve the sample quality. The QAM receiver (100) adjusts subsequent sampling by advancing or delaying a sampling timing based on the comparison.

Abstract: A signal receiver may comprise circuitry for applying multi-level sampling to an input signal, using a plurality of sampling rates that comprises at least two different sampling rates, and circuitry for processing one or more outputs of the multi-level sampling. The processing may comprises sampling at a sampling rate that is different than each of the plurality of sampling rates used during the multi-level sampling and applying analog-to-digital conversion. At least one of the sampling rates used during the multi-level sampling and/or the sampling rate used during the processing may be set based on configuring of one or more clock signals used during the multi-level sampling and/or during the processing. At least one of the one or more clock signals may be configured based on reduction of frequency of a corresponding base clock signal.

Abstract: An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a second filter configured to receive a signal in a Q-signal path of the receiver. The ADC further includes a quantizer alternatingly in connection with the first and second filters, and at least one DAC alternatingly in connection with the first and second filters. Switches in the ADC are configured to alternate connection between an input of the quantizer and outputs of the first and second filters, and are also configured to alternate connection between an output of the at least one DAC and inputs of the first and second filters.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract: Systems, methods, and other embodiments associated with preamble detection based on repeated preamble codes are described. According to one embodiment, an apparatus is provided that wirelessly receives a signal and calculates a differential output corresponding to a multiplication of the signal and a delayed version of the signal. A cross correlation is performed between the differential output and a known preamble pattern to produce a cross correlation output. One or more peaks are detected in the cross correlation. The detected peaks are used in subsequent processing to detect the known preamble pattern in the wirelessly received signal.

Abstract: This disclosure includes a point-to-point two-lineserial interface (TSI) suitable for use in a wireless communications device as well as in other applications. The TSI may employ a protocol providing multiple frame formats to achieve delivery of one type of message with a reduced latency and other messages at increased latencies. Further, although the master initiates reads, the slave circuit may signal the master in real time over the TSI.

Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.

Abstract: A signal processing circuit includes: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with a clock signal, wherein each of the plurality of synchronization circuits samples a sample signal from one of the plurality of taps in different phases and outputs a plurality of output signals.

Abstract: In a receiver circuit which can correct a deviation of phase between an input signal and a clock, a sampler detects an amplitude level of the input signal at timing indicated by the clock, a first comparison circuit compares a first and a second amplitude level detected by the sampler at first and second timings, respectively, with a determined threshold, an interpolation circuit calculates an intermediate level that approximates to an amplitude level of the input signal corresponding to an intermediate point between the first and second timings by an interpolation process based on the first and second amplitude levels, a second comparison circuit compares the intermediate level with the determined threshold, and a phase deviation detection circuit detects the deviation of phase between the clock and the input signal on the basis of comparison results obtained by the first and second comparison circuits.

Abstract: A transmission apparatus includes a plurality of orthogonal frequency division multiplexing (OFDM) modulation signal generators, which generate a first OFDM modulation signal and a second OFDM modulation signal. The transmission apparatus also includes a transmitter that transmits the first OFDM modulation signal from a first antenna and the second OFDM modulation signal from a second antenna, in an identical frequency band.

Abstract: A data reception apparatus obtains an integrated number of bits by integrating the numbers of bits of a bit string, obtains an integrated number of samples by integrating the number of samples obtained by oversampling each bit, obtains an approximated line that indicates correspondence between the integrated number of bits and the integrated number of samples, determines, based on the approximated line, a bit length of a bit string corresponding to a segment in which identical values continue in oversampling data after the integrated number of samples. Even when a receive-side clock source has a degree of clock frequency error against a transmit-side clock source, how many samples one bit of the bit string corresponds to is obtained with an accuracy higher than a period of oversampling (inverse of the number of samples).

Abstract: An operating method of a human interface device includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data stream according to the oversampling signal; calculating a difference between the oversampling number and M times of the accumulated bit number when the accumulated bit number is larger than a predetermined value; and calibrating detected information obtained operating with the oversampling signal according to the correction parameter.

Abstract: Symbol sampling in a high time delay spread interference environment includes acquiring (602) a time varying baseband waveform. The waveform has a signal amplitude that varies between one of a plurality of symbol states. The waveform is sampled (603) at a rate of m times the symbol rate. During an evaluation time, an error value is calculated (604, 606) for each of m data sample positions. Each of the error values comprises an average distance between the measured value of the waveform as indicated by the data sample and a closest known symbol value. The error values are used to create an error surface. Thereafter, the error surface is modeled as a quadratic and an optimal sample time is determined (608, 610, 612) based on finding the time location where the quadratic surface is minimum. A sinc interpolator is then used to resample the data.

Abstract: A method for a receiver to estimate phase of a carrier wave, including receiving a carrier wave carrying pilot symbols and data symbols extending between the pilot symbols, determining phase of the carrier wave at received pilot symbols, and interpolating the phase of the carrier wave at points between pilot symbols based, at least in part, on an estimated phase of demodulated data symbols. Apparatus for estimate phase of a carrier wave, including a unit for determining phase of the carrier wave at received pilot symbols, and a unit for interpolating the phase of the carrier wave at points between pilot symbols based, at least in part, on an estimated phase of demodulated data symbols. Related apparatus and methods are also described.

Abstract: The methods and apparatus disclosed herein provide an operative system for increasing the resolution of serial DRUs based on interleaved free running oversamplers. In particular, this system uses incoming data to measure and to compensate the skew between two or more free running oversamplers (e.g., SerDes), without the need for any hardware design requirement relating to the precision of the relative skew of the oversamplers.

Abstract: A data signal delay system may include a delay unit and a phase interpolation unit. The delay unit may include multiple delay elements that each have an element delay. The delay unit may be configured to generate multiple delay signals by delaying a data signal using the delay elements such that each of the delay signals has a different delay. The phase interpolation unit may be coupled to the delay unit and may include a mixer. The mixer may be configured to mix two of the delay signals based on mixing weights selected for the two delay signals to generate a final delayed data signal that is the data signal delayed by a final delay. The mixing weights may be selected based on the final delay.

Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a relative frequency estimate between a second clock domain and the first clock domain and, based on the phase estimate, a first time during which a signal from the first clock domain is unchanging such that the signal is capable of being safely sampled by the second clock domain is determined to generate a first sampled signal in the second clock domain. Additionally, an updated phase estimate is calculated, and, based on the updated phase estimate, a second time during which the signal from the first clock domain is changing such that the signal is not capable of being safely sampled by the second clock domain is determined. During the second time the first sampled signal in the second clock domain is maintained.

Abstract: The present disclosure provides an auto-determining sampling frequency method. The method is for determining sampling frequency for an input signal of a single wire transmission interface. Each frame of the input signal includes a preamble and binary data presented in a plurality of bits. The method includes utilizing an internal sampling clock to acquire a plurality of period widths of the preamble and the binary data in the input signal and determining range of the sampling frequency according to the detected period widths of the preamble and the binary data.

Abstract: The present invention relates to an information processing apparatus, a method, and a program capable of suppressing deterioration of content quality. An integrated reception buffer time adjustment unit 114 obtains a maximum transmission delay time that is the longest delay time among the transmission delays of data transmission performed by each reception unit 113. The reception buffer time setting unit 208 calculates a reception buffer time using the maximum transmission delay time, a transmission delay time of the data transmission by the reception unit 113, and a prescribed reception buffer time. The reception buffer time setting unit 208 sets various delay times and waiting times such as a variable compression encoding delay time, a redundant encoding block reception waiting time, an ARQ retransmission packet waiting time, and a network jitter handling buffer time from the reception buffer time. The present invention can be applied to an information processing apparatus, for example.

Abstract: A device and method for clock and data recovery are disclosed. For example, an integrated circuit comprises a first branch for recovering a clock signal from an input signal. The first branch includes a phase and frequency detector for detecting a phase and a frequency of the clock signal and a numerically controlled oscillator that is controlled by the phase and the frequency of the clock signal from the phase and frequency detector. The integrated circuit also includes a second branch for recovering a data signal from the input signal. The second branch includes a pre-settable numerically controlled oscillator that is pre-settable with the phase and the frequency of the clock signal from the numerically controlled oscillator. The second branch also includes a sample selector that is controlled by the pre-settable numerically controlled oscillator for recovering the data signal.

Abstract: A digital receiver equalization system has a digitized signal input derived from an analog front-end of a digital receiver and having a relatively wide bandwidth. A synthesis channelizer decomposes the digitized signal input into a plurality of time domain synthesis channels each having a relatively narrow bandwidth. An analysis channelizer recomposes the synthesis channels after digital signal processing is performed on at least a portion of the synthesis channels so as to generate a digitized output signal. A channelizer domain defines digital signal processing between the synthesis channelizer and the analysis channelizer. A least a portion of the channelizer domain digital signal processing is a cascade of multiplier arrays, and at least one of the multiplier arrays has inputs that compensate for channel distortion.

Abstract: Aspects of the disclosure provide a method. The method includes boosting a portion of frequency components of a digital signal that is converted from an analog signal based on a clock signal, generating a decision signal based on the boosted digital signal, generating a timing error signal based on the boosted digital signal and the decision signal, and filtering the timing error signal to generate a voltage signal to control a voltage controlled oscillator to generate the clock signal.

Abstract: Symbol sampling in a high time delay spread interference environment includes acquiring (602) a time varying baseband waveform. The waveform has a signal amplitude that varies between one of a plurality of symbol states. The waveform is sampled (603) at a rate of m times the symbol rate. During an evaluation time, an error value is calculated (604, 606) for each of m data sample positions. Each of the error values comprises an average distance between the measured value of the waveform as indicated by the data sample and a closest known symbol value. The error values are used to create an error surface. Thereafter, the error surface is modeled as a quadratic and an optimal sample time is determined (608, 610, 612) based on finding the time location where the quadratic surface is minimum. A sinc interpolator is then used to resample the data.

Abstract: A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.