Abstract: A system and method for determining a timing error of an incoming signal, in one embodiment, receives the incoming signal into a receiver, and locates a known portion within a time frame of the incoming signal. The known portion is compared with a stored representation of the known portion, and with a stored representation of a derivative of the known portion. The timing error of the incoming signal is determined with respect to the clock signal based on the comparing of the known portion with the stored representations, and a subsequent known portion is located within a subsequent time frame of the incoming signal based on the timing error.

Abstract: A system is provided for processing synchronization signals. A plurality of synchronization signals are received having different periods and different degrees of priority, and are used to generate a regenerated synchronization signal in response to clock pulses. A selector is used for selecting a selected synchronization signal, from among those received synchronization signals having a correct period. The selected synchronization signal is chosen based upon the different degrees of priority. A nonvolatile memory stores memorized synchronization signal and an allowable phase range. An address counter, which receives as an input a controllable initial value, counts the clock pulses to produce a clock count over a period of time, and to cause the nonvolatile memory to output the stored synchronization signal as a read-out synchronization signal and to output the stored allowable phase range as a read-out range, in response to the clock count.

Abstract: A discrete multitone modulation transmission system is described in which frame synchronization is monitored at the receiver by correlating frequency domain complex amplitudes of a synchronizing frame with a stored synchronizing pattern. If the correlation result falls below a threshold, indicating a loss of frame synchronization, a plurality of correlations are performed, in each case using the stored complex amplitudes of the synchronizing frame multiplied by a respective complex value representing a respective complex derotation corresponding to a respective possible time shift of the synchronizing frame. The best correlation result, if it exceeds another threshold, indicates a time shift for restoring frame synchronization, this being possible before the next synchronizing frame is received.

Abstract: The present invention provides, a two-system A/D converter, which provides a digital output signal with a higher conversion precision than is achieved by a single-system A/D converter. Conversely, by using a two-system D/A converter with a lower conversion precision, the present invention provides an analog output signal with a higher conversion precision than is achieved by a single-system D/A converter. Further, a digital signal clock changing unit produces data by performing high sampling of the first digital data trains, and the second digital data is synchronized with a second clock through an interpolation processing based on the timing difference between the first and second clocks. A high-precision A/D and D/A converter apparatus is thus realized by using two pulse code modulation coder/decoders (PCM.CODECs) and one digital signal processor (DSP) in a small, inexpensive structure.

Abstract: A device 11 includes a sync unit 20 to identify and achieve synchronization with the cell boundaries of a 53-byte ATM cell stream. Each cell starts with a 5-byte header in which the 5th byte is a CRC byte. Instead of testing all possible bytes to see whether they are cell boundaries, a CRC circuit 21 computes CRCs for successive 5-byte blocks, under the control of a 5-state header counter 22. If such a block is a header, its CRC is a predetermined value, and a match signal is sent to a logic circuit 23, which starts a 53-state cell counter 24 and stops the header counter 22. A 4-state repeat counter 25 checks that the next 5 blocks checked by the CRC circuit 21 are also headers, as confirmation. Synchronization is achieved within at most 5 cells, because the test period of the testing circuitry (which could be longer than the header length) is coprime with the cell length.

Abstract: Synchronization with a signal derived from code violations in periodic data block preambles, and derived using analog circuits provides for a very low jitter clock. The method involves detecting the amplitude of an analog signal derived from the preamble. The amplitude exceeds a preset value whenever a code violation is detected. The frequency of the preamble may be a fraction or a multiple of the synchronized clock.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. A synchronization unit controls the decoder to skip a subframe if a predetermined decoding time for the subframe is earlier than a current time, and to repeat the subframe if the predetermined decoding time is later than the current time. A typical MPEG audio frame includes 12 subframes, such that skipping or repeating a subframe is 1/12 as noticeable as skipping or repeating an entire frame. A buffer memory stores one or more subframes prior to decoding, such that the subframes can be skipped or repeated by manipulation of a read pointer for the memory.

Abstract: A transmitted data stream in a remote control system is a serial data stream having a synchronization sequence and a data sequence. The data sequence is encoded into a symbol comprised of a series of data bits wherein a 110 may represent a logic 1 and a 011 may represent a logic 0. A self adaptive filter adjusts its gain and offset to determine the duration of one bit. Providing a serial code format wherein the synchronization sequence has a smiller duty cycle as the duty cycle of a symbol aids the self adaptive filter to set its threshold switching level accurately and quickly, thus aiding the receiver to decode the transmitted data stream.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: Modems at ends of a transmission line are synchronized with each other by a training procedure which initiates each of a plurality of communication sessions occurring while a connection between the modems is established. The initial communication session begins with a long training sequence. Ensuing communication sessions utilize a time-saving short training sequence which includes the following. A coarse timing algorithm establishes synchronization on a symbol boundary from two alternating elements transmitted in accordance with a standard and of which a plurality of amplitude samples are taken. A fine timing algorithm then quickly finds the peak point of the symbol so that the sampling instance can be adjusted accordingly. This is accomplished by identifying, which sample of an element represents the maximum amplitude between the elements. A comparison is made between the identified sample and its preceding one for that element, and the identified sample and its succeeding one for that element.

Abstract: A quad 16 QAM transmission and reception methodology wherein a time domain pilot reference is advantageously associated therewith. There may be one or more such pilot references for each packet of multiple 16 QAM pulses. Depending upon the embodiment, each 16 QAM pulse can include a time domain pilot reference, or an estimated pilot reference for that pulse can be determined either by reference to pilot references in other pulses sharing the same packet, or by reference to pilot references for other previously received 16 QAM pulses corresponding to that same pulse.

Abstract: A timing recovery apparatus for asynchronous residual time stamping is disclosed. The timing recovery apparatus is placed at the timing domain boundaries for extending the use of synchronous residual time stamping into a new timing domain and for calculating the value indicative of the number of complete source network clock cycles in a predetermined time period which is loaded into a counter. When the counter reaches a predetermined value, a latch connected to a further counter contains a new residual time stamp value.

Abstract: A digital receiver includes a tuner and a demodulator that obtains the baseband signal carried in a received analog signal. A first sampler operates at a preselected fixed sampling rate asynchronous with the baseband component to produce a first sampler output. A controllable digital filter resamples the first sampler output to produce a filter output with a selectable resampling rate. The resampled output is time-position locked to the baseband signal epochs. The second sampling is processed to ascertain the symbol bit stream of the baseband signal. The controllable filter sampling rate is automatically varied to correspond to the symbol rate of the baseband signal, so that the sampling rate of the first sampler need not change. Initial signal acquisition is achieved by operating the receiver as a frequency spectrum analyzer. A single signal-carrying band is identified and demodulated, and a menu carried on a transport layer is read.

Abstract: A duplex voice communication radio transmitter-receiver according to the present invention is provided with a low-pass filter arranged before a time compressing device in a transmitter section for cutting off a higher frequency portion of the band of a voice signal thus to decreasing the maximum modulation frequency of the same to less than a half so that it can be operated with the use of an assigned, single frequency transmission radio wave of which frequency band is legally limited, improved in the utilization of frequencies, minimized in the delay of communication signals, and enhanced in the articulation and intelligibility of a reproduced voice sound.

Abstract: A cascaded synchronized system includes a nonlinear transmitter, a nonlinear cascaded receiver, a phase-detector/controller coupled to the receiver, and a signal generator also coupled to the receiver. The transmitter is responsive to an externally generated transmitter forcing signal for producing and transmitting a chaotic communications signal containing phase information. The cascaded receiver is responsive to a receiver forcing signal and to the chaotic communications signal for producing a chaotic receiver output signal containing phase information. The phase-detector/controller is responsive to the chaotic communications signal and to the receiver output signal for producing a correction signal. The signal generator is responsive to the correction signal for producing the receiver forcing signal in phase with and having the same frequency as the transmitter forcing signal.

Abstract: When an orthogonal frequency division multiplex (OFDM) modulated signal is demodulated by discrete Fourier transformation (DFT), DFT is performed using a time window of an accurate phase synchronized with the synchronization symbol. Therefore, first, the reproduction clock is divided to generate a basic time window signal. The results of the DFT processing on the OFDM signal are used to detect the phase deviation and the phase of the basic time window signal is adjusted based on that phase deviation. Preferably, the results of DFT are used for synchronization pull-in to generate a stable time window signal. More preferably a DFT circuit for demodulating the OFDM modulated signal and a DFT circuit for generating a time window signal are provided separately.

Abstract: A quasi-synchronous information (clocking, data, control signals) transfer between a master unit A and at least one neighbor unit B offers the advantage that one transfer can occur every cycle where any interface delays are tolerated. When the master unit A sends its internal clock along with data and/or control signals to its neighbor unit B, the last named unit receives this clock and derives any and all locally required clocks from this clock. This keeps unit B exactly at the same frequency as unit A, although a phase shift occurs. Unit B also sends its internal clock along with data and/or control signals to unit A. When the clock signals arrive back at unit A, they will have exactly the same frequency as the internal clock of unit A but also an additional phase shift. Compensation of the overall phase shift will be done by a phase alignment means to which all signals are sent on their way to unit A.

Abstract: A system and method for the transmission and recovery of asynchronous data. For instantaneous synchronization, the receiver is equipped with a high frequency timing base which has a far higher frequency than either the data-generating or transmitting rate. The receiver clock is instantly synchronized upon detection of the first transition of the incoming data packet. Data packet verification can be conducted and data processed with minimal loss of data.

Abstract: A communication control device includes (a) a rate adapting unit for inputting thereto a receive clock for receiving a signal and outputting the receive clock of which waveform is partially deformed; and (b) a receiver for receiving the signal based on the receive clock outputted from the rate adapting unit.

Abstract: An apparatus for generating a control signal including pulses occurring at a first frequency f1 and having an overall mean frequency f2 which is in an exact ratio to the difference between the frequencies of a reference signal N and an offset signal O has a common oscillator 18 operating at the frequency of the reference signal N. The offset signal O is produced from the oscillator 18 by a first channel 24a of a 2-channel direct digital synthesizer (DDS), and the frequency f1 is generated by its second channel 24b. The offset signal O controls the rate at which data is entered into a first-in first-out store (FIFO) 54. The signal from the second channel 24b of the DDS triggers sub-sequences of pulses to produce the required control signal, which modifies the extraction of data from the FIFO 54 occurring at the rate of the reference signal N. Each sub-sequence may include one pulse, no pulse or two pulses.

Abstract: A radio receiver (100) for receiving a radio frequency signal includes a receiver (110) for generating from the received signal a data signal having alternating first and second edges and a clock (135) for generating a clock signal having a clock period. Adjustment circuitry (400, 145) adjusts the clock period only on the first edges of the data signal when it is determined that adjustments of the clock period on the second edges would contradict adjustments of the clock period on the first edges. Conversely, the adjustment circuitry (400, 145) adjusts the clock period on both the first and the second edges of the data signal when it is determined that the adjustments of the clock period on the second edges would not contradict the adjustments of the clock period on the first edges.

Abstract: An improved digital communications system is disclosed in which synchronization information is transmitted with the data. A start pulse, having a duration different than the other pulses in the transmitted digital data signal is used to mark the beginning of the frame of digital data. Preferably, a midpoint pulse is also transmitted with the start pulse to mark the midpoint of the frame to facilitate the generation of a local clock signal. Bit positions within the transmitted signal are sampled by sampling pulses which are generated by digital timers having time intervals keyed to the start and midpoint pulses.