Abstract: Noise-reduced signal values derived from at least a part of the constant frequency interval of a telecommunication signal for adapting a filter to the frequency of the constant frequency interval, and to determine the position of the constant frequency interval on the basic of the filtered output values. Employing this idea, a filter can be adapted to a wide range of possible frequencies, which means that the filtered output values will show marked differences when the constant frequency interval begins and/or ends. These differences can be used to detect the position accurately and reliably.

Abstract: A system and method for information content-independent synchronization with a received signal. A variable of the signal (e.g., average energy or magnitude) which is related to the energy distribution, is measured over a period of time. The signal's information bearing point is found at the point within the information period of the signal with the highest averaged energy. The point may be found, for example, by detecting the sample point with highest average energy, or by correlating multiple sample points to a stored template. Interpolation may be performed to locate an information bearing point that is between sample points. Because the relative energy content of the signal is effectively independent of the specific information content, synchronization with the information bearing point is accomplished without requiring the insertion of any special information content or fixed content patterns into the signal.

Abstract: A spread spectrum receiver uses a comparison of the magnitude of the code correlation amplitudes at equal power at a one chip spacing to the magnitude at a central position there between to determine if multipath interference is present. The lead or lag error from constructive or destructive multipath interference may also be determined. Inaccuracies due to such interference may then be corrected or minimized by, for example, determining the residual code phase error and/or the prompt or accurate code phase delay.

Abstract: A discrete multitone modulation transmission system is described in which frame synchronization is monitored at the receiver by correlating frequency domain complex amplitudes of a synchronizing frame with a stored synchronizing pattern. If the correlation result falls below a threshold, indicating a loss of frame synchronization, a plurality of correlations are performed, in each case using the stored complex amplitudes of the synchronizing frame multiplied by a respective complex value representing a respective complex derotation corresponding to a respective possible time shift of the synchronizing frame. The best correlation result, if it exceeds another threshold, indicates a time shift for restoring frame synchronization, this being possible before the next synchronizing frame is received.

Abstract: A method and apparatus for time-shift extraction in a wideband transmitted signal containing strong narrowband interference or noise. The time-shift extraction is based on the time domain and frequency domain relation of symbol misalignment. The invention uses the sign of the product of a recieved signal sample and a reference symbol in the frequency domain to determine the time-shift. It does not rely on the signal magnitude and is therefore less dependent on the signal gain. It also does not rely on the soft phase values, which have ambiguity for values more than three hundred sixty (360) degrees.

Abstract: The present invention relates to a register for a single chip multi-sublayer PHY. More specifically, the present invention relates to a transceiver module including a single chip multi-layer PHY having one or more shadow registers. The transceiver module includes one or more storage modules adapted to store transceiver module local data. The shadow registers are adapted to facilitate collection of the local data from the storage modules and communicate the collected data to another portion of the transceiver module and/or to the upper lever system using at least one interface communicating with the shadow register.

Abstract: A technique for efficient implementation of pilot signals on a reverse link in a wireless communication system. An access channel is defined for the reverse link such that within each frame, or epoch, a portion is dedicated to sending only pilot symbols. Another portion of the frame is reserved for sending mostly data symbols; however, within this second portion of the frame, additional pilot symbols are interleaved among the data symbols. The pilot symbol or preamble portion of the access channel frame allows for efficient acquisition of the access signal at the base station, while providing a timing reference for determining the effects of multipath fading. In particular, a pilot correlation filter provides a phase estimate from the pilot symbols in the preamble portion, which is then used to decode the data symbols in the payload portion. An access acquisition portion of the receiver uses the phase estimates provided by the pilot correlation filter to process the output of a data symbol correlation filter.

Abstract: In a method of digital data transmission in a wireless communication network in which a controlling communication takes place within a fixed bandwidth of a channel from a master station to all subscribers (downlink) with the help of a fixed signal frame, and the beginning of the fixed signal frame is marked by a special frame synchronization signal detectable by the subscribers, an occupancy of at least one subband by transmission signals and a non-occupancy of at least one complementary subband by transmission signals is used as a frame synchronization signal.

Abstract: According to the present invention a received Direct Sequence Code Division Multi-Access (DS-CDMA) signal is differentially decoded at the chip level. A number of signaling schemes can be used in the invention including (1) an ON/OFF signaling scheme in which a pseudo noise number (PN) code is sent only in response to one data bit value, and no signal is sent in response to the other bit value; (2) a Two Code signaling scheme in which bit values of 1 triggers a first PN code to transmitted, and a bit value of 0 triggers a second PN code to be transmitted; and (3) an M-ary signaling method in which a plurality of data bit patterns respectively, trigger a plurality of PN codes to be transmitted. After differential decoding the received signal is despread using one or more PN codes, that can be vector sums of two or more PN codes.

Abstract: A signal processing circuit having a data sync signal detector and a disk device. Input data read from a magnetic disk is input to a data discriminator. A data discrimination output constituting a code bit output discriminated by the data discriminator is input to a post-coder the output of which is input to a decoder and a (1+D) processing unit. The processed output of the processing unit is input to an error detection/correction unit and separated into bit strings of odd numbered bits and even numbered bits, divided into groups. An error detection/correction output is input to a data sync signal detector, and matched against a sync pattern. When the number of coincident groups is greater than a threshold value, a sync signal is output and upon detection causes the decoder to demodulate the data.

Abstract: A synchronization signal includes a plurality of predetermined synchronization symbols shaped by a predetermined symbol pulse. A receiver (100) receives (202) a signal including the synchronization signal, and a processor (106)determines (204) a first plurality of cross-correlations between the predetermined symbol pulse and the received signal. The processor calculates (206) a plurality of sums of products of the plurality of predetermined synchronization symbols and a predetermined subset of the first plurality of cross-correlations. The plurality of sums are mathematically equivalent to a second plurality of cross-correlations between the synchronization signal and the received signal. The processor locates (208) a peak of the plurality of sums to establish receiver synchronization.

Abstract: A data communication circuit includes a decoder and an alignment buffer. The decoder receives and decodes parallel (N) bit channels into parallel (M+X) bit channels with signaling bits that indicate headers in the parallel (M+X) bit channels. The decoder transfers the parallel (M+X) bit channels to the alignment buffer. The alignment buffer recovers and aligns parallel (M) bit channels using the signaling bits. The alignment buffer generates a clock selection signal using the signaling bits. The alignment buffer transfers the aligned parallel (M) bit channels and the clock selection signal. The alignment buffer can have a length that is a multiple of a frame length for the (M) bit parallel channels.

Abstract: A data sync signal detecting device for detecting a sync signal having sync signal detection errors. The detecting device applies the output data of a most-likelihood decoder to shift register bit cells. The data is sequentially shifted and held in the bit cells of the shift register. The bit cell outputs are separated into odd-numbered and even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with “01001” by a first pattern matching circuit. The even-numbered bit string is matched with “01011” by a second pattern matching circuit. First and second matching results are applied to a coincidence number adder/majority decision circuit. When coincidence occurs, the matching result is “1”, and when non-coincidence occurs, the matching result is “0”.

Abstract: A system and method for effectuating the transfer of data blocks having intervals across a clock boundary between a first clock domain and a second clock domain. A first circuit portion provides the data blocks to a second circuit portion. A synchronizer controller disposed between the first and second clock domains provides at least one dead cycle control signal to the second circuit portion, which is indicative of the location of at least one dead cycle between the first and second clock signals. Control logic associated with the second circuit portion generates data transfer control signals responsive to the at least one dead cycle control signal in order to control the second circuit portion so that the data blocks may be transmitted as contiguous data blocks relative to the at least one dead cycle.

Abstract: Disclosed is a method of generating pilot sequences having double lengths of slots used for frame synchronization in an up or down link of a next generation mobile communication system which adopts W-CDMA mode. Disclosed is a method of generating pilot sequences having double lengths of slots used for frame synchronization and defined by 4l+2(l=1,2,3, . . . ) while providing a mathematical method of generating code sequences of slot length.

Abstract: A method and a system for framing variable-length packets in a data communications system are disclosed. The successive variable-length packets carrying users' data, are formed in a stream of chained packets comprising a header. Two CRC's are computed. One over the data and another one over the header however, including also the data CRC of the immediate previous packet, thus chaining successive packets in a steam of such packets. The invention also assumes that encryption is performed independently over header and corresponding CRC's and, on the other hand, over the data of current packet. The invention allows to better adapt the transportation of multi-media users' data in packets of variable-lengths while securing transport by chaining successive packets, thus preventing that accidental or malicious deletion and insertion of packets occur and remain undetected.

Abstract: A method is described for estimating channel impulse responses of a mobile radio channel with a broad bandwidth by a code division multiplexing method, and with a synchronization channel continuously transmitting sequences to mobile radio receivers. The sequences are provided for synchronization of each mobile radio receiver and are known to each of the mobile radio receivers. The transmitted sequences have pilot symbols for identifying the synchronization channel, and the pilot symbols are transmitted at points that are known to the receivers within a time slot. When searching for and identifying the synchronization channel, the pilot symbols and, possibly, further symbols and sequences which are known in the receivers, are evaluated to estimate the delay times and the complex amplitudes, of the mobile radio channel responses.

Abstract: Apparatus, and an associated method, by which to detect a symbol sequence, such as the preamble portion of a frame. Phase calculations are performed, and values of the phase calculations are at least in part determinative of detection of receipt of the symbol sequence. In one implementation, a manner is provided by which to detect reception of the preamble portion of a frame of data broadcast upon a broadcast control channel defined in a HIPERLAN/2 system.

Abstract: A method of a receiver determining the timing of a signal transmitted in a time-slotted manner, the signal comprising a sequence of information which is repeated at a known interval and has at least a known minimum length. The method performs correlation operations between groups of received slots of information, the groups spaced by the known interval. The groups are moved through the received signal, adding and removing slots, to locate a maximum correlation value sum for the group which should correspond to the timing of the slot. The method also can be used to determine a frequency offset at the receiver and/or an initial phase.

Abstract: A frequency correction process involves the steps of generating a plurality of tone values for a plurality of tone bins, where the plurality of tone bins includes a first set of tone bins assigned to a first frequency range and a second set of tone bins assigned to a second frequency range; performing complex conjugate multiplication between the tone values of the first and the second sets of tone bins; identifying a maximum value from results of the complex conjugate multiplication; and shifting receiver frequency based on a location of the maximum value relative to a predetermined pilot tone location.

Abstract: In a null symbol detection device, at the time of receiving a terrestrial digital broadcast, a null symbol can be stably detected even under a fading environment. A synchronous addition buffer group is provided subsequent to an amplitude detector so as to synchronously add an OFDM signal at a null symbol repetition period. A moving average processing unit performs a moving average operation upon synchronous addition data with the number of samples corresponding to a null symbol to output a moving average value. A transmission mode determining unit detects the minimum value among the moving average values normalized in a correction processing unit and compares levels of the minimum values to determine a reception mode. A null position detector generates a synchronous pulse at a null position.

Abstract: The present application discloses an improved mobile communications architecture, in which each base station broadcasts not only data which has been spread by that station's long code word, but also (intermittently) code identification data which has not been spread. The code identification data is a block code which includes multiple symbols, so that multiple intermittent transmissions are required to complete the transmission of the code identification data. This transmission lets the mobile station shorten the search for the base station's long code word in two ways: the code identification data gives at least some information about the long code itself; and the phase of the block code gives at least some information about the phase of the long code word.

Abstract: This proposal describes an optimized synchronization (SYNCH) symbol sequence to be used in transmission systems, which are currently under standardization. The synchronization symbol is constructed using specially designed OFDM (orthogonal frequency division multiplexing) symbols with an optimized sequence, which is mapped onto the modulated subcarriers. The resulting synchronization symbol consists of several repetitions in the time domain. Using the proposed sequence the resulting synchronization symbol achieves a high timing detection and frequency offset estimation accuracy. Furthermore the burst is optimized to achieve a very low envelope fluctuation (low Peak-to-Average Power Ratio) and a very low dynamic range to reduce complexity on the receiver and to save time and frequency acquisition time in the receiver. The proposed sequence is furthermore optimized with respect to all other synchronization symbols that are used to construct the synchronization and training preambles for the BCCH-DLCHs.

Abstract: A null symbol position detecting method, apparatus, and receiver for quickly and accurately detecting a null symbol from a broadcast signal containing it in any broadcast signal receiving environment. A digital audio broadcast (DAB) signal is received and tuned in and this signal is I/Q-demodulated. The I and Q signal obtained by the I/Q demodulation are delayed by an I-component delay circuit and a Q-component delay circuit respectively by one valid symbol period to form a delay signal Id and a delay signal Qd respectively. Correlation is obtained between the delay signals Id and Qd and the signals I and Q which are not delayed. The peak of this correlation is determined by a peak decision circuit. The level pattern of the peak is detected by a level pattern decision circuit.

Abstract: A method and apparatus to perform a real-time drift correction of a local oscillator in a wireless device such as a cordless telephone, and/or to perform software-based frequency tracking of the local oscillator. With respect to the real-time drift correction, the remote handset periodically wakes from a sleep mode and goes into a normal link verification mode. Once in the link verification mode, the remote handset enters a time division duplexing (TDD) mode and attempts to establish a link with a base unit based on the timing of the TDD data frame. After the remote handset establishes a link with the base unit, the remote handset requests a security word from the base unit. Upon receiving the requested security word, the remote handset determines if the requested security word matches a security word of the remote handset. The remote handset implements a software frequency adjustment of its local oscillator.

Abstract: A scalable slot format defining positions of synchronization symbols, pilot symbols and data symbols for various numbers of sub-channels and various lengths of time in a multi-carrier communication system. An initial pattern (500) and one or more follow-on patterns (600, 700) are defined identifying positions of data symbols, synchronization symbols and pilot symbols for a first number of sub-channels corresponding to a first bandwidth. An extended pattern is constructed from the one or more follow-on patterns. The extension pattern is appended to the initial pattern to form a base pattern (810, 910, 1010). The base pattern (810, 910, 1010) is replicated zero or more times to form an expanded pattern (812, 910, 1015) identifying positions of data symbols, synchronization symbols and pilot symbols for an expanded number of sub-channels corresponding to a second bandwidth.

Abstract: A method and apparatus for data retrieval from a storage media, such as magnetic disk drive. A synchronization detector decodes the synchronization information from either the first or second synchronization mark. A later stage detector then carries out several decoding iterations using the synchronization information from the synchronization detector and data stored in the first and second memories. Loss of the data between the first synchronization mark and the second synchronization mark, if there is a problem with the first synchronization mark, is avoided because the bit stream is stored in the first memory.

Abstract: A timing acquisition algorithm for locating the sync timing position of a sync word embedded in a received signal for achieving synchronization between the received signal and a base station, e.g., a base station receiving the received signal, within a wireless telecommunications system. The timing acquisition algorithm is preferably a set of programmable instructions incorporated within a software package and processed by a processor at the within the wireless telecommunications system, such as at the base station. The timing acquisition algorithm gets rid of the unlikely sync timing position for each branch of an adaptive antenna array in the first step; gets rid of the unlikely sync timing position for all branches in the second step; and uses optimal diversity combining for the remaining timing position and uses the conventional correlation or mean-square-error (MSE) approach on the combined data in the third step to finally locate the timing position of the sync word.

Abstract: A digital phase lock loop (PLL) for maintaining synchronization with the phase of a received data signal including a preamble and an information-containing data frame, by incrementing a state machine through an internal cyclic count, each cycle thereof including a center count tending to coincide with center regions of the successive pulses and an edge count tending to coincide with edges of the successive pulses. The PLL selects a current sample of the signal whenever the internal count reaches the predetermined center count value. The state machine internal count is updated in accordance with a cumulative phase error obtained by summing the phase errors detected over successive edges between each edge and the corresponding center count. The interval over which the cumulative phase error is computed depends upon the number of received edges during the preamble and depends upon elapsed time during the data frame.

Abstract: The invention relates to a digital transmission method, which can be used between two items of computer equipment. This digital transmission mode is characterized in that: the data are transmitted in the form of a series of digital signal frames (8), each frame (8) comprises at least successively, from start to end, frame synchronization signals (10), data signals (12) and control signals (14) for the transmitted data, and the characteristics of the synchronization signals (10) and of the data signals (12) and control signals (14) for the transmitted frames are specific to an item of reference computer equipment and are known to the follower computer equipment.

Abstract: Stereo recovery circuitry for a digital receiver is disclosed that provides increased accuracy and efficiency in recovering stereo signal information from transmitted stereo signals. The stereo decoder includes a digitally controlled oscillator that recovers a pilot tone signal from transmitted stereo signal information. By processing demodulated stereo signals on the digital side and digitally controlling the oscillator, the stereo decoder has increased efficiency and accuracy. In one embodiment, the oscillator may be a phase-locked-loop having a loop filter and an amplitude stabilized tunable resonator. Additional circuitry is disclosed for utilizing the pilot tone signal to recover left and right channel signal information from the demodulated stereo signals.

Abstract: A method and a communication system are in which a first synchronization message identifying a data transmission method with the highest-level error protection that a first device is capable of executing is transmitted from said first device to a second device. In the second device, the data transmission method is detected from the first synchronization message. In case the detected data transmission method is supported by the second device, a second synchronization message is sent to the first device identifying the detected data transmission method. In the first device, the data transmission method is detected from the second synchronization message, and in case the detected data transmission method can be executed by the first device, the devices are synchronized with the data transmission method.

Abstract: Disclosed are a communication method of transmitting and/or receiving both data and a synchronizing signal for data receiving, and electronic equipment for transmitting and/or receiving both data and a synchronizing signal for data receiving. The communication method and the electronic equipment each comprise a data communication section for transmitting and/or receiving both data and a synchronizing signal for data receiving, and a synchronizing signal monitor section for monitoring whether a time width of a predetermined section of a signal waveform of the synchronizing signal satisfies a predetermined reference.

Abstract: A set of formats and protocols is proposed for a satellite communications system. In these formats, a pilot signal (PS) is inserted after every 25 or 29 data symbols. The formats consist of SCPC frames (F) which may contain either data (D) and in-band signalling information (SU), or only signalling information (SU). In either case, the contents of each frame (F) are error-correction coded before transmission with the same coding rate. Each data frame (F) carries the data content of an integral number of input user data frames (M), each of which comprises four subframes. Different symbol transmission rates are used for different input data rates, the symbol transmission rates being selected so that their different synchronizing clock rates can easily be obtained from a common clock. Data bursts may be preceded by a constant power level preamble (P). The formats and protocols satisfy the requirements of a high data rate satellite communications system.

Abstract: A receiver is tuned into a multicarrier signal first by performing fine tuning control in the time domain, and then determining a coarse frequency offset to adjust the subcarrier to which the receiver is tuned. The coarse frequency offset is determined by summing the powers of a predetermined set of subcarriers associated with one frequency offset, repeating this for other frequency offsets, and determining whether the largest sum has a predetermined relationship to the other sums. Discrimination is improved by disregarding the largest of the powers when determining the sum. Preferably, the sums are integrated over multiple symbol periods, and the speed of locking-in is increased by terminating the operation when the predetermined relationship has been reached.

Abstract: In an arrangement where an incoming QPSK signal contains a PRN every N frames, oscillator synchronization is achieved via control signals that are developed from the PRN frame by rotating the vectors derived from demodulated received signal, applying a complex tracking filter to the results, averaging the results, performing phase accumulation, and developing an analog voltage to be applied to a voltage controlled oscillator through D/A conversion.

Abstract: In the present invention, UW gate signal generator generates a UW gate signal for detecting a unique word. Gate circuit masks received signal using UW gate signal. PN detector compares a preset unique word signal set value and the signal output from inverting circuit during the active-high interval of UW gate signal, detects whether or not they are matching, and outputs the result. UW detector compares a preset unique word signal set value and the signal output from gate circuit during the active-high interval of UW gate signal, and outputs UW detection signal. Error detector outputs a detection stop signal for stopping unique word detection based on the signals output from PN detector and UW detector.

Abstract: A circuit which recovers a synchronization code, and a method thereof. Where a synchronization code is not detected from an incoming bitstream, a plurality of synchronization code recovery candidate patterns are compared with an original synchronization pattern, and location data to produce an optimal synchronization pattern is determined and generated on the basis of a result of the comparison. The synchronization code is recovered to a location corresponding to the location data. Alternatively, where a synchronization code is not detected from an incoming bitstream, a plurality of synchronization code recovery candidate patterns are error-corrected, and location data to produce an optimal synchronization pattern is determined and generated on the basis of a result of the error correction. The synchronization code is recovered to a location corresponding to the location data.

Abstract: A signal generator and signal receiver, as well as method of signal generation and transmission, in which selected unstable periodic orbits of a lossy chaotic system are identified and extracted, and portions of the orbits concatenated together to form a resultant signal. The selected orbits are known to the signal detector a priori. The signal detector detects the transmitted signal by correlation of the received signal with the known extracted orbits, also allowing the detector identify information which the generator imposed onto the signal.

Abstract: A chirp waveform is employed in establishing timing synchronization between nodes of a data communication network. In one embodiment, the chirp waveform is combined with a waveform modulated with data to form a synchronization waveform. The receiver of the synchronization waveform determines an alignment of the chirp waveform to a template chirp waveform to synchronize timing between nodes.

Abstract: An integrated circuit has a timing circuit with a power source and a capacitor. The timing circuit outputs an output signal whose time can be adjusted and which has a switching time delayed with respect to a reference time. A control signal output by a drive circuit is connected to the timing circuit for adjustment of the output signal with regard to the switching time. The output signal from the timing circuit is connected to the drive circuit for assessment of the output signal with regard to the switching time. The operation of the timing circuit can thus be adjusted independently of process fluctuations during the production of the integrated circuit.

Abstract: A method to train a radio includes the steps of: in a radio (36), receiving a slot of information (2) containing at least an initial portion (4) containing training information (10), a second portion (5) containing training information (11), which second portion (5) is separated from the initial portion (4), and a concluding portion (6) containing training information (12), which concluding portion (6) is separated from the second portion (5). The method combining one of the initial portion (4) with the concluding portion (6a) of a previous slot of information (1) and the concluding portion (6) with an initial portion (4b) of a subsequent slot of information (3) to provide an at least one combined portion of training information. The method using the at least one combined portion of training information and the second portion of training information to train the radio.

Abstract: Carrier frequency and frames are synchronized in bursty data transmissions over unknown channels that cause inter-symbol interference. The synchronization procedure comprises two stages. The first stage performs a time-domain processing of samples to exploit a periodic signal repetition and to extract the coarse timing, the frequency offset and also to resolve frequency ambiguities. The second stage estimates the fine time offset of a received modulation signal. A coarse estimate of a frame start position of a received sequence of desired data samples may be improved by using the coarse timing estimate to generate frequency-domain received samples. A frequency-domain correlation is then determined between the frequency-domain received samples and noiseless samples. When using a fixed number of training samples, a “sandwich” preamble (“sandamble”) is utilized to achieve greater efficiency than a conventional repetition preamble.

Abstract: A synchronization method for received sign and its apparatus capable of increasing accuracy of detection of a receiving signal, of estimating a frequency and of improving reliability in the synchronization of received signal are provided. A signal intensity detecting section is used to detect some peak values and timing values of signals obtained in a first frame and to store them into a memory. A signal extracting section is used to estimate timing, in a second frame, by obtaining a largest synthesized peak value in both frames from the peak value and timing value supplied by a timing estimating section. In a frame following the second frame, frequency data estimated based on a frequency estimating signal with an estimated timing and frequency data estimated based on a frequency estimating signal corresponding to the estimated timing in the frame following the second frame are synthesized and an estimated frequency error is obtained from the synthesized frequency data.

Abstract: A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the downward shift of the shift clock 70 with the downward shift of the standard clock 34 to output a shift clock 72. The shift clock 72 is supplied to the pulse inserter 54. The phase controller 56 receives the standard clock 34 and generates a phase control signal 74 indicating cycles of the shift clock 72 to which the insert-pulses are inserted among a plurality of cycles of the shift clock 72. The pulse inserter 54 inserts the insert-pulses to the cycles of the shift clock indicated by the phase control signal 74. The phase-lock unit 58 generates a delay clock 82 by delaying the phase of the shift clock 70 oscillated by the ring oscillator 50 with respect to the phase of the standard clock, based on the standard clock and the shift clock 76 including the insert-pulses.

Abstract: In all wireless systems, the first operation that must take place at the receiver is the acquisition of the carrier and timing. OFDM systems are particularly sensitive to carrier offsets since these can introduce inter-carrier interference and loss of signal power. An algorithm, termed modulo-sub-carrier (ModSC), which can estimate the local oscillator offset in a fast and efficient manner has been devised. The carrier offset can be brought to within one half the carrier spacing within 1 to 10 OFDM symbols. By inserting a null in the center carrier, carrier acquisition can be easily accomplished by locating this null in the FFT bins at the receiver. The offset of this null from the designed position indicates the local oscillator offset in units of number of sub-carriers. An additional carrier tracking algorithm is used to estimate the offset within one half the inter-carrier spacing. Together, the ModSC and carrier tracking algorithms completely estimate the local oscillator offset.

Abstract: A method is disclosed to distinguish a first type of control channel from a second type of control channel. The method includes steps of (a) transmitting a carrier of the first type of control channel so as to include a first symbol sequence that results, when demodulated, in a sine wave having a frequency with a first offset from the carrier; (b) transmitting a carrier of the second type of control channel so as to include a second symbol sequence that results, when demodulated, in a sine wave having a frequency with a second offset from the carrier; and (c) demodulating a received carrier and detecting whether the carrier includes the first type of control channel of the second type of control channel. In the preferred embodiment of this invention the first symbol sequence is an all zeroes sequence, and the second type of symbol sequence is an alternating ones and zeroes sequence, which results in the first offset being a positive offset, and the second offset being a negative offset.

Abstract: A method and related circuit for recovering a digital signal can operate with a sampling frequency less than a data frequency. The circuit includes a plurality of interpolators for generating an output signal. The output signal is used by a computation module to generate a plurality of control words. The control words are used by the interpolators to perform weighted interpolation functions to precisely generate the output signal. A data circuit can then extract the original input signal digital information from the output signal.

Abstract: A method and apparatus for synchronizing ATM cells is disclosed. A synchronization unit receives a data clock signal and a plurality of control signals. Based on those signals, a sync pulse is generated. If synchronization is not achieved within a predetermined time period, the sync pulse is shifted one bit location. Through iterative shifting of the sync pulse, synchronization is ultimately achieved.

Abstract: The method of transmitting data as a sequence of high bits and low bits over a transmission line from a transmitting device to a receiving device includes transmitting synchronization signals over the transmission line and transmitting one and only one high bit or one and only one low bit over the transmission line at an end of each synchronization signal. When the predetermined voltage levels for the high bit, low bit and synchronization signals are different from each other, the method is implemented in an especially simple manner. The interfaces for the receiving and transmitting devices for performing the method are also described.