Abstract: An OFDM receiver determines (12; 27) the pulse response of a radio channel and locates (13; 14) its starting point, end point and the maximum and its value. The difference between the end point and the starting point gives the length of the pulse response. A guard interval time corresponding to the guard interval separating the OFDM symbols is set (17; 18) in the receiver in such a manner that it covers the most significant components of the pulse response. A slow and monotonous temporal shift of the pulse response between measurement rounds indicates an error in the sampling frequency. The error is corrected (23; 31) in such a manner that the pulse response shift is compensated for.

Abstract: A data sync signal detecting device with a simple configuration for detecting a sync signal having a few sync signal detection errors is disclosed. The detecting device is configured such that the output data of a most-likelihood decoder constituting a data discriminator is applied to a shift register bit cell and sequentially shifted and held in the bit cells of shift registers. The outputs of these bit cells are separated into an odd-numbered bit string and an even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with "01001" as a predetermined sync signal pattern by a first pattern matching circuit which produces a first matching result. The even-numbered bit string is matched with "01011" as a predetermined sync signal pattern by a second pattern matching circuit which produces a second matching result. The first and second matching results are applied to a coincidence number adder/majority decision circuit.

Abstract: A method (500) of baud detection in a communication device (700) includes the steps of sorting phase pulses among overlapping sets of time slots (502) and counting phase pulses within each of the overlapping sets of time slots creating corresponding counter values (504). Then, counter values are compared with predetermined thresholds (506-512), wherein a baud pass condition (570) is met when at least one counter has a counter value exceeding an upper threshold and wherein a counter N/2 positions away has a counter value below a lower threshold. The baud pass condition may he further conditioned on meeting the requirement that at least another counter value falls below a middle threshold.

Abstract: In a burst mode communication system bursts arrive at a receiver which must correctly acquire and track carrier and clock phases in order to recover the transmitted symbols. A burst mode receiver is used to recover the clock and carrier phase. The detection of an initiator pulse indicates the presence of a burst signal, and a cross-coupled fractionally spaced digital filter structure is used with a known preamble to perform symbol sampling phase recovery and carrier phase acquisition, and during the normal mode of operation results in a tracking of the symbol and carrier phases.

Abstract: High-frequency components are extracted from an OFDM signal. A symbol clock signal is generated in response to the extracted high-frequency components. Specifically, a sample clock signal is generated in response to the OFDM signal. A frequency of the sample clock signal is divided to generate the symbol clock signal from the sample clock signal. A timing of the frequency division is controlled in response to the extracted high-frequency components.

Abstract: A unique word (UW) differential detection system to provide a system that can expand a measurement range for the carrier frequency offset of the quasi-synchronized detection signal while maintaining detection of unique word position at a high accuracy, and maintaining a resolution for the carrier frequency at a low level. In an initial acquisition mode, the detection system uses a first UW differential detection circuit with a symbol delay N (0.5<N.ltoreq.1) and a second differential detection circuit with a symbol delay N/2 to generate a first UW detection signal of a first quasi-synchronized detection signal and first frequency offset information. The first frequency offset information reduces frequency offset of a second quasi-synchronized detection signal for demodulating a data signal.

Abstract: A receiving method for receiving, demodulating and decoding a signal with synchronizing a multicarrier signal having guard times each having the same waveform, includes a correlation detecting step of detecting correlation of a demodulated signal in the time domain, a mean value calculating step of calculating a mean value of a correlated value detected in the correlation detecting step, an accumulating step of accumulating the mean value, a peak detecting step of detecting a peak value of an accumulated value obtained in the accumulating step, a synchronization signal generating step of generating a synchronization signal by using an output signal in the peak detecting step, and a decoding step of decoding a signal by using the synchronization signal.

Abstract: In a receiving apparatus intermittently receiving modulated and transmitted information, a controller controls a supply of source voltage to a synchronization correcting signal generator and a PN code generator for accurately demodulating the intermittently received modulated information and to an information demodulator and an information decoder to be carried out at a timing independent of each other, by which the information demodulator and the information decoder can be driven once while the synchronization correcting signal generator and the PN code generator are driven N times in synchronizm with a timing for driving the synchronization correcting signal generator and the PN code generator.

Abstract: An audio bitstream is read from a digital video disc DVD for transfer, subsequent to parsing thereof, via an IEC 958 protocolled interface, for use in a multi-channel audio reproduction apparatus. For each respective audio channel MPEG audio samples are packaged recurrently in burst payloads, and these burst payloads are packaged as user data in IEC958 format frames. Pause bursts are used for signalling absence of audio for all associated channels with, each pause burst representing such audio absence during a perceptibly acceptable time interval only.

Abstract: The invention presents a method of frame synchronization of Digital Video Broadcasting (DVB) data using a temporary storage area (regfile) of substantially smaller dimension than the repetition rate of the sync pattern. Synchronization is achieved by detecting the sync pattern by correlation and determining if the pattern has a fixed repetitive separation. The synchronization scheme of the invention is simple and easily implementable as an integrated circuit, using software and a microprocessor, or as discrete circuitry.

Abstract: A system and method for generating and repetitively transmitting a single modulated symbol during idle periods in user data in a digital subscriber line (DSL) communication system. The modulated symbol to be transmitted is selected such that its spectral properties match those of user data modulated symbols. For an asynchronous DSL system, and variants thereof, a preferred idle symbol is the "superframe" synchronization symbol. A separate modulated symbol would indicate the end of the idle state. In the preferred embodiment, the end-of-idle symbol is the idle symbol shifted by a 180.degree. phase shift. In a preferred embodiment, the transmitter in a DSL modem would calculate the idle state modulated symbol once at the start of the idle period and then simply repeat this symbol until the end of the idle period, in which case the transmitter would invert the final idle symbol. At the receiver, an idle state modulated symbol detector and phase detector are implemented.

Abstract: In a radio apparatus of such as digital cellular which transmit and receive audio signals upon coded, the frequency error can be detected easily and certainly even in the environment of high noise level. The frequency error .theta..sub.e is detected according to the detection result of the complex correlation value between the synchronizing signal and the standard signal.

Abstract: A clock recovery circuit and method for an MPEG-2 system decoder. The clock recovery circuit comprises a digital signal processor including a controller, a PCR/SCR detector, an adder/subtracter unit, a digital filter and a register, a DAC, a low pass filter, a voltage controlled oscillator and a counter. The counter generates a clock value of a desired number of bits. The PCR/SCR detector receives a transport or program stream and detects a PCR or SCR therefrom. The controller checks whether the detected PCR or SCR is an initial value. If the detected PCR or SCR is the initial value, the adder/subtracter unit subtracts the clock value from the counter from the detected PCR or SCR starting from the least significant bit to generate a first value.

Abstract: A frequency-hopped mobile communication system is disclosed, in which a mobile wireless station automatically becomes a base station in accordance with the surrounding conditions, thereby automatically reconfiguring a communication network. A control frame is generated by at least one master station, and frequencies are hopped by a plurality of slave stations in accordance with the control frame. Each slave station switches the master thereof to be tracked, in accordance with the receiving conditions of the control frame and the relation between the control frame received from the master station and the status of the slave station and decides in which mode, master station or slave station, the slave station is to operate. The cells are thus automatically reconfigured.

Abstract: For frame synchronization, the time position of a synchronization sequence in a received data stream is determined before the frequency and phase synchronization according to the principle of the maximum likelihood theory; the maximum amount of the correlation between the differentially decoded, received data sequence with the conjugated-complex, differentially decoded synchronization sequence known at the reception side is thereby taken into consideration.

Abstract: A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity.

Abstract: A cordless telephone includes a base unit having a data generator which generates a digital data burst having a transition period, a data encoder which encodes the digital data burst, and a transmitter which transmits the encoded data burst; and a handset having a receiver responsive to and sampling the encoded data burst, and a synchronization device operatively coupled to the receiver for maintaining synchronization between the receiver and the transmitted encoded data burst in accordance with a characteristic of an expected time of transition of an incoming signal of the data encoder by comparing an actual time of transition to the expected time of transition and adjusting a sampling point of the transmitted encoded data burst by a one-sided majority vote of samples around the sampling point.

Abstract: A transmission frame comprises a synchronization flag and data bits. It is formed of at least a first subframe in which occur the synchronization flag and an identification field which specifies the number of subframes. Each of the other subframes comprises blocking bits disposed so that the synchronization flag cannot occur in the subframes unless in conjunction with the first subframe.

Abstract: In a method and system for transmitting digital data, a data acceptance clock signal generator that has a controllable clock frequency in a peripheral module is correspondingly adapted to clock frequency information derived from a synchronization pulse train transmitted by a central unit. The same oscillator is used as a frequency source for determining the clock frequency information and for generating the data acceptance clock pulse. In this manner, simple RC oscillators are adequate to fulfill any requirements of long time accuracy of the oscillator. The clock frequency can be changed in that the central unit simply transmits altered clock frequency information. It is also possible to carry out an adjustment or adaptation in the case of deviations of the oscillator frequency in the peripheral unit.

Abstract: An error protection method for multimedia improves data recovery and channel throughput in channels which cause a random error and a burst error by using a rate compatible punctured convolutional code (RCPC) and an automatic retransmission on request (ARQ). In a process of decoding a plurality of packets of given information, the error protection method includes the steps of a) decoding one of the plurality of packets, b) decoding another packet when an error occurs during the decoding in step a), c) decoding a combination of the packets from steps a) and b) or a third packet when an error occurs in step b), and d) repeating step c) until the decoding error no longer occurs. The error protection method has the characteristics of both Type-1 and Type-2 ARQ methods. Therefore, one can obtain constant channel throughput in a channel containing burst errors, a channel containing random errors, and a channel in which the two types of error patterns coexist simultaneously.

Abstract: The invention relates to a control signal for receivers, said control signal being formed by juxtaposing two signal elements of equal duration, and time symmetrical. For example, the signal comprises at least one first pseudo-random noise digital sequence s(N.sub.s -1) to s(0) and, periodically, at least one second digital sequence s(N.sub.s -1) to s(0), corresponding to the inverse, obtained by time symmetry, of said first sequence. The signal may be used in particular for performing time and frequency synchronization on receivers and/or for equalizing signals received by said receivers. The invention also relates to methods and apparatuses that use said signal.

Abstract: A method for a wireless discrete tone communications system, synchronizes the remote station to the base station. The method begins with the step of generating a clock signal at the base station. The base station then derives a synchronization symbol pattern from the base station clock signal and spreads the it with spreading codes that distributes the symbol pattern over a plurality of discrete tones, forming a discrete tone signal. The base station then transmits the spread signal to the remote station. The remote station generates a first clock signal and samples the discrete tones using the remote station first clock signal, forming a first sampled signal. Then the remote station applies the first sampled signal to a matched filter bank, forming a frequency error signal. The method then adjusts a frequency of the remote station first clock signal using the frequency error signal, forming a second clock signal.

Abstract: A method and system for time aligning a frame (60) in a communication network (10) involves the steps of; i) determining if a frame needs to be advanced at a BTS (14), and ii) sending a shortened synchronization pattern from the BSC (12). The BTS (14) then determines if a short or long synchronization pattern has been sent by determining (256) if the received data stream matches a long synchronization pattern and setting a first flag when they do match. If the received data stream does not match the long synchronization pattern and the first flag is set (264), the data stream is compared (266) to the short synchronization pattern. When they match a second flag is set (268).

Abstract: A bit synchronization circuit receives polarity-judged output signal and a level-judged output signal that are produced through demodulation of a 2-value FSK or 4-value FSK transmission signal. Flip-flop circuits and an exclusive-OR circuit generate a second sampling output by sampling and delaying the polarity-judged output signal. Flip-flop circuits and an exclusive-NOR circuit generate a third sampling signal having a given temporal relationship with the second sampling output by sampling and delaying the level-judged output signal. AND circuits supply a correction signal to a counter circuit when levels of the second and third sampling outputs and a phase signal indicating a correction period of the counter circuit satisfy a given relationship. In response to the correction signal, the counter circuit corrects its count so as to produce a clock signal having a rate that is equal to a transmission rate of the transmission signal.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. A synchronization unit controls the decoder to skip a subframe if a predetermined decoding time for the subframe is earlier than a current time, and to repeat the subframe if the predetermined decoding time is later than the current time. A typical MPEG audio frame includes 12 subframes, such that skipping or repeating a subframe is 1/12 as noticeable as skipping or repeating an entire frame. A buffer memory stores one or more subframes prior to decoding, such that the subframes can be skipped or repeated by manipulation of a read pointer for the memory.

Abstract: A discrete multitone modulation transmission system is described in which frame synchronization is monitored using a transmitted synchronizing frame. The existence or loss of frame synchronization is determined by comparing the values of the synchronizing frame with corresponding stored values.

Abstract: A network node destination module for ensuring proper reception and transmission of information over a network having an optional network reference clock including an input stage for receiving the information, a synchronous residual time stamp (SRTS) timing control stage for implementing digital phase comparison techniques utilizing the network reference clock, and a clock generation stage for generating a transmit clock in response to a control value generated by the SRTS timing control stage. The SRTS timing control stage maintains a constant phase offset between the receive clock of the source node and the transmit clock of the destination node. The SRTS timing control stage includes an RTS sample generator for generating a local RTS sample for comparison with the source RTS sample to determine a current phase offset between the source and clocks. The current phase offset is then compared to a target phase offset stored in a phase register to generate a control value.

Abstract: A circuit for decoding an input signal includes a measurement circuit having an input to receive a timing clock signal that is asynchronous with clocking of the input signal, to measure duration of a plurality of pulses received on the input signal in relation to frequency of the timing clock signal and a decode circuit to decode the input signal into digital data. In one embodiment, the circuit may include a servo mechanism for generating the timing clock signal to have a frequency that varies in response to variations in frequency of clocking of data on the input signal. The servo mechanism may include a digitally controlled oscillator and a feedback circuit, to control the digital frequency of the digitally controlled oscillator in response to variation of clocking of data on the input signal. The invention permits use of all digital components for decoding digital audio data encoding using biphase-mark encoded data according to the SPDIF or AES/EBU standards.

Abstract: In the process for data transmission via data blocks between a transmitting station and receiving station the data blocks each have a synchronization pattern field (SYNC), a header field (HEADER) and an information field (INFORMATION) following the header field. The process includes providing a fixed information field (FIXINFO) in each data block for information to be immediately transmitted without delays for error detection and correction following the synchronization pattern field (SYNC); immediately transmitting each fixed information field (FIXINFO) to the receiving station without information from the header field and independently of any occurring transmission errors after a receiver-side synchronization and testing a remaining portion of each data block for at least one error within a predetermined error detection range in the receiving station and, when the at least one error is detected within the detection range, performing an error correction only for that remaining portion of the data block.

Abstract: A method of synchronizing carrier frequencies in a mobile radio network having base and mobile stations, in which a synchronization signal is radiated from the base stations, is received by the mobile stations and is used to derive the transmission frequency.A group of sinusoidal oscillations having different frequencies is emitted from each base station as a synchronization signal. The mobile stations each have a matched filter, with which at least one of the transmitted sinusoidal oscillations can be found and detected.The method is insensitive to fading, and permits an extensive normalization of the circuits in the base stations and, in particular, permits a unified evaluation in the mobile stations.

Abstract: A method for modulating a radio signal has the steps of: predetermining a first time interval so as to define a data word; generating a synchronization pulse, the synchronization pulse initiating a single data word having a length of the predetermined first time interval; and generating a single data pulse within the data word after a second time interval with respect to the synchronization pulse, the length of the second time interval defining at least one character. Defining at least one character by a single data pulse after a second time interval with respect to the synchronization pulse enhances an energy efficiency of the transmitted radio signal while mitigating a duty cycle thereof.

Abstract: In a wide band radio frequency (RF) simulcast communications system analog voice signals are distributed in a digitized form over high speed data channels and processed as high speed data. A conventional Ericsson, Inc. EDACS.TM. simulcast communications system is improved by altering the apparatus and manner by which "clear voice" (unencrypted analog voice) is distributed from a control point and "aligned" at multiple transmitter sites for simultaneous RF broadcasting. In the improved arrangement, the EDACS.TM. simulcast system inherent digital data stream alignment process produces the requisite time domain alignment for the digitized "clear voice" signals without the need for costly analog audio alignment procedures and equipment.

Abstract: A synchronization method and apparatus for synchronizing a receiver, such as a radiotelephone operable in a cellular communication system with a transmitter. Synchronization signals are transmitted as parts of a control signal to the receiver. Such synchronization signals are of high margins and also permit synchronization of the radiotelephone responsive to a reduced number of calculations. The time for such synchronization is reduced by use of nonlinear transformation metrics, such as logarithmic metrics, which reduce the impact of a noise or error component within the control signal.

Abstract: A phase shifter system includes a number of gates 40, 41 for receiving a reference clock and a number of gates 30-33 for receiving a predicted desired phase. The reference clock is manipulated by latches 43-46 and further gates 48, 49 so as to produce quadrature derivatives and these are connected across the resistor chain R1-R9 to produce multilevel waveforms, the steps being selected by selector 36 connected to the resistor nodes under the control of the predicted phase information from gates 30-33. Filtering and reshaping via comparator 50 provides an output clock pulse of desired phase. The output clock can be used to provide phase control in a transmission/reception system on a communications network.

Abstract: The location of a subscriber device in a wireless cellular communications system is established by transmitting digital data signals to a cellular digital data receiver of the subscriber device from at least three different cellular cell site transmitters at known locations. Each data signal has a time-synchronized synchronization signal, preferably synchronized through the time signals of the global positioning system. The time of arrival of each of the time-synchronized synchronization signals is determined with respect to an internal clock of the receiver. The location of the subscriber device is established from the locations of the cell sites and the times of arrival of the synchronization signals relative to the internal clock.

Abstract: An improved SRTS clock recovery system of a network node comprising a novel adaptifier arrangement that continually monitors the flow of data through a data FIFO and briefly assumes control over the SRTS clock recovery system to permanently adjust the phase and/or temporarily adjust the frequency of a transmit clock to avoid dataflow errors. Specifically, the adaptifier includes a phase controller that permanently adjusts a target phase offset utilized by the SRTS clock recovery system to effect a permanent change in the transmit clock phase. A frequency controller of the adaptifier temporarily overrides an error signal generated by the SRTS clock recovery system prior to it being utilized by a clock generator to effect a temporary adjustment of the transmit clock frequency. Clock perturbations are minimized, including graceful entry and exit of adaptifier action. The adaptifier implements either or both adjustments to avoid an impending dataflow error based upon a number of predetermined conditions.

Abstract: A data receiving unit includes a data receiving circuit for receiving, through a transmission path, transmission data which has been encoded into a predetermined transmission code by using a predetermined transmission clock signal and includes a reference pulse having a pulse width corresponding to a period of the transmission clock signal, a clock for generating a received clock signal in synchronization with the transmission data, and a data decoding circuit for decoding the transmission data received by the data receiving circuit using the received clock signal generated by the clock, where the clock includes an oscillator generating at least a reference clock having a period which is shorter than that of the transmission clock signal, a counter circuit counting an interval between points of change of the transmission data received by the data receiving circuit according to the reference clock signal, a reference pulse detector circuit for detecting the reference pulse on the basis of a count value from th

Abstract: A digital audio broadcasting (DAB) system includes a radio-frequency (RF) transmitter and a corresponding RF receiver. The RF transmitter formats a DAB signal into a sequence of frames, each frame having a header comprising a predefined grouping of psuedo-random number sequences comprising 100 symbols. Of these 100 symbols, 86 symbols of the header are used for frame synchronization and channel sounding (for characterization of a communications channel), while the remaining 14 symbols are used for interleaver and data synchronization in an interleaved fashion.

Abstract: Briefly, in accordance with one embodiment of the invention, a coarse frequency burst detector for use at the receiving end of a wireline communications system comprises: a digital signal filter adapted to filter a component of decoded signal samples, the decoded signal samples being derived from a baseband signal transmitted via the wireline communications system; and a threshold detector adapted to threshold the signal level of the filtered component of the decoded signal samples with respect to a substantially predetermined level. In accordance with another embodiment, a method of detecting at the receiving end of a wireline communications system a frequency burst in a baseband signal transmitted via the wireline communications system comprises the steps of: filtering a component of a decoded signal derived from the baseband signal transmitted via the wireline communications system; and thresholding the filtered component.

Abstract: A synchronous serial communication link between a controller and a peripheral is resynchronized by the sending of a series of bits at a first logic level by the controller. The series of bits is long enough to ensure that the peripheral will decode a command word in which all of the bits are at the first logic level. The peripheral, upon decoding such a command word, resets the synchronization circuitry within the peripheral. The controller then sends a single bit of the opposite logic state followed by serial data. The peripheral, upon receipt of this bit of the opposite logic state, releases the synchronization circuitry from its reset condition and begins to decode the serial data in synchronization with the controller.

Abstract: A data discriminating circuit is provided on the receiver side of a digital signal transmission system, and performs data discrimination with a proper phase relation settled between data and a clock signal. In the discrimination circuit, a data discriminating section discriminates input data in synchronism with a clock signal and outputs resultant data as discriminated data, a phase-relation judging section judges a phase relation between the input data and the discriminated data, a clock phase controller produces a phase control signal to control and initially-determined phase of the clock signal, based on an output of the phase-relation judging section, and a clock phase judging section determines a phase of the clock signal and alters the initially-determined phase of the clock signal in accordance with the phase control signal from the clock phase controller.

Abstract: A matrix display of light reflecting elements is capable of displaying images represented by data codes received from a variety of different sources at different respective frame rates. The codes are stored at whatever frame rate they are received, but are read at a subframe rate which is an integral multiple of each of the different frame rates.

Abstract: One can compensate for signal propagation delay in an open-loop system of interconnected components by fixing overall path propagation time and selectively adjusting transmit timing at each of the interconnected components.

Abstract: The audio system having a master clock, a serial port clocked according to a serial clock from the audio system, a programmable audio functional circuitry programmable and operable at a plurality of sample rates, and a rate selection control logic which sense a ratio between the serial clock and the master clock. The serial clock is derived from the master clock. The rate selection control logic reprograms the audio functional circuitry based on the ratio, to operate at one of the plurality of sample rates in response to a change in the clock rate of the serial clock, such that the audio functional circuitry operates at another of the plurality of sample rates.

Abstract: A method and apparatus for processing a plurality of facility datalinks is provided. In particular, synchronizers (14 and 16) receive multiple facility datalinks and synchronize them. These synchronized signals are transmitted to FDL state machine (18). FDL state machine (18) separately stores each of the facility datalinks in a memory (20). A processor (22) accesses the facility datalinks stored within memory (20) and initiates responses based on the accessed facility datalinks.

Abstract: A data transfer apparatus includes a computer-side input and output unit for transmitting a data signal which is periodically updated, and a printer-side input and output unit for receiving the data signal transmitted from the computer-side input and output unit and detecting the logic level of the data signal. Particularly, this data transfer apparatus further includes a state transition time measuring circuit, a computer-side CPU, and a printer-side CPU cooperated to transmit a transition test data signal from the computer-side input and output unit in a tuning mode, measure the transition time of the transition test data signal received by the printer-side input and output unit, and adjust transfer parameters which define the transmission rate of the data signal to be transmitted from the computer-side input and output unit and a timing for detecting the logic level of the data signal, on the basis of a result of measurement.

Abstract: A modulator used in an IC card reader/writer includes a phase variation detector for detecting a varying point of the phase of a modulated signal, a signal processing circuit for modifying the modulated signal for a half period at the phase varying point to have a frequency and amplitude twice those of the modulated signal, a first Miller integrator for integrating the modified signal to produce a triangular wave signal, and a second Miller integrator for integrating the triangular wave signal to produce a sinusoidal wave signal having a continuous phase. A demodulator used in the reader/writer includes a sync control circuit which controls a carrier sync signal generation circuit thereby to control the phase of a carrier sync signal in response to the discrimination as to whether the carrier sync signal is in lead-phase or lag-phase relative to the signal modulated based on binary phase shift keying (BPSK).

Abstract: A signal transmitting apparatus using orthogonal frequency division multiplexing includes an inverse fast Fourier transform circuit for converting a digital information signal into a first multi-value QAM modulation signal. A guard interval setting circuit is operative for periodically generating a guard interval signal equal to a time segment of the first multi-value QAM modulation signal, and inserting the guard interval signal into the first multi-value QAM modulation signal to convert the first multi-value QAM modulation signal into a second multi-value QAM modulation signal. A clock signal generating circuit is operative for generating a first clock signal which drives the inverse fast Fourier transform circuit, and generating a second dock signal which drives the guard interval setting circuit. The inverse fast Fourier transform circuit includes a device for generating a pilot signal which corresponds to a given-order carrier, and adding the pilot signal to the first multi-value QAM modulation signal.

Abstract: An apparatus and method for a data communications device such as a modem (100, 101) to determine carrier frequency offset and timing frequency offset, from a received probe signal. The various embodiments utilizing a processor (108) or digital signal processor (106) receive first and second sets of a transmitted probe signal having known characteristics, and determine a set of phase differences for the tones comprising the probe signal (702, 703, 704, 705). The various method and apparatus embodiments then form a linear approximation from the set of phase differences to determine the carrier frequency offset and the timing frequency offset (706). In the preferred embodiments, the linear approximation is formed from a minimization of a least square error estimate proportionally weighted by either signal to noise ratios or normalized, average amplitudes of the set of tones of the received probe signal.

Abstract: A Residual Time Stamp (RTS) technique provides a method and apparatus for recovering the timing signal of a constant bit rate input service signal at the destination node of a synchronous ATM telecommunication network. At the source node, a free-running P-bit counter counts cycles in a common network clock. At the end of every RTS period formed by N service clock cycles, the current count of the P-bit counter, defined as the RTS, is transmitted in the ATM adaptation layer. Since the absolute number of network clock cycles likely to fall within an RTS period will fall within a range determined by N, the frequencies of the network and service clocks, and the tolerance of the service clock, P is chosen so that the 2.sub.P possible counts, rather than representing the absolute number of network clock cycles an RTS period, provide sufficient information for unambiguously representing the number of network clock cycles within that predetermined range.