Abstract: A server apparatus receives packetized data and transmits the packetized data over a network. The apparatus includes an input for receiving the packetized data from a signal source. An AC clock counter receives an AC power signal and generates a count value in dependence upon a frequency of the AC power signal. An output is coupled to the network and transmits the packetized data and the count value to a client device. A clock associated with the client device is controlled in dependence upon the count value.

Abstract: A method for synchronizing receivers that receive turbo encoded signals to a received signal. Turbo encoding may enable signals to be decoded at a much lower signal to noise ratio than previously practical. A traditional method of synchronizing a receiver to an incoming signal is to use a slicer to determine a received symbol and then to compare the determined symbol to the incoming waveform, in order to adjust the phase of the slicer with respect to the incoming signal. At signal low levels, at which turbo encoded signals may be decoded, this slicing method may be prone to errors that may disrupt the synchronization of the receiver to the incoming signal. By replacing the slicer by a Viterbi decoder with zero traceback (i.e. one which does not consider future values of the signal only past values) a prediction as to what the incoming signal is can be made.

Abstract: A method and apparatus for time synchronization (TS) method using GPS information in a communication system synchronizing the time of slave nodes, which do not have a GPS receiver, by using GPS information of a node having a GPS receiver. The method includes the steps of extracting 1PPS, TOD, 1PPS_en, and clocks using GPS signals by a grand master node having a GPS receiver, stabilizing the signals, generating a sync message for TS, and transmitting the sync message to a slave node; receiving the sync message by the slave node and conducting a TS operation using OFCC synchronization technology extracting 1PPS, TOD, and 1PPS_en signals using the modified TOD information by the block and delivering to a stabilization block of the slave node for stabilization; and redelivering to the TS block to update TOD information and generate a sync message for TS of a second slave node.

Abstract: A technique for efficient implementation of pilot signals on a reverse link in a wireless communication system. An access channel is defined for the reverse link such that within each frame, or epoch, a portion is dedicated to sending only pilot symbols. Another portion of the frame is reserved for sending mostly data symbols; however, within this second portion of the frame, additional pilot symbols are interleaved among the data symbols. The pilot symbol or preamble portion of the access channel frame allows for efficient acquisition of the access signal at the base station, while providing a timing reference for determining the effects of multipath fading. In particular, a pilot correlation filter provides a phase estimate from the pilot symbols in the preamble portion, which is then used to decode the data symbols in the payload portion. An access acquisition portion of the receiver uses the phase estimates provided by the pilot correlation filter to process the output of a data symbol correlation filter.

Abstract: A method for the synchronization of a digital telecommunication receiver comprises the steps of:—storing a plurality of consecutive samples E?1, E, M, L, L+1 of an incoming spread spectrum signal in a delay line 56;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a first digitally controlled interpolator 26, an interpolated early sample (e) anticipating an optimal sampling time instant;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a second digitally controlled interpolator 24, an interpolated middle sample (m) corresponding to the optimal sampling time instant;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a third digitally controlled interpolator 28, an interpolated late sample (l) delayed with respect to the optimal sampling time instant;—calculating an error signal ? as the difference between the energy of the symbols com

Abstract: A microcontroller having digital to frequency converter and pulse frequency modulator capabilities. The digital to frequency converter (DFC) generates a 50 percent duty cycle square wave signal that may be varied in frequency, wherein the 50 percent duty cycle square wave signal is directly proportional and linear with a count value put into an increment register. The pulse to frequency modulator (PFM) generates pulses having pulse widths of the input clock for each rollover of a counter. The frequency of these pulses is directly proportional and linear with the count value put into the increment register.

Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

Abstract: Methods and systems for detecting bit synchronization boundary in a received signal. A counter is set for defining a bit boundary of the received signal. Transitions in the received signal are detected and compared with the counter value as the transitions are expected to occur only at the bit boundary. The bit boundary is confirmed if a preset number of transitions aligned with the bit boundary.

Abstract: Some embodiments store a training sequence in a communications system. The stored training sequence exhibits certain desirable characteristics when used by a peak to average power constrained modulation format. In one embodiment, a set of original ordered sequences is selected to have at least one desired property. A set of extended sequences is created from the original sequences by beginning with an element of an original sequence and cyclically appending elements of the original sequence in order to obtain a desired extended sequence length. Each extended sequence is modified using a corresponding modifying sequence, such that a training sequence can be generated from any one of the modified extended sequences. Each modifying sequence is selected so that the generated training sequence when modulated by a selected modulation format has the at least one desired property of the corresponding original ordered sequence.

Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

Abstract: A method and a bit stream decoding unit for bit stream decoding has a bit stream comprising a number of consecutive samples. In order to provide for rapid and, in particular, reliable decoding of the bit stream, a detection window comprising a number of samples is defined and the detection window is positioned at certain positions on the bit stream in order to comprise certain samples with respective sample values. A majority voting is applied to the sample values in the detection window and, in dependence on the result of the majority voting, the bit stream is decoded and respective bit values are generated.

Abstract: A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal.

Abstract: The present invention provides a transceiver couplable to a communications network having a jitter control processor and method of operating the same. In one aspect of the present invention, the jitter control processor of the transceiver includes a receiver stage. The receiver stage includes: (1) a receive time error measurement system configured to generate a receive time error signal as a function of a receive clock signal experiencing jitter and a feedback signal, (2) a jitter processing circuit configured to develop a dejittered control signal as a function of the time error signal, and (3) a clock generator system configured to provide the feedback signal as a function of the dejittered control signal and a transceiver local clock signal.

Abstract: A method of correlating a signal to a synchronization pattern is disclosed. The signal has a waveform with frequency and phase angle components that may be varied, at each repeated signal pulse, to communicate a change in a bit pattern of the signal. A synchronization pattern is generated using knowledge of phase rotation direction due to two consecutive bits in a synchronization key. The signal is compared with the synchronization pattern. It is determined whether the comparison of the signal and the synchronization pattern indicate a correlation between the signal and the synchronization pattern.

Abstract: Systems and methods are described for distribution of synchronization in a packet switched local area network environment. A method for extracting network synchronization timing from a data transmission burst includes: recovering a clock during the data transmission burst; and then holding over the clock after the data transmission burst ceases. A method for inserting network synchronization timing into a data transmission burst includes encoding data using a time-base reference signal governed clock.

Abstract: A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal (MODE) represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters (300 and 400) and is detected using differential receiver (600). One embodiment is presented that achieves signaling of an extended run length data sequence to allow continued transmitter/receiver synchronization throughout the transmission of the sequence. In an alternate embodiment, a separate data path is provided to signal the extended run length sequence when a common mode signaling path is not available.

Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). THE CDR circuitry is provided with a programmable serializer and/or deserializer that can support higher data clock rates than the highest clock rate associated with the reference clock signal or clock signal from a phase locked loop circuit.

Abstract: A programmable spread spectrum clock generator (SSCG) reduces electromagnetic interference by spreading the frequency bandwidth of an output signal. The rate at which the frequency of the output signal changes, as well as other aspects of the output signal, are software programmable. The programmable SSCG receives a periodic signal whose cycles have substantially identical periods and outputs the output signal whose cycles have periods that vary smoothly over a plurality of cycles of the periodic signal. The programmable SSCG generates a control signal using the periodic signal. The programmable SSCG includes a variable delay element that generates the output signal by delaying the periods of the periodic signal based on the magnitude of the control signal. The output signal is generated without using a phase locked loop. Moreover, successive cycles of the output signal rarely have identical periods.

Abstract: The invention relates to power control of a cellular mobile communication system using TPC, and a power control circuit in a base station set and a radio terminal is equipped with a synchronism detecting unit for detecting synchronism data indicating synchronism establishment from radio data every frame; a synchronism/asynchronism judging unit for judging synchronism/asynchronism based on the synchronism data, an execution/unexecution judging unit for judging execution/unexecution of TPC based on the synchronism data, TPC bits extracting unit for detecting TPC bits contained in the radio data, and a selection control unit for selecting execution/unexecution of transmission power control using the TPC bits based on the judged result and the judged result. 3-Stage control of suspension, execution and unexecution of TPC becomes feasible every frame on the basis of quality, more stable quality can be secured, and increase in the quantity of channel interference can be prevented.

Abstract: A circuit board includes a pair of interconnects configured to support conveyance of a differential mode communication signal, which comprises a balanced first signal (e.g., signal X) and corresponding second signal (e.g., signal ?X) of opposite polarities. A transmitter circuit coupled to the pair of interconnects supports generation of a non-differential mode communication signal that is different than a classic differential mode communication signal. A receiver circuit coupled to the first pair of interconnects supports reception of the non-differential mode communication signal. Thus, the pair of interconnects convey the non-differential mode communication signal instead of the differential mode communication signal, mitigating interference with other pairs of interconnects on the circuit board that convey yet other communication signals.

Abstract: A frame synchronous circuit operable in a dedicated short-range communication system, applicable to several modulation schemes, includes a UW detector for detecting a UW word from received data, an operation setting register group for specifying the operations of an on-board unit, a synchronous manager for controlling synchronization, an unlimited synchronization continuation register for maintaining the unlimited continuation of the synchronization, and an FCMC data analyzer for analyzing FCMC data. The operation setting register group can control synchronization by using not only operational information obtained from the FCMC data but also another operational information retrieved from an input device such as a CPU or terminal connected to the on-board unit. Consequently, debug and test operations can be performed without receiving any FCMC data.

Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Abstract: In a null symbol detection device, at the time of receiving a terrestrial digital broadcast, a null symbol can be stably detected even under a fading environment. A synchronous addition buffer group is provided subsequent to an amplitude detector so as to synchronously add an OFDM signal at a null symbol repetition period. A moving average processing unit performs a moving average operation upon synchronous addition data with the number of samples corresponding to a null symbol to output a moving average value. A transmission mode determining unit detects the minimum value among the moving average values normalized in a correction processing unit and compares levels of the minimum values to determine a reception mode. A null position detector generates a synchronous pulse at a null position.

Abstract: In a data processor, a pickup head reads the data from a memory medium. Such data transferred in a plurality of parallel bits in synchronization with the clock signal to a controller unit from a read channel unit. The controller unit detects the predetermined mark for detecting synchronization included in the data in order to establish the synchronization of a series of data to be received from the read channel unit in order to demodulate the data other than the predetermined mark for detecting synchronization. The mark detecting unit in the controller unit detects the predetermined mark for detecting synchronization from the parallel data received with the shift register.

Abstract: Methods and apparatus for synchronizing a stereo viewing device in a multiple end-view environment. Two or more video streams and a corresponding number of signals, each synchronous with one of the video streams, are provided. Each of the video streams may have a different refresh rate. One of the video streams is selected for stereo viewing, and a corresponding synchronizing signal is selected. The selected synchronizing signal is used to generate a control signal that synchronizes a stereo viewing device to the selected video stream.

Abstract: A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer.

Abstract: A method is for decoding a bit stream from a waveform representing the bit stream, having a first synchronization mark, data, and a second synchronization mark. Digitized samples are decoded to form a reconstructed bit stream. The reconstructed bit stream is then stored. At least one of the first synchronization mark and the second synchronization mark are then extracted from the reconstructed bit stream. Finally, the data are extracted from the reconstructed bit stream using an iterative decoding process, in accordance with at least one of the first synchronization mark and the second synchronization mark. As such, loss of the data between the first synchronization mark and the second synchronization mark, if there is a problem with the first synchronization mark, is avoided.

Abstract: A receiving terminal for CDMA system for receiving received signals from a plurality of signal propagation channels is disclosed. The electric field level of the received signal from each signal propagation channel is judged, and the operation control clock supply to a circuit system receiving signal from a low electric field level signal propagation channel is suspended for a predetermined period of time for power consumption reduction.

Abstract: A data sync signal detecting device for detecting a sync signal having sync signal detection errors. The detecting device applies the output data of a most-likelihood decoder to shift register bit cells. The data is sequentially shifted and held in the bit cells of the shift register. The bit cell outputs are separated into odd-numbered and even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with “01001” by a first pattern matching circuit. The even-numbered bit string is matched with “01011” by a second pattern matching circuit. First and second matching results are applied to a coincidence number adder/majority decision circuit. When coincidence occurs, the matching result is “1”, and when non-coincidence occurs, the matching result is “0”. The coincidence number adder/majority decision circuit produces a sync signal detection output when the first or second matching result is “1”.

Abstract: A method for the reception of a signal comprising the following steps: 1) on the detection or reception of an edge in the received signal, a counting cycle Nc is activated, 2) when the value of Nc is equal to a number M of beeps of a generation clock Hg, a leading edge of the reception clock signal is sent and a new counting cycle Nc is activated, 3) when this new value of Nc is equal to a number M of beeps of a generation clock Hg, the clock Hr is made to pass to zero, and simultaneously 3.1) in the event of reception of an edge in the received signal, a new clock signal edge is sent when Nc=M, 3.2) in the event of non-reception in the received signal, a new clock signal edge offset by a value of 1(M+1) is sent when Nc=M, 4) the steps 1) and 2) are executed so long as the header is not detected, 5) upon the detection of a header, a Header Found signal is sent, the steps 1), 2), 3) and 3.1) are executed and this Header Found signal is transmitted at a processing step.

Abstract: A wireless communication system can comprise two or more antennas that interfere with one another via free space coupling, surface wave crosstalk, dielectric leakage, or other interference effect. The interference effect can produce an interference signal on one of the antennas. A cancellation device can suppress antenna interference by generating an estimate of the interference signal and subtracting the estimate from the interference signal. The cancellation device can generate the estimate based on sampling signals on an antenna that generates the interference or on an antenna that receives the interference. The cancellation device can comprise a model of the crosstalk effect. Transmitting test signals on the communication system can define or refine the model.

Abstract: In a security system, a method and apparatus for two-way frequency hopping communications between the control panel and each peripheral device which maintains channel synchronization through the assignment of fixed beacon frequencies for the transmission of synchronizing data. The use of frequency hopping provides high immunity to jamming and interference, reduced occurrence of multi-path phenomena, and allows for transmissions at a much higher output power than conventional fixed-frequency communications, to thus increase the effective range of the peripheral devices while providing effective and reliable two-way communications between the control panel and the peripheral devices. The invention also provides a large number of channels, which allows for actuators such as sirens, strobes and line seizing devices to be wireless in addition to sensors.

Abstract: A received wireless signal contains a plurality of path components, each having a phase indeterminate data stream derived from an original data stream. The receiver splits the received signal into N signal copies for N raking channels, which correlate each of the N signal copies with N locally generated signals, respectively, to generate N correlated signals. Each of the N correlated signals carries an estimated phase indeterminate data stream. The raking channels then synchronize each of the correlated signals to a system clock in phase and frequency to generate N synchronized signals. The N raking channels then align the N synchronized signals to generate N aligned signals, each of which carries an aligned path data stream that is normalized in time with respect to the other aligned signals. Finally the receiver combines the aligned signals to produce an estimated original data stream.

Abstract: Synchronization of a bus master to a bus slave permits the desired hierarchical structuring of buses by virtue of a bus slave on a bus receiving the synchronization information for an associated bus master is disclosed. A phase locked loop is used to filter this clock information and to regenerate missing clock pulses. This clock which is now “sound,” is supplied to one or more parallel bus masters of other buses, which generate the corresponding clock information using the necessary messages on the respective bus. This principle is independent of the respective bus system, which means that a plurality of identical buses or else different bus systems can be operated hierarchically in synchronization with one another.

Abstract: A demodulator for demodulating digital data includes a receiver for receiving a digital data signal, a determining device to determine if a fractional sample delay added to a demodulator's symbol sampling timing would improve synchronization timing, an implementing device implementing the fractional sample delay if the determining device determines that a fractional sample delay would improve the demodulation synchronization timing, and a demodulating device for demodulating the digital data signal. A method for demodulating digital data includes the steps of receiving a digital data signal, determining if a fractional sample delay added to a demodulator's symbol sampling timing would improve synchronization timing, implementing the fractional sample delay if it is determined in the determining step that a fractional sample delay would improve the demodulation synchronization timing, and demodulating the digital data signal.

Abstract: The present invention refers to a method and an apparatus for synchronizing operation at a node of a communication network. According to the invention a phase relationship between an output frame synchronization signal and an input frame synchronization signal is controlled by the adjustment of a phase difference between the output frame synchronization signal and a node synchronization signal.

Abstract: A demodulation method for establishing clock synchronization within a short period of time from a received signal modulated by ?/4-shift QPSK modulation that contains a synchronization establishment signal wherein the change in phase periodically alternates between positive and negative, and for demodulating the received signal. The method includes establishing synchronization from the received signal based on the timing of changes in the positive/negative polarity of the change in phase of the synchronization establishment signal contained in the received signal, and demodulating the received signal.

Abstract: A method and apparatus are provided that generate, transmit, or receive a training sequence in a communications system, where the training sequence exhibits certain desirable characteristics when used by a peak to average power constrained modulation formal. In one embodiment, the invention includes selecting an original training sequence from a set of possible original training sequences having at least one desired property, forming a modified training sequence by modifying the original training sequence based on a corresponding modifying sequence, such that the modified training sequence exhibits the desired property of the original training sequence when used in a peak to average power constrained modulation format that would otherwise impair the desired property of the original training sequence.

Abstract: A reception AGC circuit includes a high-speed power calculating circuit for calculating the power of an input signal at a short period, a normal power calculating circuit for calculating the power at a normal period, a circuit for receiving a power calculation result from the high-speed power calculating circuit or normal power calculating circuit to calculate a feedback amplification value, and addition amplification value setting units for self-station communication and peripheral station monitoring which receive the feedback amplification value through a switch and add the feedback amplification value to an amplifier in use.

Abstract: A method of producing a correction signal includes receiving a predetermined data sequence (500). The data sequence is sampled at predetermined times, thereby producing a sampled data sequence (522, 532). The sampled data sequence is separated into first and second sampled data sequences. A ratio is calculated (550, 558) from the first and second sampled data sequences. A correction signal is produced (556, 564) in response to the ratio.

Abstract: An apparatus and method for OFDM demodulation establish symbol synchronization to minimize between-symbol interference even under an environment where multipath occurs. An incoming signal is an OFDM signal including a transmission symbol structured by a valid symbol period and a guard interval, and a predetermined synchronization symbol is included in the OFDM signal for every transmission frame. A correlator calculates how a signal generated by a synchronization symbol generator and the OFDM signal are correlated. A correlation calculator then calculates a correlation therefrom. An integrator integrates the calculated correlation by the guard interval. A timing determination device determines symbol timing from the integrated correlation. An FFT window generator outputs operation timing for Fourier transform from the determined symbol timing.

Abstract: A method and system is provided for clock/data recovery for self-clocked high speed interconnects. A data signal is received and then equalized. The equalized data signal then provides the trigger to separate “ones” and “zeros” one-shots. The equalized Manchester data signal is also integrated, compared with a threshold value to determine the negative and positive peaks of the data signal. Then after the appropriate peak is determined, a mid-bit signal is sent as input to a set-reset flip-flop which thereby outputs an asynchronous recovered non-return to zero signal. This asynchronous recovered non-return to zero signal then provides an enable input to the “ones” one-shot and the complementary asynchronous recovered non-return to zero signal provides an enable input to the “zeros” one-shot. The “ones” one-shot outputs a “ones” clock signal and the “zeros” one-shot outputs a “zeros” clock signal. These two signals are verified and a recovered clock out signal is provided.

Abstract: The present invention provides a transceiver couplable to a communications network having a jitter control processor and methods of operating the same. In one aspect of the present invention, the jitter control processor of the transceiver includes a transmitter stage that controls a transmit signal. In one embodiment, the transmitter stage includes a transmit time error measurement system configured to generate a transmit time error signal as a function of timing synchronization associated with a communications network clock and a transceiver master clock, a transmit filter circuit configured to develop a filtered time error signal as a function of the transmit time error signal, and a stuffing control system configured to insert a stuffing control signal into the transmit signal as a function of the transmit time error signal and the filtered time error signal.

Abstract: A transmission method uses multiple kinds of control codes to be exchanged on a serial transmission path between a sender side and a receiver side, and each of the multiple kinds of control codes has bits smaller in number than a predetermined fixed length.

Abstract: An arrangement for capturing data from a data stream of a predetermined data transfer rate using a flip-flop, comprises a symmetrical multi-phase clock generator that is adapted to be locked to a reference clock which in turn is adapted to generate a reference clock signal at the data transfer rate or at a fraction thereof. The multi-phase clock generator is adapted to generate “n” clock signals mutually shifted in phase 360°/n from each other. A selector is connected to the clock generator to receive the n clock signals and selects one of these n clock signals as the system clock signal in response to a control signal from a clock phase counter. The clock phase counter is controlled to count up or down in response to the phase of the system clock signal when a predetermined number of data transitions have occurred in the data stream. The flip-flop is controlled by the opposite phase of the system clock signal to capture the data from the data stream.

Abstract: A interface, which connects memory and an integrated circuit, having a write path and read path that allow synchronous data propagation is provided. Further, a method for synchronizing data propagation through a read path and a write path of an interface is provided. The interface uses clock signals and paths based on a clock signal to synchronize the flow of data through various paths within the interface.

Abstract: A system selects a tone at which a pilot sequence is to be transmitted. The system includes logic configured to adaptively select a tone on which the pilot sequence is transmitted based one or more conditions in the transmission system.

Abstract: A method of processing a stream of encoded units of data samples includes the step of calculating a sample advantage using timing information embedded in selected ones of the encoded units, the sample advantage representing a time difference in number of samples between the presentation of a reference sample and the availability of the reference sample. A number of phantom samples substantially equal to the number of samples represented by the calculated sample advantage are queued and then output from the queue at a selected rate. Substantially simultaneous with the outputting of the phantom samples from the queue, at least some data samples of at least one encoded unit are decoded and queued behind the phantom samples.

Abstract: At the transmitter side, carrier waves are modulated according to an input signal for producing relevant signal points in a signal space diagram. The input signal is divided into, two, first and second, data streams. The signal points are divided into signal point groups to which data of the first data stream are assigned. Also, data of the second data stream are assigned to the signal points of each signal point group. A difference in the transmission error rate between first and second data streams is developed by shifting the signal points to other positions in the space diagram expressed at least in the polar coordinate system. At the receiver side, the first and/or second data streams can be reconstructed from a received signal. In TV broadcast service, a TV signal is divided by a transmitter into low and high frequency band components which are designated as first and second data streams respectively.

Abstract: An error protection method for multimedia improves data recovery and channel throughput in channels which cause a random error and a burst error by using a rate compatible punctured convolutional code (RCPC) and an automatic retransmission on request (ARQ). In a process of decoding a plurality of packets of given information, the error protection method includes the steps of a) decoding one of the plurality of packets, b) decoding another packet when an error occurs during the decoding in step a), c) decoding a combination of the packets from steps a) and b) or a third packet when an error occurs in step b), and d) repeating step c) until the decoding error no longer occurs. The error protection method has the characteristics of both Type-1 and Type-2 ARQ methods. Therefore, one can obtain constant channel throughput in a channel containing burst errors, a channel containing random errors, and a channel in which the two types of error patterns coexist simultaneously.