Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.

Abstract: An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.

Abstract: An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

Abstract: Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.

Abstract: A method of manufacturing a semiconductor device includes forming a charge compensation device structure in a semiconductor substrate. The method further includes measuring a value of an electric characteristic related to the charge compensation device. At least one of proton irradiation and annealing parameters are adjusted based on the measured value. Based on the at least one of the adjusted proton irradiation and annealing parameters the semiconductor substrate is irradiated with protons, and thereafter, the semiconductor substrate is annealed.

Abstract: The threshold voltage is shifted in a negative or positive direction in some cases by an unspecified factor in a manufacturing process of the thin film transistor. If the amount of shift from 0 V is large, driving voltage is increased, which results in an increase in power consumption of a semiconductor device. Thus, a resin layer having good flatness is formed as a first protective insulating film covering the oxide semiconductor layer, and then a second protective insulating film is formed by a sputtering method or a plasma CVD method under a low power condition over the resin layer. Further, in order to adjust the threshold voltage to a desired value, gate electrodes are provided over and below an oxide semiconductor layer.

Abstract: Provided is a display device including: a substrate; and multiple pixels provided on the substrate, the pixels each having an organic EL element obtained by laminating a lower electrode provided on the substrate, an organic compound layer, and an upper electrode in the stated order, and the lower electrode including an electrode independently placed for each of the pixels, in which: the lower electrode is formed of a first lower electrode layer provided on the substrate and a second lower electrode layer provided on the first lower electrode layer; the organic compound layer and the upper electrode cover the first lower electrode layer and the second lower electrode layer; and charge injection property from the second lower electrode layer into the organic compound layer is larger than charge injection property from an end portion of the first lower electrode layer into the organic compound layer.

Abstract: A transistor including an oxide semiconductor with favorable electric characteristics and a manufacturing method thereof are provided. A semiconductor device includes a transistor. The transistor includes an oxide semiconductor film over a base insulating film, a gate electrode overlapping with the oxide semiconductor film with a gate insulating film interposed therebetween, and a pair of electrodes in contact with the oxide semiconductor film and serving as a source electrode and a drain electrode. The base insulating film includes a first oxide insulating film partly in contact with the oxide semiconductor film and a second oxide insulating film in the periphery of the first oxide insulating film. An end portion of the oxide semiconductor film which crosses the channel width direction of the transistor is located over the second oxide insulating film.

Abstract: A method of manufacturing a substrate of a display device is disclosed. The method comprises forming a pixel electrode having a side edge that is under a patterned thermosetting insulating material layer. The method also comprises forming, from the patterned thermosetting insulating material, an insulating layer that covers the side edge of the pixel electrode by heat-treatment of the patterned thermosetting insulating material. As a result of the heat treatment of the patterned thermosetting insulating material, the patterned thermosetting insulating layer melts over the side edge of the pixel electrode.

Abstract: Provided is a functional thin film forming method comprising: (a) forming a transparent semiconductor layer on a substrate; (b) adjusting a surface resistance of the transparent semiconductor layer by performing a n-type doping process on the transparent semiconductor layer formed in the step (a); and (c) forming an insulating protective film of SiOx on the transparent semiconductor layer of which the surface resistance is adjusted in the step (b), wherein the surface resistance of the transparent semiconductor layer is in a range of from 10 M?/? to 100 M?/?.

Abstract: An organic light-emitting device including a substrate, an anode layer on the substrate, the anode layer including WOxNy (2.2?x?2.6 and 0.22?y?0.26), an emission structure layer on the anode layer, and a cathode layer on the emission structure layer.

Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.

Abstract: A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.

Abstract: There is provided a thin film transistor including an active layer on a substrate (the active layer including polysilicon and a metal catalyst dispersed in the polysilicon, a source area, a drain area, and a channel area), a gate electrode disposed on the channel area of the active layer, a source electrode electrically connected to the source area, and a drain electrode electrically connected to the drain area, wherein the gate electrode, the source area, and the drain area of the active layer include metal ions, the source area and the drain area are separate from each other, and the channel is disposed between the source area and the drain area.

Abstract: A process fabricates a fin field-effect-transistor by implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. A height of the cavity defines a height of the epitaxially grown semiconductor.

Abstract: In a processing method of a stacked-layer film in which a metal film is provided on an oxide insulating film, plasma containing an oxygen ion is generated by applying high-frequency power with power density greater than or equal to 0.59 W/cm2 and less than or equal to 1.18 W/cm2 to the stacked-layer film side under an atmosphere containing oxygen in which pressure is greater than or equal to 5 Pa and less than or equal to 15 Pa, the metal film is oxidized by the oxygen ion, and an oxide insulating film containing excess oxygen is formed by supplying oxygen to the oxide insulating film.

Abstract: An organic electroluminescent (EL) element comprises: an anode; a cathode; a functional layer disposed between the anode and the cathode, and including a light-emitting layer containing an organic material; a hole injection layer disposed between the anode and the functional layer; and a bank that defines an area in which the light-emitting layer is to be formed, wherein the hole injection layer includes tungsten oxide and includes an occupied energy level that is approximately 1.8 electron volts to approximately 3.6 electron volts lower than a lowest energy level of a valence band of the hole injection layer in terms of a binding energy, the hole injection layer has a recess in an upper surface of the area defined by the bank, and an upper peripheral edge of the recess is covered with a part of the bank.

Abstract: Some embodiments include a method of providing a semiconductor device. The method can include: (a) providing a flexible substrate; (b) depositing at least one layer of material over the flexible substrate, wherein the deposition of the at least one layer of material over the flexible substrate occurs at a temperature of at least 180° C.; and (c) providing a diffusion barrier between a metal layer and an a-Si layer. Other embodiments are disclosed in this application.

Abstract: A method for fabricating a pixel structure includes the following steps. A patterned semiconductor layer, an insulation layer, and a patterned metal layer are formed on a substrate sequentially. A first inter-layer dielectric (ILD) layer is formed to cover the patterned metal layer. A low temperature annealing process is performed after forming the first ILD layer. A hydrogen plasma treatment process is performed after the low temperature annealing process. A second ILD layer is formed to cover the first ILD layer after the hydrogen plasma treatment process. A third ILD layer is formed to cover the second ILD layer. A source electrode and a drain electrode are formed on the third ILD layer. A passivation layer is formed on the source electrode and the drain electrode. A pixel electrode is formed on the passivation layer. A pixel structure manufactured by the above-mentioned method is also provided.

Abstract: A process fabricates a fin field-effect-transistor by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.

Abstract: The present invention relates to a visible ray sensor and a light sensor capable of improving photosensitivity by preventing photodegradation. The visible ray sensor may include: a substrate, a light blocking member formed on the substrate, and a visible ray sensing thin film transistor formed on the light blocking member. The light blocking member may be made of a transparent electrode, a band pass filter, or an opaque metal.

Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.

Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Abstract: A voltage equal to the threshold value of a TFT (106) is held in capacitor unit (109). When a video signal is inputted from a source signal line, the voltage held in the capacitor unit is added thereto and a resultant signal is applied to a gate electrode of the TFT (106). Even when a threshold value is varied for each pixel, each threshold value is held in the capacitor unit (109) for each pixel. Thus, the influence of a variation in threshold value can be eliminated. Further, holding of the threshold value is conducted by only the capacitor unit (109) and a charge does not move at writing of a video signal so that a voltage between both electrodes is not changed. Thus, it is not influenced by a variation in capacitance value.

Abstract: A method for manufacturing a thin-film transistor, includes: preparing a substrate; forming a gate electrode above the substrate; forming a gate insulating layer above the gate electrode; forming a semiconductor film above the gate insulating layer; forming, above the semiconductor film, a protective layer comprising an organic material; forming a source electrode and a drain electrode above the protective layer; forming a semiconductor layer patterned, by performing dry etching on the semiconductor film; removing at least a portion of a region of an altered layer, the region contacting the semiconductor layer, the altered layer being a surface layer of the protective layer that is altered by the dry etching; and forming a passivation layer having a major component identical to a major component of the protective layer so as to contact the semiconductor layer in a region in which the altered layer has been removed.

Abstract: A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack that includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area, and doping the second portion of the doped semiconductor layer with a third doping dose.

Abstract: A substrate with two SiGe regions having different Germanium concentrations and a method for making the same. The method includes: providing a substrate with at least two active regions; epitaxially depositing a first SiGe layer over each active regions; epitaxially depositing a Silicon layer over each SiGe layer; epitaxially depositing a second SiGe layer over each Silicon layer; forming a hard mask over the second SiGe layer of one of the active regions; removing the epitaxially deposited second SiGe layer of the unmasked active region, removing the hard mask, and thermally mixing the remaining Silicon and SiGe layers of the active regions to form a new SiGe layer with uniform Germanium concentration for each of the active regions, where the new SiGe layer with uniform Germanium concentration of one of the at least two active regions has a different concentration of Germanium than the new SiGe layer with uniform Germanium concentration of the other SiGe layer.

Abstract: A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth.

Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.

Abstract: The semiconductor device has a semiconductor layer, a gate electrode which covers an end portion of the semiconductor layer, and an insulating layer for insulating the semiconductor layer and the gate electrode. The film thickness of the insulating layer which insulates a region where an end portion of the semiconductor layer and the gate electrode overlap each other is thicker than the film thickness of the insulating layer which covers the central portion of the semiconductor layer.

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.

Abstract: A semiconductor device and method of making the same are provided. The method of forming semiconductor device uses non-implant process to form doped layers, and thus is applicable for large-size display panel. The method of forming semiconductor device uses annealing process to reduce the resistance of the doped layers, which improves the electrical property of the semiconductor device. A first dielectric layer of the semiconductor device is able to protect a semiconductor layer disposed in a first region of the substrate from being damaged during the process, and an etching stop layer of the semiconductor device is able to protect the semiconductor layer disposed in a second region of the substrate from being damaged when defining second doped layers. The first dielectric layer and the etching stop layer are formed by the same patterned dielectric layer, thus no extra process is required, fabrication cost is reduced, and yield is increased.

Abstract: A semiconductor device having a semiconductor element (a thin film transistor, a thin film diode, a photoelectric conversion element of silicon PIN junction, or a silicon resistor element) which is light-weight, flexible (bendable), and thin as a whole is provided as well as a method of manufacturing the semiconductor device. In the present invention, the element is not formed on a plastic film. Instead, a flat board such as a substrate is used as a form, the space between the substrate (third substrate (17)) and a layer including the element (peeled layer (13)) is filled with coagulant (typically an adhesive) that serves as a second bonding member (16), and the substrate used as a form (third substrate (17)) is peeled off after the adhesive is coagulated to hold the layer including the element (peeled layer (13)) by the coagulated adhesive (second bonding member (16)) alone. In this way, the present invention achieves thinning of the film and reduction in weight.

Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.

Abstract: A photoresist composition, a method of forming a pattern using the photoresist composition, and a method of manufacturing a display substrate are disclosed. A photoresist composition includes an alkali-soluble resin, a quinone diazide-based compound, a multivalent phenol-based compound, and a solvent. Therefore, photosensitivity for light having a wavelength in a range of about 392 nm to about 417 nm may be improved, and reliability of forming a photo pattern and a thin film pattern using the photoresist composition may be improved.

Abstract: The present invention relates to a thin film transistor substrate and method for fabricating the same which can secure an alignment margin and reduce the number of mask steps. A thin transistor substrate according to the present invention includes a gate line and a data line crossing each other to define a pixel, a gate metal pattern under the data line, a thin film transistor having a gate electrode, a source electrode and a drain electrode in the pixel, and a pixel electrode connected to the drain electrode of the thin film transistor by a connection electrode, wherein the data line has a plurality of first slits to disconnect the gate metal pattern from the gate line.

Abstract: Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.

Abstract: A semiconductor device has a first element region, a second element region, and a first isolation region in a thin film region and a third element region, a fourth element region, and a second isolation region in a thick film region. It is manufactured with step (a) of providing a substrate having a silicon layer formed via an insulating layer, step (b) of forming element isolation insulating films in the silicon layer in the first isolation region and the second isolation region of the substrate step (c) of forming a hard mask in the thin film region, step (d) of forming silicon films over the silicon layer exposed from the hard mask in the third element region and the fourth element region, and step (e) of forming element isolation insulating films between the silicon films in the third element region and the fourth element region.

Abstract: A thin film transistor includes, on an insulating substrate, at least: a gate electrode; a gate insulating layer; a source electrode; a drain electrode; a metal oxide layer including a semiconductor region and an insulating region, each of the semiconductor region and the insulating region being composed of a same metal oxide material; and an insulating protective layer. The semiconductor region includes a region between the source electrode and the drain electrode, and is overlaid on a part of each of them. The semiconductor region is formed between the gate insulating layer and the insulating protective layer to abut on at least one of them. The electric conductivity of the semiconductor region is higher than that of the insulating region.

Abstract: An electronic device, such as a thin-film transistor, includes a semiconducting layer formed from a semiconductor composition. The semiconductor composition comprises a polymer binder and a small molecule semiconductor. The semiconducting layer has been deposited on an alignment layer that has been aligned in the direction between the source and drain electrodes. The resulting device has increased charge carrier mobility.

Abstract: Embodiments of the present invention disclose a thin film transistor array substrate, a manufacturing method thereof, and a display device. The thin film transistor array substrate comprises: an active pixel region and a wiring region, in which a conductive electrode is formed within the wiring region and the conductive electrode is grounded. The manufacturing method comprises: a thin film transistor array is formed within an active pixel region of a substrate; and a conductive electrode is formed within a wiring region located at the periphery of the active pixel region.

Abstract: A thin film transistor, an array substrate, and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer and an active layer sequentially on a substrate, and forming an active region through a patterning process; forming a gate insulating layer and a gate electrode sequentially; forming Ni deposition openings; forming a dielectric layer having source/drain contact holes in a one-to-one correspondence with the Ni deposition openings; and forming source/drain electrodes which are connected with the active region via the source/drain contact holes and the Ni deposition openings.

Abstract: Techniques are described to simultaneously form an isolation trench and a handle wafer contact without additional mask steps. In one or more implementations, an isolation trench and a handle wafer contact trench are simultaneously formed in a substrate. The substrate includes an insulating layer that defines a trench bottom of the handle wafer contact trench. A handle wafer is bonded to a bottom surface of the substrate. An oxide insulating layer is deposited in the isolation trench and the handle wafer contact trench. The oxide insulating layer is then etched so that the oxide insulating layer covering the trench bottom is at least partially removed. The trench bottom is then etched so that a top surface of the handle wafer is at least partially exposed. The handle wafer contact trench may then be at least partially filled with an electrical conductive material.

Abstract: A method for manufacturing fan-out lines on an array substrate is disclosed. The fan-out lines comprise an amorphous silicon layer, an ohmic contact layer and a source-drain electrode layer disposed on a gate insulating layer. The manufacturing processes can be conducted by forming a first layer of photoresist on the source-drain electrode layer and performing a half-exposure development process on the first layer of photoresist; etching the amorphous silicon layer, the ohmic contact layer and the source-drain electrode layer by an etching process; removing the first layer of photoresist; forming a second layer of photoresist and performing full-exposure development process on the second layer of photoresist; and etching the amorphous silicon layer by etching process to form the fan-out lines.

Abstract: A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region.

Abstract: A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of beryllium oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is single crystal beryllium oxide.

Abstract: A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

Abstract: An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.

Abstract: A method of manufacturing an epitaxial silicon wafer including a silicon wafer having a surface added with phosphorus and an epitaxial film provided on the surface includes adjusting an in-plane thickness distribution of the epitaxial film formed on the surface of the silicon wafer based on an in-plane resistivity distribution of the silicon wafer before an epitaxial growth treatment.