Abstract: A semiconductor device, and method of fabricating the device. The device including a plurality of vertical transistors, each vertical transistor having a raised semiconductor island having a first cross-sectional profile, a source-drain region disposed above the raised semiconductor island, the source-drain region having a second cross-sectional profile, and a semiconductor channel disposed above the source-drain region, the semiconductor channel having a third cross-sectional profile. The second cross-sectional profile is asymmetric.

Abstract: A layout structure of a standard cell using vertical nanowire (VNW) FETs is provided. A p-type transistor region in which VNW FETs are formed and an n-type transistor region in which VNW FETs are formed are provided between a power supply interconnect VDD and a power supply interconnect VSS. A local interconnect is placed across the p-type transistor region and the n-type transistor region. The top electrode of a transistor that is a dummy VNW FET is connected with the local interconnect.

Abstract: Methods and materials for growing TMD materials on substrates and making semiconductor devices are described. Metal contacts may be created prior to conducting a deposition process such as chemical vapor deposition (CVD) to grow a TMD material, such that the metal contacts serve as the seed/catalyst for TMD material growth. A method of making a semiconductor device may include conducting a lift-off lithography process on a substrate to produce a substrate having metal contacts deposited thereon in lithographically defined areas, and then growing a TMD material on the substrate by a deposition process to make a semiconductor device. Further described are semiconductor devices having a substrate with metal contacts deposited thereon in lithographically defined areas, and a TMD material on the substrate, where the TMD material is a continuous, substantially uniform monolayer film between and on the metal contacts, where the metal contacts are chemically bonded to the TMD material.

Abstract: A method is disclosed that includes operations as follows: after forming an ion-implanted layer disposed between an epitaxial layer and a first semiconductor substrate, bounding the epitaxial layer to a bonding oxide layer without forming any layer between the epitaxial layer and the bonding oxide layer; and removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping a remaining portion of the ion-implanted layer on the epitaxial layer.

Abstract: A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.

Abstract: A display device capable of reducing a non-display area includes a substrate including at least one hole area disposed within an emission area, and at least one blocking hole passing through inorganic insulating films disposed beneath a light emitting element while including upper and lower insulating films made of different materials. Side surfaces of the upper inorganic insulating film exposed through the blocking hole protrude beyond side surfaces of the lower inorganic insulating film exposed through the blocking hole, respectively. Accordingly, it is possible to minimize a bezel area, which is a non-display area, and to disconnect a light emitting stack by the blocking hole.

Abstract: A plasmonic field-enhanced photodetector is disclosed. The photodetector absorbs surface plasmon polaritons (SPPs) by using a light absorbing layer having a conduction band and a valence band in which an energy is split, the SPPs being generated by combining surface plasmons (SPs) with photons of a light wave, and generates photocurrent based on the absorbed SPPs.

Abstract: Semiconductor FET devices with bottom dielectric isolation and high-? first are provided. In one aspect, a semiconductor FET device includes: a substrate; at least one device stack including active layers oriented horizontally one on top of another on the substrate; source and drains alongside the active layers; and gates, offset from the source and drains by inner spacers, surrounding a portion of each of the active layers, wherein the gates include a gate dielectric that wraps around the active layers but is absent from sidewalls of the inner spacers. A method of forming a semiconductor FET device is also provided.

Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor.

Abstract: A thin-film transistor, method of manufacturing the same, and a display apparatus are provided. The thin-film transistor includes a first active layer, a source, a drain, a gate, and a second active layer, the source, the drain, the gate are disposed on the first active layer with spacing, the gate is located between the source and the drain, the second active layer is disposed on the gate, the source, and the drain, the source and the drain are both respectively connected to the first active layer and the second active layer, and the gate is respectively insulated from the first active layer, the second active layer, the source, and the drain. When a voltage is applied to the gate, the source and the drain may be conducting via the first and second active layer. Therefore, a larger current may flow between the source and the drain.

Abstract: A semiconductor device is provided. The device includes a plurality of transistor pairs that are stacked over a substrate. Each of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The device also includes a plurality of gate electrodes that are stacked over the substrate with a staircase configuration. The plurality of gate electrodes are electrically coupled to gate structures of the plurality of transistor pairs. The device further includes a plurality of source/drain (S/D) local interconnects that are stacked over the substrate with a staircase configuration. The plurality of S/D local interconnects are electrically coupled to source regions and drain regions of the plurality of transistor pairs.

Abstract: Micron scale tin oxide-based semiconductor devices are provided. Reactive-ion etching is used to produce a micron-scale electronic device using semiconductor films with tin oxides, such as barium stannate (BaSnO3). The electronic devices produced with this approach have high mobility, drain current, and on-off ratio without adversely affecting qualities of the tin oxide semiconductor, such as resistivity, electron or hole mobility, and surface roughness. In this manner, electronic devices, such as field-effect transistors (e.g., thin-film transistors (TFTs)), are produced having micron scale channel lengths and exhibiting complete depletion at room temperature.

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

Abstract: The present disclosure provides an LTPS type TFT and a method for manufacturing the same. The TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area.

Abstract: A semiconductor device and method for forming the semiconductor device are provided. A first layer is formed over a semiconductor layer, and a first patterned mask is formed over the first layer. A cyclic etch process is then performed to define a second patterned mask in the first layer. The cyclic etch process includes a first phase to form a polymer layer over the first patterned mask and a second phase to remove the polymer layer and to remove a portion of the first layer. A portion of the semiconductor layer is removed using the second patterned mask to define a fin from the semiconductor layer.

Abstract: A method of fabricating the vertical field effect transistor includes forming a dielectric layer on a metal semiconductor alloy layer that is present on a substrate of a semiconductor material. The dielectric layer is bonded to a supporting substrate. The substrate of the semiconductor material is cleaved, wherein a remaining portion of the semiconductor material provides a semiconductor surface layer in direct contact with the metal semiconductor alloy layer. A vertical fin type field effect transistor (FinFET) is formed atop the stack of the semiconductor surface layer, the metal semiconductor alloy layer, the dielectric layer and the supporting substrate, wherein the semiconductor surface layer provides at least one of a source region or a drain region of the FinFET and the metal semiconductor alloy provides a contact to the source region or the drain region of the FinFET.

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, and forming a sacrificial film over the first semiconductor layer and the second semiconductor layer. The sacrificial film fills an area between the first semiconductor layer and the second semiconductor layer. The method further includes forming a space in the sacrificial film between the first semiconductor layer and the second semiconductor layer and removing the sacrificial film.

Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.

Abstract: The present disclosure provides an LDD-free semiconductor structure including a semiconductor layer, a gate over the semiconductor layer and a regrowth region made of semiconductor material positioned in the semiconductor layer. The regrowth region forms a source region or a drain region of the LDD-free semiconductor structure. The gate includes a gate electrode layer laterally covered by a gate spacer. The regrowth region extends towards a region beneath the gate spacer and close to a plane extending along a junction of the gate spacer and the gate electrode layer. The present disclosure also provides a method for manufacturing an LDD-free semiconductor structure. The method includes forming a gate over a semiconductor layer, removing a portion of the semiconductor layer and obtaining a recess, and forming a regrowth region over the recess.

Abstract: A coating liquid for forming an oxide or oxynitride insulator film, the coating liquid including: A element; at least one selected from the group consisting of B element and C element; and a solvent, wherein the A element is at least one selected from the group consisting of Sc, Y, Ln (lanthanoid), Sb, Bi, and Te, the B element is at least one selected from the group consisting of Ga, Ti, Zr, and Hf, the C element is at least one selected from the group consisting of Group 2 elements in a periodic table, and the solvent includes at least one selected from the group consisting of an organic solvent having a flash point of 21° C. or more but less than 200° C. and water.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface and a back surface, at least one semiconductor device, a first TSV disposed in the substrate, an insulating layer surrounding the first TSV, a shielding layer surrounding the insulating layer, and a second TSV adjacent to the first TSV. The semiconductor device is disposed in a device region of the substrate. The first TSV is exposed by the front surface and the back surface of the substrate. The insulating layer includes an electrically insulating material. The shielding layer includes an electrically conductive material coupled to ground through a ground layer. The second TSV is exposed by the front surface and the back surface of the substrate.

Abstract: Display substrates and display devices with reduced electrical resistance are disclosed. One inventive aspect includes a switching device, a first wiring and a second wiring. The switching device includes a first semiconductor layer, first and second gate insulation layers, a source electrode and a drain electrode. The source and drain electrodes are formed to electrically connect, through the first and second gate insulation layers, to the first semiconductor layer. The second wiring is formed on the second gate insulation layer and electrically connected to the first wiring.

Abstract: The disclosure discloses a thin film transistor, a method for fabricating the same, an array substrate, and a display panel. The thin film transistor includes: a first conductive layer on a base substrate, a first insulation layer on a side of the first conductive layer facing away from the base substrate, and a second conductive layer on a side of the first insulation layer facing away from the first conductive layer, wherein an active layer is arranged on a side of the first insulation layer facing the first conductive layer, and/or a side thereof facing the second conductive layer.

Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.

Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

Abstract: A TFT array substrate, a fabrication method thereof and a LCD panel are provided. The TFT array substrate adopts the transparent silicon-based nanolines to form the semiconductor layer of the TFT, adopts the transparent material to form the gate electrode of the TFT, and has the pixel electrode covering the region occupied by the TFT, such that the illumination emitted by the backlight can pass through the whole TFT and the pixel electrode, i.e. the pixel portion occupied by the TFT 20 is also transparent, and thus the aperture ratio can be significantly increased to enhance transmittance and display effect of high PPI LCD panels.

Abstract: A method of forming a transistor from a stack of layers comprising at least one insulating layer topped by at least one active layer and at least one first and one second insulating trench defining in the active layer a reception area for receiving the transistor, the transistor comprising a conduction channel formed at least partially in the active layer, the method comprising at least the following steps: forming a grid stack extending over at least the conduction channel; forming a source zone and a drain zone; wherein the formation of the grid stack is carried out in such a way as to provide at least a first and a second portion of the reception zone, not covered by the grid stack.

Abstract: A method and apparatus, the method comprising: forming a layer of two dimensional material (23), in particular graphene, on a first release layer; forming, possibly a (gate) insulating layer (35), and at least two, preferably three, electrodes (25); forming a second release layer overlaying at least a portion of the layer of two dimensional material; providing a mouldable polymer (24, 26, 28) overlaying the at least two electrodes and the second release layer; and removing the first and second release layers to provide a cavity (29) between the mouldable polymer (26) and the layer of two dimensional material (23).

Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ? in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.

Abstract: A liquid crystal display apparatus including a gate driving circuit disposed on a liquid crystal display is provided. The apparatus further includes a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to data lines. The gate driving circuit includes a plurality of stages connected to one another in parallel. The odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal and the even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal.

Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.

Abstract: An embodiment of a method for manufacturing a semiconductor device includes: providing a monocrystalline semiconductor substrate having a first side; forming a plurality of recess structures in the semiconductor substrate at the first side; filling the recess structures with a dielectric material to form dielectric islands in the recess structures; forming a semiconductor layer on the first side of the semiconductor substrate to cover the dielectric islands; and subjecting the semiconductor layer to heat treatment and recrystallizing the semiconductor layer to form a recrystallized semiconductor layer, so that a crystal structure of the recrystallized semiconductor layer adapts to a crystal structure of the semiconductor substrate, and so that the semiconductor substrate and the semiconductor layer together form a compound wafer with the dielectric islands at least partially buried in the semiconductor material of the compound wafer.

Abstract: A technique relates to a semiconductor device. Fins are formed of varying concentrations of germanium. Gate material is formed on the fins. Source or drain (S/D) regions are adjacent to the fins, and transistor devices include the fins.

Abstract: An array of recessed access devices comprises islands comprising semiconductive material surrounded by insulating material. The insulating material has a bottom adjacent individual of the islands. Rows of transistor gate lines individually cross multiple of the islands within the semiconductive material and cross within the insulating material between the individual islands. Individual of the gate lines are operatively adjacent a channel region of individual of the transistors within the individual islands and interconnect the transistors in that row. The individual transistors comprise a pair of source/drain regions on opposite sides of the individual gate lines in the individual islands. A lower portion of the individual islands proximate individual of the bottoms of the insulating material has less horizontal area than an uppermost portion of the individual islands. Additional embodiments are disclosed.

Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.

Abstract: The present disclosure provides an LTPS type TFT and a method for manufacturing the same. The TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area.

Abstract: The invention provides an oxide semiconductor TFT and manufacturing method thereof. The oxide semiconductor TFT comprises: a substrate, a gate on the substrate, a gate insulating layer on the gate and substrate, an oxide semiconductor layer on the gate insulating layer, and a barrier layer on the semiconductor layer, and a source and a drain on the oxide semiconductor layer and gate insulating layer; the oxide semiconductor layer comprising: a channel region and two contact regions respectively located at two sides of the channel region, and the barrier layer being located on the channel region; the channel region comprising a plurality of channel strips spaced apart in a channel width direction, and the barrier layer comprising a plurality of barrier strips respectively corresponding to the plurality of channel strips. The invention can reduce power consumption of the oxide semiconductor TFT and improve and the stability in the winding state.

Abstract: An image sensor includes a plurality of pixels arranged in matrix, and each pixel includes a first TFT having a first gate electrode and a second gate electrode that are arranged on a substrate, a second TFT, and a photoelectric conversion element that has a first electrode electrically connected to a first surface of an a-Si thin film and the second gate electrode of the first TFT and a second electrode connected to a second control line, and that is arranged above the first TFT so as to be superposed on the first TFT in an laminated direction. Provided is a gas barrier film that is positioned between the first and the second TFTs and the photoelectric conversion element and that prevents hydrogen from permeating into the first and the second TFTs, the first electrode and the second gate electrode are constructed by the same layer, and the gas barrier film is not provided with an aperture in each of the pixels.

Abstract: A semiconductor device comprising a first field insulating film around at least a part of a first fin type pattern and at least a part of a second fin type pattern, a second field insulating film between the first fin type pattern and the second fin type pattern and protruding from the first field insulating film and a first gate structure which extends over the first and second field insulating films in a second direction intersecting with a first direction, and includes a first portion on the first field insulating film, and a second portion on the second field insulating film, wherein a first width of the first portion of the first gate structure is greater than a second width of the second portion of the first gate structure.

Abstract: A TFT, a method for fabricating the same, a display substrate, and a display device are disclosed. The TFT comprises a substrate, a gate, a gate insulating layer, semiconductor layer, a source, and a drain. The gate comprises a rough surface on a side facing the semiconductor layer. Since the surface of gate is uneven, the light which has been reflected on the surface of gate will no longer be reflected, or will be directly scattered to other directions. The incident light from the backlight source cannot impinge onto the semiconductor layer by continuous reflection. This reduces the possibility that the semiconductor layer is irradiated by light, and improves stability of TFT.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The manufacturing method includes: forming a light-shielding pattern layer, a buffer layer, an active layer, a gate insulating layer and a gate electrode on a base substrate, which are away from the base substrate in sequence; depositing an amorphous silicon (a-Si) film on the base substrate in a temperature range of 15-150° C.; forming a first interlayer dielectric (ILD) at least disposed above the active layer by patterning the a-Si film; forming through holes in the first ILD, through which a source contact region and a drain contact region of the active layer are exposed; and forming a source electrode and a drain electrode on the first ILD, which are respectively connected with the source contact region and the drain contact region via the through holes.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.

Abstract: There is provided an etching method which includes supplying an etching gas including an H2 gas or an NH3 gas to a target substrate having a germanium portion in an excited state; and etching the germanium portion.

Abstract: Provided is a substrate wiring path inspection system whereby, at the time of performing electrical inspection of a wiring path of a substrate having a surface on which a plurality of electrically independent wiring paths are formed, whether a probe is reliably electrically connected to the wiring path can be easily checked at a low equipment cost. The present invention is configured by being provided with: a probe set 2 to be in contact with end portions of a plurality of wiring paths 31-34 formed on a substrate 1; a flexible conductor 9 that short-circuits the wiring paths 31-34 at portions excluding the end portions; and an inspection device 4 which is provided with a determination section 8 that determines whether a resistance value between a pair of wiring lines is lower than a predetermined value, said pair of wiring lines having been selected from among the wiring lines 31-34 short-circuited by the flexible conductor 9.

Abstract: One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The method includes: providing a semiconductor structure, where the semiconductor structure includes: a semiconductor substrate, and a first active region located on the semiconductor substrate, the first active region including a first doped region and a second doped region abutting against the first doped region, and the second doped region being located at an upper surface of the first active region; forming a semiconductor layer on an upper surface of the second doped region; and forming a contact connected to the semiconductor layer. The present disclosure enables defects or damages caused when forming the contact to be kept away from a junction field formed by the second doped region and the first doped region. Therefore, leakage current may be reduced and device performances may be improved.