Abstract: An organic light emitting diode display device capable of improving capacitance Cst of a storage capacitor and transmittance and a method of fabricating the same are disclosed. The organic light emitting diode display device includes a driving thin film transistor (TFT) formed on the substrate, a passivation film formed to cover the TFT driver, a color filter formed on the passivation film in a luminescent region, a planarization film formed to cover the color filter, a transparent metal layer formed on the planarization film, an insulating film formed on the transparent metal layer, a first electrode connected to the TFT driver and overlapping the transparent metal layer while interposing the insulating film therebetween, an organic light emitting layer and a second electrode which are sequentially formed on the first electrode. The transparent metal layer, the insulating film, and the first electrode constitute a storage capacitor in the luminescent region.

Abstract: A TFT flat sensor comprises pixel units each comprising: a common electrode and a common electrode insulating layer on a substrate, wherein a first via hole is provided in the common electrode insulating layer at a location corresponding to the common electrode; a gate electrode on the common electrode insulating layer; a first conductive film layer on the common electrode and the gate electrode wherein the first conductive film layer contacts the common electrode through a first via hole; a gate insulating layer, an active layer, a drain electrode and a source electrode, a second conductive film layer, a protection layer and a third conductive film layer on the first conductive film layer; a second via hole is provided in the protection layer at a location corresponding to the source electrode through which the third conductive film layer contacts the source electrode.

Abstract: A thin film transistor array substrate including a first TFT including a first active layer, a gate electrode, a first source electrode and a first drain electrode, a second TFT including a second active layer, a floating gate electrode, a control gate electrode, a second source electrode, and a second drain electrode, a capacitor including a first electrode and a second electrode, and a capping layer contacting a portion of the first electrode, the capping layer and the second electrode being on a same layer, is disclosed. A method of manufacturing thin film transistor array substrate is also disclosed.

Abstract: In a semiconductor device in which transistors are formed in a plurality of layers to form a stack structure, a method for manufacturing the semiconductor device formed by controlling the threshold voltage of the transistors formed in the layers selectively is provided. Further, a method for manufacturing the semiconductor device by which oxygen supplying treatment is effectively performed is provided. First oxygen supplying treatment is performed on a first oxide semiconductor film including a first channel formation region of a transistor in the lower layer. Then, an interlayer insulating film including an opening which is formed so that the first channel formation region is exposed is formed over the first oxide semiconductor film and second oxygen supplying treatment is performed on a second oxide semiconductor film including a second channel formation region over the interlayer insulating film and the exposed first channel formation region.

Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.

Abstract: A method to construct a semiconductor device, the method including: forming a first layer including mono-crystallized semiconductor and first logic circuits; forming a second layer including a mono-crystallized semiconductor layer, the second layer overlying the first logic circuits; forming transistors on the second layer; forming connection paths from the second transistors to the first transistors, where the connection paths include a through layer via of less than 200 nm diameter; and connecting the first logic circuits to an external device using input/output (I/O) circuits, the input/output (I/O) circuits are constructed on the second mono-crystallized semiconductor layer.

Abstract: Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: A semiconductor device and method of making the same are provided. The method of forming semiconductor device uses non-implant process to form doped layers, and thus is applicable for large-size display panel. The method of forming semiconductor device uses annealing process to reduce the resistance of the doped layers, which improves the electrical property of the semiconductor device. A first dielectric layer of the semiconductor device is able to protect a semiconductor layer disposed in a first region of the substrate from being damaged during the process, and an etching stop layer of the semiconductor device is able to protect the semiconductor layer disposed in a second region of the substrate from being damaged when defining second doped layers. The first dielectric layer and the etching stop layer are formed by the same patterned dielectric layer, thus no extra process is required, fabrication cost is reduced, and yield is increased.

Abstract: MMIC circuits with thin film transistors are provided without the need of grinding and etching of the substrate after the fabrication of active and passive components. Furthermore, technology for active devices based on non-toxic compound semiconductors is provided. The success in the MMIC methods and structures without substrate grinding/etching and the use of semiconductors without toxic elements for active components will reduce manufacturing time, decrease economic cost and environmental burden. MMIC structures are provided where the requirements for die or chip attachment, alignment and wire bonding are eliminated completely or minimized. This will increase the reproducibility and reduce the manufacturing time for the MMIC circuits and modules.

Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.

Abstract: An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

Abstract: The present invention provides an anode connection structure of an organic light-emitting diode and a manufacture method thereof. The structure includes: a thin-film transistor (20) and an anode (40) of an organic light-emitting diode arrange don the thin-film transistor (20). The thin-film transistor (20) includes a low-temperature poly-silicon layer (24) formed on a substrate (22), a gate insulation layer (26) formed on the low-temperature poly-silicon layer (24), a gate formed on the gate insulation layer (26), a protection layer (27) formed on the gate, and a source/drain (28) formed on the protection layer (27). The anode (40) of the organic light-emitting diode is connected to the low-temperature poly-silicon layer (24).

Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.

Abstract: A pixel, a storage capacitor, and a method for forming the same. The storage capacitor formed on a substrate comprises a semiconductor layer, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer. The semiconductor layer is formed on the substrate wherein the semiconductor layer and the substrate are covered by the first dielectric layer. The first conductive layer is formed on a part of the first dielectric layer. The second dielectric layer is formed on the first conductive layer, and the lateral side of the stacking structure including the second dielectric layer and the first conductive layer has a taper shaped. The second conductive layer is formed on a part of the second dielectric layer.

Abstract: A method for fabricating a sensor, comprises: forming, on a base substrate, a pattern of a data line (31), a pattern of a drain electrode (34), a pattern of a source electrode (33), a pattern of a receive electrode (39), a pattern of a photodiode (40) and a pattern of a transparent electrode (41); forming a pattern of an ohmic layer by using a first patterning process; forming a pattern of an active layer by using a second patterning process; forming a pattern of a gate insulating layer by using a third patterning process; and forming a pattern of a gate line (30), a pattern of a gate electrode (38) and a pattern of a bias electrode (42) by using a fourth patterning process. Such a method can reduce the number of mask as well as the production cost and simplifies the production process, thereby significantly improves the production capacity and the defect-free rate.

Abstract: A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region.

Abstract: A method of manufacturing a thin film transistor (TFT) array substrate is disclosed. In one aspect, the method includes forming an active layer on a substrate, forming a first insulating layer on the substrate to cover the active layer, and forming a first gate electrode on the first insulating layer in an area corresponding to the active layer, doping the active layer with ion impurities, forming a second insulating layer on the first insulating layer to cover the first gate electrode, performing an annealing process on the active layer, forming a lower electrode of a capacitor on the second insulating layer, forming a third insulating layer on the second insulating layer to cover the lower electrode, wherein the third insulating layer has a dielectric constant that is greater than those of the first and second insulating layers, and forming an upper electrode of the capacitor on the third insulating layer.

Abstract: A method for fabricating a sensor includes: forming, on a base substrate, a pattern of a source electrode and a drain electrode, a pattern of a data line, a pattern of a receiving electrode, a pattern of a photodiode, and a pattern of a transparent electrode disposed by using a first patterning process; forming a pattern of an ohmic layer by using a second patterning process; forming a pattern of an active layer by using a third patterning process; forming a pattern of a gate insulating layer by using a fourth patterning process, wherein the gate insulating layer has a via hole above the transparent electrode; and forming a pattern of a gate electrode, a pattern of a gate line, and a pattern of a bias line connected to the transparent electrode via the via hole above the transparent electrode by using a fifth patterning process.

Abstract: After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.

Abstract: A method of manufacturing an organic light-emitting diode (OLED) display is disclosed. In one aspect, the method includes forming a color filter on a thin film transistor substrate, forming an organic planarization layer on the color filter, and performing a vacuum heat-treatment on the color filter and organic planarization layer. The method also includes forming a first electrode on the organic planarization layer, forming an organic light-emitting layer on the first electrode, and forming a second electrode on the organic light-emitting layer. The vacuum heat-treatment is performed at a temperature in the range of about 150° C. to about 300° C. under a pressure substantially equal to or lower than about 10?3 Torr before the organic light-emitting layer is formed.

Abstract: A semiconductor device includes: a capacitor including a first insulating film between a lower electrode and an upper electrode; and a first laminated structure including a second insulating film and a semiconductor film, the second insulating film and the semiconductor film being located between part or all of a rim of the lower electrode and the first insulating film.

Abstract: A display device includes a pixel area including pixels arranged in a matrix and having a horizontal resolution of 350 ppi or more and a color filter layer overlapping with the pixel area. The pixels each include a first transistor whose gate is electrically connected to a scan line and whose one of a source and a drain is electrically connected to a signal line; a second transistor whose gate is electrically connected to the other of the source and the drain of the first transistor and whose one of a source and a drain is electrically connected to a current-supplying line; and a light-emitting element electrically connected to the other of the source and the drain of the second transistor. The first and second transistors each have a channel formation region including a single crystal semiconductor.

Abstract: A method to fabricate a diode device includes providing a fin structure formed in a SOI layer. The fin structure has a sacrificial gate structure disposed on the fin structure between a first end of the fin structure and a second end of the fin structure. The method further includes depositing first doped semiconductor material on the first and second ends of the fin structure, where the first doped semiconductor material on the first end of the fin structure has one of the same doping polarity or an opposite doping polarity as the first doped semiconductor material on the second end of the fin structure. The method further includes removing the sacrificial gate structure to form a gap between the deposited first doped semiconductor material; depositing a second doped semiconductor material within the gap and forming first and second electrical contacts conductively connected to the first doped semiconductor material.

Abstract: A display panel is provided, which includes a transparent substrate, a first thin film transistor (TFT), a second TFT, a transparent bottom electrode, a capacitance layer, a transparent top electrode, an opposite substrate and a display medium layer. The transparent substrate has a display region and a peripheral region. The display region has sub-pixel regions, and at least one sub-pixel region at least includes a capacitance region and a transistor region. The first and the second TFTs are disposed on the transistor region of the transparent substrate. The transparent bottom electrode, the capacitance layer and the transparent top electrode are sequentially disposed on the capacitance region of transparent substrate, in which the transparent bottom electrode is connected to a source/drain electrode of the first TFT, and the transparent top electrode is connected to a source/drain electrode of the second TFT.

Abstract: A thin film transistor (TFT) substrate, an organic light-emitting display apparatus including the TFT substrate, and a method of manufacturing the TFT substrate that enable simple manufacturing processes and a decrease in the interference between a capacitor and other interconnections are disclosed. The TFT substrate may include a substrate, a TFT arranged on the substrate, the TFT including an active layer, a gate electrode, a source electrode, and a drain electrode, a pixel electrode electrically connected to one of the source electrode and the drain electrode, and a capacitor including a lower capacitor electrode and an upper capacitor electrode, the lower capacitor electrode formed from the same material as the active layer and arranged on the same layer as the active layer, and the upper capacitor electrode formed from the same material as the pixel electrode.

Abstract: A thin-film transistor (“TFT”) array substrate includes: a TFT including an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer disposed between the active layer and the gate electrode, and a second insulating layer disposed between the gate electrode, and the source and drain electrode; a pixel electrode including a transparent conductive oxide and disposed in an opening defined in the second insulating layer; a capacitor including a first electrode disposed on a layer on which the active layer is disposed, and a second electrode disposed on a layer on which the gate electrode is disposed; a pad electrode disposed on the second insulating layer and including a material substantially the same as a material in the source electrode and the drain electrode; a first protective layer disposed on the pad electrode; and a second protective layer disposed on the first protective layer.

Abstract: There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprising a support layer, a semiconductor structure portion formed on the support layer, and a resin film formed on the semiconductor structure portion. The resin film comprises an opening formed by a laser irradiation therein, and also an electroconductive member which is in contact with the surface of the semiconductor structure portion is disposed within the opening of the resin film.

Abstract: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.

Abstract: A method of manufacturing oxide thin film transistor and display device are provided. In the method of manufacturing an oxide thin film transistor, the method includes: forming an active layer of an oxide semiconductor on a substrate, and performing surface treatment with plasma for the active layer to permeate oxygen into the active layer.

Abstract: A method for manufacturing an active device array substrate includes providing a flexible substrate having a transistor region and a transparent region; forming a gate electrode on the transistor region; sequentially forming a dielectric layer and a semiconductor layer to cover the gate electrode and the flexible substrate; removing a part of the semiconductor layer to form a channel layer above the gate electrode and removing a thickness of the dielectric layer disposed on the transparent region, such that a portion of the dielectric layer on the gate electrode has a first thickness, and another portion of the dielectric layer on the transparent region has a second thickness less than the first thickness; respectively forming a source electrode and a drain electrode on opposite sides of the channel layer; and forming a pixel electrode electrically connected to the drain electrode.

Abstract: A TFT array panel and a manufacturing method thereof. The TFT array panel includes an insulation substrate, a plurality of gate lines, a plurality of first dummy wiring lines, a gate insulating layer, and a plurality of data lines. The insulation substrate has a display area for displaying an image and a peripheral area outside the display area. The plurality of gate lines are formed in the display area and in a portion of the peripheral area. The plurality of first dummy wiring lines are insulated from the gate lines and formed in the peripheral area. The gate insulating later is formed on the gate lines and the first dummy wiring lines, and has at least one contact hole exposing at least lateral end portions of the first dummy wiring lines.

Abstract: To provide a light-emitting element or a light-emitting device in which power is not consumed wastefully even if a short-circuit failure occurs. The present invention focuses on heat generated due to a short-circuit failure which occurs in a light-emitting element. A fusible alloy which is melted at temperature T2 by heat generated due to the short-circuit failure when the short-circuit failure occurs is used for at least one of a pair of electrodes in a light-emitting element, and a layer containing an organic composition which is melted at temperature T1 is formed on a surface of the electrode opposite to a surface facing the other electrode. The present inventors have reached a structure in which the temperature T2 is lower than temperature T3 at which the light-emitting element is damaged and the temperature T1 is lower than the temperature T2, and this structure can achieve the objects.

Abstract: At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.

Abstract: An array for an in-plane switching (IPS) mode liquid crystal display device includes a gate line formed on a substrate to extend in a first direction, a common line formed on the substrate to extend in the first direction, a data line formed to extend in a second direction, a thin film transistor formed at an intersection between the gate line and the data line, wherein the thin film transistor includes a gate line, a gate insulating layer, an active layer, a source electrode, and a drain electrode, a passivation film formed on the substrate including the thin film transistor, a pixel electrode formed on the passivation film located on a pixel region defined by the gate line and the data line, the pixel electrode being electrically connected to the drain electrode, a common electrode formed on the passivation film, and a common electrode connection line connected to the common electrode and the common line, wherein the common electrode connection line overlaps with the common line and the drain electrode.

Abstract: A method to construct a semiconductor device, the method including: forming a first mono-crystallized semiconductor layer; forming a second mono-crystallized semiconductor layer including mono-crystallized semiconductor transistors; where the second mono-crystallized semiconductor layer overlays the first mono-crystallized semiconductor layer, where the first mono-crystallized semiconductor layer includes an alignment mark and the transistors are aligned to the alignment mark, and where the first mono-crystallized semiconductor layer includes logic circuits, and connecting the logic circuits to an external device using input/output (I/O) circuits, where the input/output (I/O) circuits are constructed on the second mono-crystallized semiconductor layer.

Abstract: A MOSFET includes an active region formed on an SOI substrate. A buried well is formed in the active region. A drain region having the first conductivity type is formed in the active region and spaced laterally from a source region and the buried well. A body region is formed in the active region between the source and drain regions on the buried well, and a drift region is formed in the active region between the drain and body regions on at least a portion of the buried well. A shielding structure is formed proximate the upper surface of the active region, overlapping a gate. During conduction, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes the drift region. The MOSFET is configured to sustain a linear mode of operation of an inversion channel formed under the gate.

Abstract: A particular device includes a replica circuit disposed above a dielectric substrate. The replica circuit includes a thin film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The device further includes a transformer disposed above the dielectric substrate and coupled to the replica circuit. The transformer is configured facilitate an impedance match between the replica circuit and an antenna.

Abstract: An organic light emitting display device includes a substrate having transmitting and pixel regions, the pixel regions being separated by the transmitting regions, at least one thin film transistor in each of the pixel regions, a plurality of transparent first conductive lines electrically connected to the thin film transistors and extending across the transmitting regions, a plurality of second conductive lines electrically connected to the thin film transistors and extending across the transmitting regions, a passivation layer, a plurality of pixel electrodes on the passivation layer, the pixel electrodes being separated and positioned to correspond to respective pixel regions, each of the pixel electrodes being electrically connected to and overlapping a corresponding thin film transistor, an opposite electrode overlapping the pixel electrodes in the transmitting and pixel regions, and an organic emission layer between the pixel electrodes and the opposite electrode.

Abstract: A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device.

Abstract: An organic light-emitting display device includes a capacitor lower electrode that includes a semiconductor material doped with ion impurities. A first insulating layer covers an active layer and the capacitor lower electrode. A gate electrode includes a gate lower electrode formed of a transparent conductive material and a gate upper electrode formed of metal. A pixel electrode is electrically connected to the thin film transistor. A capacitor upper electrode is at the same level as the pixel electrode. An etch block layer is formed between the first insulating layer and the capacitor upper electrode. Source and drain electrodes are electrically connected to the active layer. A second insulating layer has an opening completely exposing the capacitor upper electrode. A third insulating layer exposes the pixel electrode. An intermediate layer includes an emissive layer. An opposite electrode faces the pixel electrode.

Abstract: The present disclosure relates to a radio frequency (RF) switch that includes multiple body-contacted field effect transistor (FET) elements coupled in series. The FET elements may be formed using a thin-film semiconductor device layer, which is part of a thin-film semiconductor die. Conduction paths between the FET elements through the thin-film semiconductor device layer and through a substrate of the thin-film semiconductor die may be substantially eliminated by using insulating materials. Elimination of the conduction paths allows an RF signal across the RF switch to be divided across the series coupled FET elements, such that each FET element is subjected to only a portion of the RF signal. Further, each FET element is body-contacted and may receive reverse body biasing when the RF switch is in an OFF state, thereby reducing an OFF state drain-to-source capacitance of each FET element.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

Abstract: The present invention provides a manufacturing method of array substrate, which comprises: substrate; source, drain, driving electrode, and first capacitance electrode being formed on substrate; a first dielectric layer being formed to cover source, drain, driving electrode, and first capacitance electrode; first dielectric layer comprising first section covering first capacitance and second section covering the driving electrode; second section being thicker than first section; second capacitance electrode being formed on the first section of the first dielectric layer; first capacitor being formed with second capacitance electrode, first capacitance electrode, and first dielectric layer in between. Through this invention, the glue sealing of display device with present invention of array substrate is more effective.

Abstract: Provided is a method of manufacturing a capacitor of a display apparatus, the display apparatus being formed on a substrate and including a thin film transistor, which includes an active layer, a gate electrode, and source and drain electrodes, a display device connected to the thin film transistor, and the capacitor, the method including: forming an electrode layer on the substrate; forming a passivation layer on the electrode layer; patterning the passivation layer to form a first pattern including first branch patterns parallel to each other, and a second pattern including second branch patterns parallel to each other and interposed between the first branch patterns; and forming first and second electrodes by etching the electrode layer using the first and second patterns as masks.

Abstract: A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.

Abstract: A thin-film transistor (TFT) array substrate comprises: a substrate; an active layer and a capacitor first electrode formed on the substrate; a gate insulating film formed on the substrate, the active layer and the capacitor first electrode; a gate electrode formed on the gate insulating film corresponding to the active layer and a capacitor second electrode formed on the gate insulating film corresponding to the capacitor first electrode; an interlayer insulating film formed on the gate insulating film, the gate electrode, and the capacitor second electrode; and a pixel electrode, a source electrode, and a drain electrode formed on the interlayer insulating film; wherein at least one of the source electrode and the drain electrode is formed on the pixel electrode. A method of fabricating the TFT array substrate is also disclosed.

Abstract: Embodiments of the present invention disclose an array substrate comprising a peripheral wiring area which comprises an electrostatic discharge prevention area. The electrostatic discharge prevention area comprises a substrate on which a gate line, a gate insulating layer, a data line, a protection layer and a transparent electrode are formed. A first through hole is formed in the gate insulating layer, a second through hole is formed at the position of the protection layer corresponding to the first through hole, and the gate line, the data line and the transparent electrode are connected together through the first through hole and the second through hole. The present invention also discloses a manufacturing method of the array substrate.