Abstract: The invention relates to a method for forming a pattern on a substrate (S) with an upper surface and a lower surface which comprises the steps of depositing a first layer (E1) of an opaque material on the upper surface of the substrate (S), depositing a photosensitive layer (R) such that part of the photosensitive layer (R) covers at least part of the first layer (E1), exposing the photosensitive layer (R) to a light beam (L), the light beam (L) impinging on the lower surface of the substrate (S) under an oblique angle (?) of incidence, removing the exposed region of the photosensitive layer (R), depositing a second layer (E2) of an opaque material such that part of the second layer (E2) covers a remaining region of the photosensitive layer (R), and removing at least a part of the remaining region of the photosensitive layer (R).

Abstract: The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first wiring layer and a second wiring layer which are over the gate insulating film and whose end portions overlap with the gate electrode; and an oxide semiconductor layer which is over the gate electrode and in contact with the gate insulating film and the end portions of the first wiring layer and the second wiring layer. The gate electrode of the non-linear element and a scan line or a signal line is included in a wiring, the first or second wiring layer of the non-linear element is directly connected to the wiring so as to apply the potential of the gate electrode.

Abstract: The present invention provides methods for manufacturing a thin film transistor (TFT) array substrate and a display panel.

Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.

Abstract: A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer.

Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits.

Abstract: In a method of manufacturing a display device, a first insulating layer is formed on a semiconductor pattern. Ions of a first concentration are injected into source and drain domains of the semiconductor pattern and a lower electrode of the semiconductor pattern by using a mask pattern that selectively overlaps a channel domain of the semiconductor pattern and is positioned on the top of the first insulating layer. The mask pattern is removed. An ion injection process of injecting ions of a second concentration lower than the first concentration into the semiconductor pattern of the channel domain is directly performed in the first insulating layer. A gate electrode that overlaps the channel domain is formed on the top of the first insulating layer. An upper electrode that overlaps the lower electrode is formed on the top of the first insulating layer.

Abstract: A manufacturing method of thin film transistor substrate of a liquid crystal display panel includes following steps. A substrate is provided. Then, a transparent conducting layer and an opaque conducting layer are formed on the substrate. Thereafter, the transparent conducting layer and the opaque conducting layer are patterned by a gray-tone mask to form at least one storage capacitor electrode. Next, a first insulating layer is formed on the storage capacitor electrode. Then, at least one gate electrode is formed on the substrate. Subsequently, at least one gate insulating layer, a patterned semiconductor layer, a source electrode, a drain electrode, and a second insulating layer are formed sequentially on the gate electrode. Moreover, at least one pixel electrode is formed on the first insulating layer and the second insulating layer. A part of the pixel electrode overlaps a part of the storage capacitor electrode to form a storage capacitor.

Abstract: An array substrate and method for manufacturing the same is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased.

Abstract: A display panel includes a gate line dividing a pixel region into a first region and a second region and including a gate electrode, a data line crossing the gate line and including a source electrode, a thin film transistor connected to the gate line and the data line and including the gate electrode, the source electrode, and a drain electrode facing the source electrode, a protective layer disposed on the thin film transistor and comprising a first contact hole and a second contact hole, and first and second sub-pixel electrodes disposed on the first and second regions of the divided pixel region, respectively. The drain electrode is directly connected to the first sub-pixel electrode through the first contact hole, and the drain electrode is directly connected to the second sub-pixel electrode through the second contact hole.

Abstract: An object is to improve the aperture ratio of a semiconductor device. The semiconductor device includes a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit includes a channel-etched thin film transistor for driver circuit and a driver circuit wiring formed using metal. Source and drain electrodes of the thin film transistor for the driver circuit are formed using a metal. A channel layer of the thin film transistor for the driver circuit is formed using an oxide semiconductor. The display portion includes a bottom-contact thin film transistor for a pixel and a display portion wiring formed using an oxide conductor. Source and drain electrode layers of the thin film transistor for the pixel are formed using an oxide conductor. A semiconductor layer of the thin film transistor for the pixel is formed using an oxide semiconductor.

Abstract: A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes.

Abstract: A fabricating method for a pixel structure is provided. First, a substrate having an active device and a capacitor electrode line thereon is provided. Next, a passivation layer is formed on the substrate to cover the active device. After that, a light shielding layer is formed on the passivation layer to define a unit area. Next, an ink-jet printing is performed to form a color filter pattern within the unit area defined by the light shielding layer. After that, a portion of the color filter pattern is removed to form a first hole above active device. Next, the passivation layer exposed by the first hole is removed so as to form a contact hole exposing a portion of the active device. After that, a pixel electrode is formed on the color filter pattern to fill into the contact hole so as to electrically connect with active device.

Abstract: An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.

Abstract: A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on a part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on a part of the passivation layer and is electrically connected to the transistor through the second opening. The first storage capacitor is formed by the third conductive layer, the passivation layer, and the second conductive layer.

Abstract: An organic light emitting diode display and a method of manufacturing the display, the organic light emitting diode display including: a substrate; a semiconductor layer formed on the substrate, having a channel region, a source region, and a drain region; a gate insulating layer covering the semiconductor layer; a gate electrode formed on the channel region; and an interlayer insulating layer covering the gate electrode. Source and drain electrodes are formed on the interlayer insulating layer, and are connected to the source and drain regions, respectively. A pixel electrode extends from the drain electrode, in the same plane as the source and drain electrodes. The source and drain electrodes each have a first conductive layer formed of a transparent conductive material, and a metallic second conductive layer formed on the first conductive layer. The pixel electrode is formed from the first conductive layer.

Abstract: Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.

Abstract: A thin-film transistor (TFT) array substrate comprises: a substrate; an active layer and a capacitor first electrode formed on the substrate; a gate insulating film formed on the substrate, the active layer and the capacitor first electrode; a gate electrode formed on the gate insulating film corresponding to the active layer and a capacitor second electrode formed on the gate insulating film corresponding to the capacitor first electrode; an interlayer insulating film formed on the gate insulating film, the gate electrode, and the capacitor second electrode; and a pixel electrode, a source electrode, and a drain electrode formed on the interlayer insulating film; wherein at least one of the source electrode and the drain electrode is formed on the pixel electrode. A method of fabricating the TFT array substrate is also disclosed.

Abstract: An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.

Abstract: A thin film transistor having a crystalline silicon film that is formed over an insulating substrate with a gate electrode and a gate insulating film in between, and has a channel region in a region corresponding to the gate electrode; an insulating channel protective film that is selectively formed in a region corresponding to the channel region on the crystalline silicon film; an n+ silicon film having a source region and a drain region that sandwich a region corresponding to the channel region on the channel protective film and the crystalline silicon film; and a metal film having a source electrode and a drain electrode that respectively correspond to the source region and the drain region.

Abstract: In an organic light-emitting display having superior image quality and device reliability, and a related method of manufacturing the organic light-emitting display, the organic light-emitting display comprises: a gate electrode formed on a substrate; an interlayer insulating film formed on the substrate so as to cover the gate electrode; and a transparent electrode formed on the interlayer insulating film. The interlayer insulating film comprises multiple layers having different refractive indices.

Abstract: Lift-off method and half-tone photolithography are used to fabricate LCD TFT array plate. Only two photo masks are used to respectively define a first and a second metal layers to accomplish the LCD TFT array plate.

Abstract: A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.

Abstract: At least two TFTs which are connected with a light emitting element are provided, crystallinities of semiconductor regions composing active layers of the respective TFTs are made different from each other. As the semiconductor region, a region obtained by crystallizing an amorphous semiconductor film by laser annealing is applied. In order to change the crystallinity, a method of changing a scan direction of a continuous oscillating laser beam so that crystal growth directions are made different from each other is applied. Alternatively, a method of changing a channel length direction of TFT between the respective semiconductor regions without changing the scan direction of the continuous oscillating laser beam so that a crystal growth direction and a current flowing direction are different from each other is applied.

Abstract: Provided are an organic semiconductor structure and a method of manufacturing the same, an organic thin film transistor (OTFT) using the organic semiconductor structure and a method of manufacturing the OTFT, and a display apparatus using the same.

Abstract: A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.

Abstract: A semiconductor device includes: diffusion layers formed at the front surface of a substrate; low-resistance parts formed at the front surfaces of the diffusion layers so as to have resistance lower than the diffusion layer; and rear contact electrodes passing through the substrate from the rear surface of the substrate to be connected to the low-resistance parts through the diffusion layers.

Abstract: This invention is related to a thin film transistor (TFT) array and method of making same, for use in an active matrix liquid crystal display (AMLCD) having a high pixel aperture ratio. The TFT array and corresponding display are made by forming the TFTs and corresponding address lines on a substrate, coating the address lines and TFTs with a photo-imageable insulating layer which acts as a negative resist, exposing portions of the insulating layer with UV light which are to remain on the substrate, removing non-exposed areas of the insulating layer so as to form contact vias, and depositing pixel electrodes on the substrate over the insulating layer so that the pixel electrodes contact respective TFT source electrodes through the contact vias. The resulting display has an increased pixel aperture ratio because the pixel electrodes are formed over the insulating layer so as to overlap portions of the array address lines.

Abstract: A method is provided for fabricating a microelectronic device and a resistor on a substrate. The method can include forming device regions in a monocrystalline semiconductor region of a substrate, in which the device regions have edges defined according to a first semiconductor feature overlying a major surface of the semiconductor region. A dielectric region is formed having a planarized surface overlying the semiconductor region and overlying a second semiconductor feature disposed above a surface of an isolation region in the substrate. The surface of the isolation region can be disposed below the major surface. The method can further include removing at least a portion of the first semiconductor feature exposed at the planarized surface of the dielectric region to form an opening and forming a gate at least partially within the opening.

Abstract: A method for manufacturing an array substrate is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased.

Abstract: An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

Abstract: The present invention provides a vapor deposition method and a vapor deposition system of film formation systems by which EL materials can be used more efficiently and EL materials having superior uniformity with high throughput rate are formed. According to the present invention, inside a film formation chamber, an evaporation source holder in a rectangular shape in which a plurality of containers sealing evaporation material is moved at a certain pitch to a substrate and the evaporation material is vapor deposited on the substrate. Further, a longitudinal direction of an evaporation source holder in a rectangular shape may be oblique to one side of a substrate, while the evaporation source holder is being moved. Furthermore, it is preferable that a movement direction of an evaporation source holder during vapor deposition be different from a scanning direction of a laser beam while a TFT is formed.

Abstract: A method of forming a display device including source/drain electrodes on a substrate, a pixel electrode, an insulating partition wall layer, a channel-region semiconductor layer. The source/drain electrodes and the pixel electrode are formed on the substrate and in contact with each other. The insulating partition wall layer is formed on the substrate and provided with a first opening extending to between the source electrode and the drain electrode and a second opening formed on the pixel electrode and extending to the pixel electrode. The channel-region semiconductor layer is formed on the bottom of the first opening. The insulating film is formed on the partition wall layer so as to cover the first opening including the channel-region semiconductor layer. The oriented film covers the first opening from above the insulating film and the second opening from the pixel electrode.

Abstract: A semiconductor device includes a semiconductor layer on an insulating layer, and a first partially depleted transistor and a first diode in the semiconductor layer. The first transistor has a first gate electrode above the semiconductor layer via an insulating film and a first source or drain of a first conductivity type in the semiconductor layer below both sides of the gate electrode. The first diode has a first impurity layer of a second conductivity type in a shallow portion of the semiconductor layer and a second impurity layer of the first conductivity type in a deep portion of the semiconductor layer. The first and second impurity layers are stacked in a depth direction of the semiconductor layer. The side surfaces of the first and second impurity layers contact the semiconductor layer just below the first gate electrode.

Abstract: A method for forming a pixel of an electroluminescence device includes providing a substrate; defining at least a first area for capacitors and a second area for a transistor on the substrate; forming a first conductive layer over the first area; forming a first dielectric layer over the first conductive layer; forming a second conductive layer over the first dielectric layer; forming a second dielectric layer over the second conductive layer; forming a third conductive layer over the second dielectric layer; forming a layer of capping silicon nitride between the second dielectric layer and the third conductive layer; forming a semiconductor layer over the second area; forming a gate oxide layer over the second area; and forming a fourth conductive layer over the gate oxide layer.

Abstract: A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.

Abstract: A method for fabricating an active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is formed on the display area of the substrate. A gate insulator is formed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are formed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then formed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is formed on the passivation layer.

Abstract: A conductive shield covering a semiconductor integrated circuit prevents electrostatic breakdown of the semiconductor integrated circuit (e.g., malfunction of a circuit and damage to a semiconductor element) due to electrostatic discharge. Further, with use of a pair of insulators between which the semiconductor integrated circuit is sandwiched, a highly reliable semiconductor having resistance can be provided while achieving reduction in the thickness and size. Moreover, also in the manufacturing process, external stress, or defective shapes or deterioration in characteristics resulted from electrostatic discharge are prevented, and thus the semiconductor device can be manufactured with high yield.

Abstract: A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

Abstract: A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.

Abstract: Provided are a method of manufacturing a thin film transistor (TFT) substrate and a method of manufacturing an organic light emitting display apparatus, which increase the capacitance of a capacitor without increasing the probability of short circuits between wires. The method of manufacturing a TFT substrate includes (a) forming a capacitor electrode and a gate electrode on a substrate having a first region and a second region, so that the capacitor electrode is formed to correspond to the first region and the gate electrode is formed in a portion of the second region; (b) forming an interlayer insulating layer to cover the gate electrode and the capacitor electrode; and (c) etching a portion of the interlayer insulating layer in the first region by using a halftone mask to a thickness that is less than a thickness of a portion of the interlayer insulating layer in the second region.

Abstract: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.

Abstract: A thin film transistor (TFT) array substrate and a method of manufacturing the same that is capable of decreasing the number of usage of exposure masks to reduce the process time and the process costs and excessively etching a passivation film below a photoresist pattern to easily perform a lift-off process of the photoresist pattern are disclosed.

Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

Abstract: A flat panel display apparatus including a gate electrode on a substrate, a first insulating layer and a semiconductor layer sequentially stacked on the gate electrode and including a transparent conductive oxide, a capacitor first electrode extending on a plane on which the gate electrode extends, and a capacitor second electrode extending on a plane on which the semiconductor layer extends and including a material of the semiconductor layer, wherein the first insulating layer is between the capacitor second electrode and the semiconductor layer, source and drain electrodes that are separated by a second insulating layer and are connected to the semiconductor layer and the capacitor second electrode, a third insulating layer covering the source and drain electrodes, and a pixel electrode electrically connected to the source or drain electrode on the third insulating layer and being electrically connected to one of the source electrode and/or the drain electrode.

Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions.

Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

Abstract: Disclosed is a method of fabricating a liquid crystal display (LCD) device in which a photosensitive film is selectively patterned using a half-tone mask, and then a portion of a passivation layer at a pixel area is selectively removed to secure an penetration path of a stripper. Additionally, a crack is generated on a conductive film formed on a photosensitive film pattern through a predetermined heat treatment to facilitate a lift-off process. Thus, the number of masks can be reduced to simplify the fabrication process of the LCD device and reduce fabrication costs.

Abstract: A thin film transistor array substrate device includes a gate line formed on a substrate, a data line crossing the gate line with a gate insulating pattern position therebetween, a thin film transistor at a crossing of the gate line and the data line, a pixel electrode formed at a pixel region defined by the crossing of the gate line and the data line and connected to the thin film transistor, a gate pad part having a lower gate pad electrode connected to the gate line and an upper gate pad electrode connected to the lower gate pad electrode, a data pad part having a lower data pad electrode connected to the date line and an upper data pad electrode connected to the lower data pad electrode, and a passivation film pattern formed at a region besides the region including the pixel electrode, the upper data pad electrode, and the upper gate pad electrode, wherein the pixel electrode is formed on the gate insulating pattern of the pixel region exposed by the passivation film pattern.