Including Forming Gate Electrode As Conductive Sidewall Spacer To Another Electrode Patents (Class 438/267)
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Patent number: 8017991Abstract: Example embodiments provide a non-volatile memory device with increased integration and methods of operating and fabricating the same. A non-volatile memory device may include a plurality of first storage node films and a plurality of first control gate electrodes on a semiconductor substrate. A plurality of second storage node films and a plurality of second control gate electrodes may be recessed into the semiconductor substrate between two adjacent first control gate electrodes and below the bottom of the plurality of first control gate electrodes. A plurality of bit line regions may be on the semiconductor substrate and each may extend across the plurality of first control gate electrodes and the plurality of second control gate electrodes.Type: GrantFiled: March 15, 2007Date of Patent: September 13, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Won-joo Kim, Suk-pil Kim, Yoon-dong Park, June-mo Koo
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Patent number: 8017477Abstract: A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes. The second control gate electrodes are disposed on the semiconductor substrate over the first control gate electrodes. The first storage node films are disposed between the semiconductor substrate and the first control gate electrodes. The second storage node films are disposed between the semiconductor substrate and the second control gate electrodes. A method of fabricating the nonvolatile memory device includes forming the first storage node films, forming the first control gate electrodes, forming the second storage node films, and forming the second control gate electrodes.Type: GrantFiled: February 9, 2007Date of Patent: September 13, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Won-joo Kim, Suk-pil Kim, Yoon-dong Park
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Patent number: 8003463Abstract: A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The method of manufacturing the multi-work function metal gate structure comprises forming a first type of metal with a first work function in a central region and forming a second type of metal with a second work function in at least one edge region adjacent the central region. The first work-function is different from the second work function.Type: GrantFiled: August 15, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7977191Abstract: A method of forming a flash memory device includes forming a plurality of memory gates over a semiconductor substrate, forming an oxide film over the uppermost surface and sidewalls of the memory gates and then forming a plurality of selective gates on sidewalls of each of the memory gates.Type: GrantFiled: December 27, 2009Date of Patent: July 12, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Ki-Jun Yun
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Patent number: 7973357Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.Type: GrantFiled: December 18, 2008Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Suk Kim, Sun-Il Shim, Chang-Seok Kang, Won-Cheol Jeong, Jung-Dal Choi, Jae-Kwan Park, Seung-Hyun Lim, Sun-Jung Kim
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Patent number: 7973356Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a first gate electrode formed on the semiconductor substrate through a gate insulating film; a second gate electrode formed in a side direction of the first gate electrode and electrically insulated from the first gate electrode; and an insulating film formed at least between the semiconductor substrate and the second gate electrode to trap electric charge, as an electric charge trapping film. The first gate electrode comprises a lower portion contacting the gate insulating film and an upper portion above the lower portion of the first gate electrode, and a distance between the upper portion of the first gate electrode and the second gate electrode is longer than a distance between the lower portion of the first gate electrode and the second gate electrode.Type: GrantFiled: September 30, 2008Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventor: Takeshi Kikuchi
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Patent number: 7968405Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.Type: GrantFiled: February 6, 2008Date of Patent: June 28, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Mi Hong, Kwang-Tae Kim, Ji-Hoon Park
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Patent number: 7943453Abstract: A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.Type: GrantFiled: December 20, 2007Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Bernd Ernst Eduard Kastenmeier, Byoung Hun Lee, Naim Moumen, Theodorus Eduardus Standaert
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Patent number: 7939407Abstract: Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.Type: GrantFiled: November 9, 2009Date of Patent: May 10, 2011Assignee: SanDisk CorporationInventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, James Kai
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Patent number: 7927951Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.Type: GrantFiled: November 30, 2010Date of Patent: April 19, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Whan Kim, Kae-Dal Kwack, Sang-Su Park
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Patent number: 7923327Abstract: Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device comprises: a control gate region formed by doping a semiconductor substrate with second impurities; an electron injection region formed by doping the semiconductor substrate with first impurities, where a top surface of the electron injection region includes a tip portion at an edge; a floating gate electrode covering at least a portion of the control gate region and the tip portion of the electron injection region; a first tunnel oxide layer interposed between the floating gate electrode and the control gate region; a second tunnel oxide layer interposed between the floating gate electrode and the electron injection region; a trench surrounding the electron injection region in the semiconductor substrate; and a device isolation layer pattern filled in the trench.Type: GrantFiled: June 24, 2008Date of Patent: April 12, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Sung Kun Park
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Patent number: 7915123Abstract: A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.Type: GrantFiled: April 20, 2006Date of Patent: March 29, 2011Assignee: Spansion LLCInventors: Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Amol Joshi, Kyunghoon Min, Chi Chang
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Patent number: 7902024Abstract: A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.Type: GrantFiled: September 7, 2007Date of Patent: March 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Se-Hoon Lee, Donghoon Jang, Jong Jin Lee, Jeong-Dong Choe
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Patent number: 7892943Abstract: A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.Type: GrantFiled: December 21, 2007Date of Patent: February 22, 2011Assignee: Micron Technology, Inc.Inventor: Michael Violette
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Patent number: 7888203Abstract: Nonvolatile memory devices and methods of making the same are described. A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor.Type: GrantFiled: February 27, 2006Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Lee, Jung-Dal Choi
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Patent number: 7888211Abstract: A method of manufacturing a flash memory device includes preparing a semiconductor substrate comprising a cell area and a peripheral area, forming a first well and an oxide-nitride-oxide (ONO) layer in the cell area, forming a second well in the peripheral area of the semiconductor substrate comprising the first well and forming a first oxide layer in the peripheral area, forming a first polysilicon layer over the ONO layer and the first oxide layer and performing a first etch process to form a memory gate comprising an ONO layer pattern and a first polysilicon pattern in the cell area, forming a second oxide layer pattern and a second polysilicon pattern over either sidewall of the memory gate and forming a gate in the peripheral area, performing a third etch process so that the second oxide layer pattern and the second polysilicon pattern remain over only the one sidewall of the memory gate to form a select gate, and forming a first impurity area in the semiconductor substrate between the memory gates adjacType: GrantFiled: August 20, 2009Date of Patent: February 15, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Cheon-Man Shim
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Patent number: 7863673Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.Type: GrantFiled: February 13, 2009Date of Patent: January 4, 2011Assignees: Samsung Electronics Co., Ltd., Industry-University Cooperation Foundation, Hanyang-UniversityInventors: Tae-Whan Kim, Kae-Dal Kwack, Sang-Su Park
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Patent number: 7859041Abstract: A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a side of the first gate conductive film, a plurality of trenches formed between the gates, a second gate oxide film formed on an interior wall of each trench; and a second conductive film formed in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film and the thermal oxide film.Type: GrantFiled: June 16, 2009Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventors: Young Bog Kim, Jun Soo Chang, Min Yong Lee, Yong Seok Eun
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Patent number: 7855135Abstract: A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.Type: GrantFiled: August 12, 2009Date of Patent: December 21, 2010Assignee: International Business Machines CorporationInventors: Leland Chang, Isaac Lauer, Renee T. Mo, Jeffrey W. Sleight
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Patent number: 7855114Abstract: A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.Type: GrantFiled: January 9, 2009Date of Patent: December 21, 2010Assignee: Spansion LLCInventors: Wei Zheng, Mark Randolph, Hidehiko Shiraiwa
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Patent number: 7855410Abstract: According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.Type: GrantFiled: July 7, 2008Date of Patent: December 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jin Yang, Jeong-Uk Han, Yong-Suk Choi, Hyok-Ki Kwon, Bae-Seong Kwon
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Patent number: 7851846Abstract: A memory device, and method of making the same, in which a trench is formed into the surface of a semiconductor substrate. Source and drain regions define a channel region there between. The drain is formed under the trench. The channel region includes a first portion that extends along a bottom wall of the trench, a second portion that extends along a sidewall of the trench, and a third portion that extends along the surface of the substrate. The floating gate is disposed over the channel region third portion. The control gate is disposed over the floating gate. The select gate is at least partially disposed in the trench and adjacent to the channel region first and second portions. The erase gate disposed adjacent to and insulated from the floating gate.Type: GrantFiled: December 3, 2008Date of Patent: December 14, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Nhan Do, Hieu V. Tran, Amitay Levi
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Patent number: 7843007Abstract: A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.Type: GrantFiled: August 12, 2009Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Leland Chang, Isaac Lauer, Renee T. Mo, Jeffrey W. Sleight
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Patent number: 7838203Abstract: A system and method are disclosed for increasing retention reliability of a floating gate of a CMOS compatible memory cell. A mask structure is formed with a plurality of apertures near the edges of the mask structure. The size of the apertures is less than a resolution limitation of a photo exposure system. The mask structure is placed over a resist material and the resist material is exposed to light through the apertures of the mask structure. Zero order diffraction light passes though the apertures and imparts energy to the exposed portions of the resist material. A develop process is then used to remove portions of the resist material to form a sloped edge resist pattern. A sloped edge floating gate that is formed from the pattern facilitates the deposition of a thicker oxide layer at the sloped edge of the floating gate and reduces backend leakage current.Type: GrantFiled: November 13, 2006Date of Patent: November 23, 2010Assignee: National Semiconductor CorporationInventors: Jiankang Bu, Kenneth M. Lewis, Li-Heng Chou
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Patent number: 7838363Abstract: A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.Type: GrantFiled: October 31, 2007Date of Patent: November 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Robert F. Steimle, Gowrishankar L. Chindalore, Matthew T. Herrick
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Patent number: 7838406Abstract: The present invention is a semiconductor device including a semiconductor substrate having a trench, a first insulating film provided on side surfaces of the trench, a second insulating film of a material different from the first insulating film provided to be embedded in the trench, a word line provided extending to intersect with the trench above the semiconductor substrate, a gate insulating film of a material different from the first insulating film separated in an extending direction of the word line by the trench and provided under a central area in a width direction of the word line, and a charge storage layer separated in the extending direction of the word line by the trench and provided under both ends in the width direction of the word line to enclose the gate insulating film, and a method for manufacturing the same.Type: GrantFiled: December 24, 2008Date of Patent: November 23, 2010Assignee: Spansion LLCInventors: Takayuki Maruyama, Fumihiko Inoue
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Patent number: 7821055Abstract: A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.Type: GrantFiled: March 31, 2009Date of Patent: October 26, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Konstantin V. Loiko, Cheong M. Hong, Sung-Taeg Kang, Taras A. Kirichenko, Brian A. Winstead
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Patent number: 7816207Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.Type: GrantFiled: March 8, 2010Date of Patent: October 19, 2010Assignee: Renesas Technology Corp.Inventors: Tsutomu Okazaki, Motoi Ashida, Hiroji Ozaki, Tsuyoshi Koga, Daisuke Okada
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Patent number: 7811886Abstract: A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).Type: GrantFiled: February 6, 2007Date of Patent: October 12, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Brian A. Winstead, Taras A. Kirichenko, Konstantin V. Loiko, Ramachandran Muralidhar, Rajesh A. Rao, Sung-Taeg Kang, Ko-Min Chang, Jane Yater
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Patent number: 7785966Abstract: An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.Type: GrantFiled: December 21, 2006Date of Patent: August 31, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chang Liu, Wen-Ting Chu, Chi-Hsin Lo, Chia-Shiung Tsai
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Patent number: 7768061Abstract: A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.Type: GrantFiled: November 17, 2006Date of Patent: August 3, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-seog Jeon, Seung-beom Yoon, Yong-tae Kim
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Patent number: 7759197Abstract: Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross, e.g., are orthogonal to, the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with material, e.g., conductive material, to form conductive contacts.Type: GrantFiled: September 1, 2005Date of Patent: July 20, 2010Assignee: Micron Technology, Inc.Inventor: Luan C. Tran
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Patent number: 7727838Abstract: A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor body laterally spaced from the gate structure, thereby defining an active area in the semiconductor body therebetween. The method further includes performing an angled implant into the gate structure, wherein the shadowing structure substantially blocks dopant from the angled implant from implanting into the active area, and performing a source/drain implant into the gate structure and the active area.Type: GrantFiled: July 27, 2007Date of Patent: June 1, 2010Assignee: Texas Instruments IncorporatedInventors: Borna Obradovic, Shashank S. Ekbote
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Patent number: 7723188Abstract: A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.Type: GrantFiled: November 19, 2008Date of Patent: May 25, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Gyun Kim, Ji-Hoon Park, Sang-Woo Kang, Sung-Woo Park
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Patent number: 7723779Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.Type: GrantFiled: May 22, 2006Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Digh Hisamoto, Shin'ichiro Kimura, Daiske Okada, Kan Yasui
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Patent number: 7713820Abstract: A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.Type: GrantFiled: November 26, 2007Date of Patent: May 11, 2010Assignee: Nanya Technology CorporationInventors: Hung-Mine Tsai, Ching-Nan Hsiao, Chung-Lin Huang
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Patent number: 7704835Abstract: A selective spacer for semiconductor and MEMS devices and method of manufacturing the same. In an embodiment, a selective spacer is formed adjacent to a first non-planar body having a greater sidewall height than a second non-planar semiconductor body in a self-aligned manner requiring no patterned etch operations. In a particular embodiment, a margin layer of a particular thickness is utilized to augment an existing structure and provide sufficient margin to protect a sidewall with a spacer that is first anisotropically defined and then isotropically defined. In another embodiment, the selective spacer formation prevents etch damage by terminating the anisotropic etch before a semiconductor surface is exposed.Type: GrantFiled: December 29, 2006Date of Patent: April 27, 2010Assignee: Intel CorporationInventors: Rajwinder Singh, Willy Rachmady, Uday Shah, Jack T. Kavalieros
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Patent number: 7704829Abstract: A nonvolatile memory device and method for fabricating the same are provided. The nonvolatile memory device includes an active region; a source region formed in the active region; a source line formed on the source region and electrically connected with the source region, to cross over the active region; word lines aligned at each sidewall of the source line to cross over the active region in parallel with the source line; and a charge storage layer interposed between the word lines and the active region. Since the word lines are formed at both sides of the source line using an anisotropic etch-back process, without photolithography, the area of a unit cell can be reduced.Type: GrantFiled: December 30, 2005Date of Patent: April 27, 2010Assignee: LG Electronics Inc.Inventor: Sang Bum Lee
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Patent number: 7704834Abstract: Disclosed is a method for forming a non-volatile memory device, comprising the steps of: successively depositing a gate oxide and a floating gate material on a semiconductor substrate; depositing and selectively etching a first dielectric on the floating gate material to form a first dielectric pattern; forming a first floating gate oxide on the floating gate material; selectively etching the floating gate material with using the first dielectric pattern as a mask to form a floating gate pattern; forming an insulating layer on the floating gate pattern; etching a portion of the semiconductor substrate between neighboring floating gate patterns to form a trench in the substrate; depositing a control gate oxide on surfaces of the trench; depositing a control gate material to fill the trench and to cover the substrate surface; depositing a second dielectric on the control gate material; selectively etching the second dielectric and the control gate material to form a control gate pattern and a second dielectricType: GrantFiled: December 30, 2005Date of Patent: April 27, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Heong Jin Kim
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Patent number: 7700439Abstract: A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process with which to form silicided surfaces on both the select gate electrode and the control gate electrode.Type: GrantFiled: March 15, 2006Date of Patent: April 20, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Erwin J. Prinz, Ko-Min Chang, Robert F. Steimle
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Patent number: 7679126Abstract: A non-volatile memory device (e.g., a split gate type device) and a method of manufacturing the same are disclosed. The memory device includes an active region on a semiconductor substrate, a pair of floating gates above the active region, a charge storage insulation layer between each floating gate and the active region, a pair of wordlines over the active region and partially overlapping the floating gates, respectively, and a gate insulation film between each wordline and the active region. The method may prevent or reduce the incidence of conductive stringers on the active region between the floating gates, to thereby improve reliability of the memory devices and avoid the active region resistance from being increased due to the stringer.Type: GrantFiled: September 5, 2006Date of Patent: March 16, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Hyo Jung
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Patent number: 7659569Abstract: A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided.Type: GrantFiled: December 10, 2007Date of Patent: February 9, 2010Assignee: Spansion LLCInventors: Wei Zheng, Kuo-Tung Chang, Sung-Yong Chung, Ashot Melik-Martirosian
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Patent number: 7651914Abstract: A manufacturing method of a nonvolatile semiconductor memory device including: providing a first insulating film and a silicon film on a semiconductor substrate; providing a fifth insulating film containing silicon and oxygen on the silicon film; providing a second insulating film containing silicon and nitrogen on the fifth insulating film; providing a third insulating film on the second insulating film, the third insulating film is composed of a single-layer insulating film containing oxygen or multiple-layer stacked insulating film at least whose films on a top layer and a bottom layer contain oxygen, and relative dielectric constant of the single-layer insulating film and the stacked insulating film being larger than relative dielectric constant of a silicon oxide film; providing a fourth insulating film containing silicon and nitrogen on the third insulating film; and providing a control gate above the fourth insulating film.Type: GrantFiled: July 21, 2008Date of Patent: January 26, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Wakako Takeuchi, Yoshio Ozawa
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Patent number: 7618862Abstract: A method for manufacturing a flash memory device includes: a) forming a stack gate pattern composed of a tunnel oxide layer, a floating gate, ONO layers, and a control gate on a semiconductor substrate; b) conformably forming a first sidewall oxide layer made of a silicon oxide layer along both sidewalls of the stack gate pattern; c) performing a plasma nitride process for forming a nitride barrier layer in the first sidewall oxide layer; d) forming a sidewall nitride layer on the first sidewall oxide layer; e) conformably forming a second sidewall oxide layer on the sidewall nitride layer; and f) performing an etching process for forming a spacer which includes the first sidewall oxide layer, the nitride barrier layer, the sidewall nitride layer, and the second sidewall oxide layer. The flash memory device prevents data from being lost via the spacer equipped with a nitride barrier layer, resulting in increased reliability of a desired flash memory device.Type: GrantFiled: August 30, 2007Date of Patent: November 17, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Joo-Hyeon Lee
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Patent number: 7608884Abstract: A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction for charging the floating gate by electron injection from the source to the floating gate and at least a first dielectric is layered on top of the floating gate to form a second junction. At least a first polycrystalline silicon is layered on top of the first dielectric, the first polycrystalline silicon electrically connected to the source. Electron tunneling provided through the second junction to the floating gate charges the floating gate, thereby increasing the source-coupling ratio of the floating gate and increasing the efficiency of storing electrical charge.Type: GrantFiled: March 24, 2005Date of Patent: October 27, 2009Assignee: Taiwan Semiconductor Manufactruing Co., Ltd.Inventors: Te-Hsun Hsu, Hung-Cheng Sung
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Patent number: 7601596Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming trenches in a first side of a semiconductor material and forming a thick oxide layer on the trenches and on the first side. A part of the first side and the trenches is masked using a first mask, and the semiconductor material is doped by implantation through the thick oxide layer while the first mask is present. At least part of the thick oxide layer is removed while the first mask remains.Type: GrantFiled: November 16, 2006Date of Patent: October 13, 2009Assignee: Infineon Technologies Austria AGInventors: Markus Zundel, Franz Hirler, Rudolf Zelsacher, Erwin Bacher
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Patent number: 7601594Abstract: A method for fabricating a semiconductor memory, the method including: forming an element isolation region in a concave portion of the semiconductor substrate; forming a layer of a gate electrode material so as to cover the concave portion and the element isolation region; forming a gate electrode by forming a mask on a surface of the layer of a gate electrode material so that a height from an upper surface of the convex portion to the surface of the mask is higher than a height from the surface of the element isolation region to the upper surface of the convex portion and by patterning the layer of the gate electrode material; forming a charge storing layer at least one of side surfaces of the gate electrode in contact with the convex portion; and forming a sidewall on a part of the charge storing layer.Type: GrantFiled: March 11, 2008Date of Patent: October 13, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Koji Takaya
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Patent number: 7601593Abstract: The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the control gate and a read wordline. A tunneling metal-insulator-metal capacitor is created between the control gate and a write/erase bit line. In one embodiment, the insulator is a metal oxide.Type: GrantFiled: July 14, 2006Date of Patent: October 13, 2009Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7585726Abstract: The present invention enables to avoid a reduction in coupling ratio in a nonvolatile semiconductor memory device. The reduction is coupling ratio is caused due to difficulties in batch forming of a control gate material, an interpoly dielectric film material, and a floating gate material, the difficulties accompanying a reduction in word line width. Further, the invention enables to avoid damage caused in the batch forming on a gate oxide film. Before forming floating gates of memory cells of a nonvolatile memory, a space enclosed by insulating layers is formed for each of the floating gates of the memory cells, so that the floating gate is buried in the space. This structure is realized by processing the floating gates in a self alignment manner after depositing the floating gate material.Type: GrantFiled: February 9, 2006Date of Patent: September 8, 2009Assignee: Renesas Technology Corp.Inventors: Yoshitaka Sasago, Takashi Kobayashi
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Patent number: 7585731Abstract: A method of manufacturing a semiconductor integrated circuit device is provided including providing a substrate with projecting island regions formed in stripes, with first regions of the substrate adjacent the projecting island regions and with a conductive film covering the projecting island regions and first regions. An insulating film is formed between the projecting island regions and conductive film, wherein the projecting island regions extend in a first direction in stripes. The conductive film is anisotropically etched using a mask covering portions of the conductive film to form conductive lines on sides of the projecting island regions and the portions of the conductive film integrated with the conductive lines, which conductive lines serve as common gate electrodes for MISFETs.Type: GrantFiled: February 8, 2007Date of Patent: September 8, 2009Assignee: Renesas Technology Corp.Inventor: Shoji Shukuri