Abstract: A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity region, with a second insulating film being interposed; and a third insulating film formed on a side surface of the first gate. An interface between the third insulating film and the semiconductor substrate directly under the third insulating film is located above an interface between the second insulating film and the main surface of the semiconductor substrate directly under the second insulating film. The total number of steps can thus be reduced, and lower cost is achieved.

Abstract: Method for fabricating a semiconductor device, including the steps of providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon, forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate, selectively removing the first insulating film, the polysilicon, and the second insulating film, to form a floating gate pattern at the cell region, elevating a temperature initially in a state O2 gas is injected, maintaining a fix temperature, and dropping the temperature in a state N2 gas is injected, to form a gate oxide film on a surface of the semiconductor substrate at the logic region, and forming a gate electrode pattern at each of the cell region and the logic region, whereby preventing a threshold voltage of a semiconductor device from dropping due to infiltration of impurities from doped polysilicon at the cell region to the active channel region.

Abstract: Split gate memory cell formation includes forming a sacrificial layer over a substrate. The sacrificial layer is patterned to form a sacrificial structure with a first sidewall and a second sidewall. A layer of nanocrystals is formed over the substrate. A first layer of polysilicon is deposited over the substrate. An anisotropic etch on the first polysilicon layer forms a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall. Removal of the sacrificial structure leaves the first sidewall spacer and the second sidewall spacer. A second layer of polysilicon is deposited over the first and second sidewall spacers and the substrate. An anisotropic etch on the second layer of polysilicon forms a third sidewall spacer adjacent to a first side of the first sidewall spacer and a fourth sidewall spacer adjacent to a first side of the second sidewall spacer.

Abstract: The present invention relates to a method for processing of a non-volatile memory cell (50) which comprises a double gate stack and a single access gate. The method combines a way of processing an access gate with drain implant, separate from source implant, in a self-aligned manner. The method of the present invention does not require mask alignment sensitivity and makes it possible to implant self-aligned an extended drain for erasing of the memory device. Furthermore, the method provides a way of performing separately drain and source implant with different doping without the use of an additional mask.

Abstract: A nonvolatile memory device may include a semiconductor substrate; first and second floating gate electrodes formed on the semiconductor substrate; a control gate electrode formed on the first and second floating gate electrodes that may include a line body and a first leg, second leg, and third leg extending vertically from the line body toward the semiconductor substrate; and an inter-layer insulating film interposed between the semiconductor substrate and a lower end of the first leg and between the semiconductor substrate and a lower end of the second leg.

Abstract: Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.

Abstract: Embodiments relate to a single poly type EEPROM and a method for manufacturing an EEPROM. According to embodiments, a single poly type EEPROM may include unit cells. A unit cell may include a floating gate at a side of a control node formed on and/or over a semiconductor substrate having an activation region and a device isolation area, not overlapping a device isolation region but overlapping only a top of the activation region. A select gate may be formed on and/or over a top of the activation region. According to embodiments, a ratio of a capacitance of a control node side to a capacitance of a bit line side may increase, which may improve a coupling ratio. According to embodiments, a junction capacitance may be maximized by not doping the floating gate with an impurity, which may allow for a reduction in chip size by securing design margins.

Abstract: A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.

Abstract: Disclosed herein is a method for forming a gate structure of a semiconductor device. The method comprises forming a plurality of gates including a first gate dielectric film, a first gate conductive film, and a gate silicide film sequentially stacked on a silicon substrate having a field oxide film, forming a thermal oxide film on a side of the first gate conductive film, etching the silicon substrate exposed between the plurality of gates to a predetermined depth to form a plurality of trenches, forming a second gate oxide film on the interior wall of the trenches, and forming a second gate conductive film in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film, and the thermal oxide film.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.

Abstract: In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.

Abstract: A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates (49 and 50) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate (34). A source doped region (60) is positioned in the semiconductor substrate (12) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer (42) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.

Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

Abstract: A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted.

Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region.

Abstract: A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.

Abstract: The present disclosure provides a memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, a tantalum-nitride layer, and a control gate layer. When a positive bias is applied to the control gate and the select gate, negative charges are injected from a channel region of a substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the negative charges in the charge storage layer. When a negative bias is applied to the control gate, negative charges are tunneled from the charge storage layer to the channel region of the substrate through the tunneling dielectric layer.

Abstract: A non-volatile memory device including a control gate pattern having a tunnel insulation pattern, a trap-insulation pattern, a blocking insulation pattern and a control gate electrode, which are stacked on a semiconductor substrate. A selection gate pattern is disposed on the semiconductor substrate at one side of the control gate pattern. A gate insulation pattern is interposed between the selection gate electrode and the semiconductor substrate, and between the selection gate electrode and the control gate pattern. A cell channel region includes a first channel region defined in the semiconductor substrate under the selection gate electrode and a second channel region defined in the semiconductor substrate under the control gate electrode.

Abstract: A method of manufacturing a split gate type non-volatile memory device includes the steps of defining an active region on a semiconductor substrate; forming a pair of first conductive film patterns, each having an electric charge storage layer interposed between the substrate and the first conductive film pattern, on the active region; forming a second conductive film on top of the first conductive film patterns and a remainder of the active region; etchbacking the entire surface of the second conductive film to planarize a top of the second conductive film formed between the first conductive film patterns; forming a photoresist pattern, with an opening corresponding to the active region between the first conductive film patterns, on the second conductive film; and forming a pair of split gates each having one of the first conductive film patterns and a second conductive film pattern formed by patterning the second conductive film using the photoresist pattern as an etching mask.

Abstract: A scalable two-transistor memory (STTM) device includes a planar transistor and a vertical transistor on a semiconductor substrate. The planar transistor includes spaced apart metal silicide source/drain regions on the substrate and a floating gate electrode on the substrate between the metal silicide source/drain regions that controls a channel region of the planar transistor. The vertical transistor includes a tunnel junction structure on the floating gate electrode and a control gate electrode on a sidewall of the tunnel junction structure that controls a channel region of the vertical transistor. Related methods of forming STTM devices are also discussed.

Abstract: A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined in the semiconductor substrate. The second and third insulation layers are formed in the high and low voltage device regions, respectively. The transistors are formed on the second and third insulation layers, respectively.

Abstract: A method of manufacturing a non-volatile memory includes providing a substrate and forming a patterned mask layer, a tunnel dielectric layer, and a first conductive layer on the substrate. The first conductive layer on the mask layer is removed to form second conductive layers disposed on the sidewall of the mask layer and the substrate. The mask layer is then removed and a source region is formed. Subsequently, an inter-gate dielectric layer and a third conductive layer are formed on the substrate. The third conductive layer is patterned to cover the source region and a portion of the second conductive layer on both sides of the source region. A portion of the inter-gate dielectric layer and the second conductive layers are then removed. After that, a dielectric layer, a fourth conductive layer, and a drain region are formed, respectively.

Abstract: A semiconductor device has: an isolation region formed on a semiconductor substrate and defining a continuous active region including a select transistor region and a direct tunnel element region; a gate insulating film formed on a channel region of the select transistor region; a tunnel insulating film formed on a partial area of the direct tunnel element region and having a thickness different from a thickness of the gate insulating film; a continuous floating gate electrode formed above the gate insulating film and the tunnel insulating film; an inter-electrode insulating film formed on a surface of the floating gate electrode; a control gate electrode facing the floating gate electrode via the inter-electrode insulating film; and a pair of source/drain regions formed on both sides of the channel region of the select transistor region and not overlapping the tunnel insulating film.

Abstract: A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region.

Abstract: A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than the first dielectric layer; depositing a third dielectric layer to fill the trench; removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer; oxidizing the lower portion of the third dielectric layer after removing the upper portion; removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer; and forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.

Abstract: Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.

Abstract: The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the control gate and a read wordline. A tunneling metal-insulator-metal capacitor is created between the control gate and a write/erase bit line. In one embodiment, the insulator is a metal oxide.

Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Abstract: A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.

Abstract: A multi-bit split-gate memory device is formed over a substrate. A storage layer is formed over the substrate. A first conductive layer is formed over the storage layer. A thickness of a portion of the conductive layer is removed to leave a pillar of the conductive layer and an area of reduced thickness of the conductive layer. A first sidewall spacer is formed adjacent to the pillar to cover a first portion and a second portion of the area of reduced thickness of the conductive layer. The pillar is replaced with a select gate. The area of reduced thickness is selectively removed to leave the first and second portions as control gates.

Abstract: A method for fabricating a semiconductor device for a system on chip (SOC) for embodying a transistor for a logic device, an electrical erasable programmable read only memory (EEPROM) cell and a flash memory cell in one chip is provided. Floating gates of the EEPROM cell and the flash memory cell are formed by using a first polysilicon layer; and a gate electrode of the logic device and control gates of the EEPROM cell and the flash memory cell are formed by using a second polysilicon layer. Thus, it is possible to stably form the logic device, the EEPROM cell and the flash memory cell in one chip.

Abstract: A storage device has a two bit cell in which the select electrode is nearest the channel between two storage layers. Individual control electrodes are over individual storage layers. Adjacent cells are separated by a doped region that is shared between the adjacent cells. The doped region is formed by an implant in which the select gates of adjacent cells are used as a mask. This structure provides for reduced area while retaining the ability to perform programming by source side injection.

Abstract: A semiconductor device includes a substrate including a high-voltage transistor area provided with a high-voltage transistor and a low-voltage transistor area provided with a low-voltage transistor; a LOCOS layer provided as a device isolation layer of the high-voltage transistor area; and a shallow-trench isolation layer provided as a device isolation layer of the low-voltage transistor area. Accordingly, a sufficient breakdown voltage level can be provided in a high-voltage transistor area, on-resistance and leakage current can be enhanced, and the chip area in a low-voltage transistor area can be reduced.

Abstract: Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A protection liner covers the semiconductor fin and the trench isolations in a bottom portion of the gate groove and the pockets. An insulator collar is formed in the exposed upper sections of the gate groove and the pockets, wherein a lower edge of the insulator collar corresponds to a lower edge of source/drain regions formed within the semiconductor fin. The protection liner is removed. The bottom portion of the gate groove and the pockets are covered with a gate dielectric and a buried gate conductor layer. The protection liner avoids residuals of polycrystalline silicon between the active area in the semiconductor fin and the insulator collar.

Abstract: A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first conductive structure. Then, the size of the second conductive structure is reduced so that a top surface of the second conductive structure is relatively lower than that of the first conductive structure. Thereafter, a second dielectric layer is formed over the substrate to cover the first and the second conductive structure. A via is formed in the second dielectric layer to expose the top surface of the first conductive structure. Finally, a via plug is formed in the via.

Abstract: A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.

Abstract: Disclosed are a multi-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the multi-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

Abstract: A method of formation a gate in a semiconductor device includes forming a gate oxide layer and a sacrificial layer on a semiconductor substrate. The sacrificial layer is then selectively etched to form a sidewall opening. Next, a polycrystalline silicon layer is formed on an area of the gate oxide layer exposed through the sidewall opening and on the sacrificial layer. Anisotropic etching of the polycrystalline silicon layer is performed such that sidewall gates are formed by remaining portions of the polycrystalline silicon layer on sidewalls of the sidewall opening, a width of the sidewall gates corresponding to a desired width of a gate. The sacrificial layer is removed following etching of the polycrystalline silicon layer.

Abstract: Split gate memory cell formation includes forming a sacrificial layer over a substrate. The sacrificial layer is patterned to form a sacrificial structure with a first sidewall and a second sidewall. A layer of nanocrystals is formed over the substrate. A first layer of polysilicon is deposited over the substrate. An anisotropic etch on the first polysilicon layer forms a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall. Removal of the sacrificial structure leaves the first sidewall spacer and the second sidewall spacer. A second layer of polysilicon is deposited over the first and second sidewall spacers and the substrate. An anisotropic etch on the second layer of polysilicon forms a third sidewall spacer adjacent to a first side of the first sidewall spacer and a fourth sidewall spacer adjacent to a first side of the second sidewall spacer.

Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

Abstract: A method of manufacturing a NAND flash memory device, including the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined; simultaneously forming a plurality of cell gates on the semiconductor substrate of the cell region and forming selection gates on the semiconductor substrate of the select transistor region; forming an oxide film on the entire structure and then forming a nitride film; etching the nitride film so that the nitride film remains only between the selection gates and adjacent edge cell gates; and, blanket etching the oxide film to form spacers on sidewalls of the selection gates. Accordingly, uniform threshold voltage distributions can be secured, and process margins for a spacer etch target can be secured when etching the spacers. Furthermore, the nitride film partially remains between the edge cell gates and the selection gates even after the gate spacers are etched.

Abstract: Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: A semiconductor device with a recessed channel and a method of fabricating the same are provided. The semiconductor device comprises a substrate, a gate, a source, a drain, and a reverse spacer. The substrate comprises a recessed trench. The gate is formed above the recessed trench and extends above the substrate. The gate further comprises a polysilicon layer and a conductive layer; wherein the polysilicon layer is formed inside the recessed trench of the substrate, and the conductive layer is formed above the polysilicon layer and extends above the substrate. Moreover, the width of the conductive layer increases gradually bottom-up. The source and the drain are formed respectively at two sides of the gate. The reverse spacer is formed above the polysilicon layer and against the sidewall of the conductive layer.

Abstract: The invention relates to a method for manufacturing at least one phase change memory cell. The method at least fabricating at least one first lamellar spacer of conductive material, which is electrically coupled to the PCM material of the memory cell; fabricating at least one second lamellar spacer on top of the first lamellar spacer, wherein the second lamellar spacer crosses the first lamellar spacer in the area of the PCM material; partially removing the first lamellar spacer, wherein the second lamellar spacer serves as a hardmask for partially removing the first lamellar spacer, so that the first lamellar spacer forms at least one electrode contacting an area of PCM material.

Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

Abstract: A manufacturing method of a nonvolatile semiconductor memory includes steps (a) to (d). The (a) is a step of laminating a 2nd insulating film, a gate film and a hard mask film which cover a 1st gate electrode of a 1st memory cell transistor formed on a 1st region of a semiconductor substrate through a 1st insulating layer and a 3rd gate electrode of a 2nd memory cell transistor formed on a 2nd region through the 1st insulating layer. The (b) is a step of forming a 1st hard mask layer which covers a bottom portion and a side surface of a concave portion formed using the gate film between the 1st gate electrode and the 3rd gate electrode by etching the hard mask film. The (c) is a step of forming a 2nd gate electrode of the 1st memory cell transistor on the 1st region, a 4th gate electrode of the 2nd memory cell transistor on the 2nd region, and a connection layer which connects the 2nd gate electrode and the 4th gate electrode under the 1st hard mask layer by etching the gate film.

Abstract: A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) that are physically separated from one another but that control a substrate channel (71) subsequently defined in the substrate (11) by source/drain regions (82, 102, 84, 104) that are implanted around the etched gate structures (72, 74). Depending on how the first spacer structure (42) is positioned and configured, the channel (71) may be controlled to provide either a logical AND gate (100) or logical OR gate (200) functionality.

Abstract: A method for fabricating a flash memory device including the steps of: providing a substrate having thereon a gate with therein a control gate; lining the substrate and the gate with a liner; forming a silicon layer on the liner; forming a sacrificing layer on the silicon layer; etching the sacrificing layer to expose a portion of the silicon layer; removing the exposed silicon layer to expose a portion of the liner; removing the sacrificing layer; forming a spacer layer on the substrate covering the remaining silicon layer and the exposed liner; etching the spacer layer to form a spacer on sidewall of the gate; and removing the silicon layer that is not covered by the spacer thereby forming floating gate on sidewall of the gate.