Abstract: A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.

Abstract: A semiconductor process and structure (32) uses a disposable sidewall spacer (42) associated with lightly doped drain (LDD) transistors. The disposable sidewall spacers are efficiently removed by a gaseous fluorine ambient. Either molecular or atomic fluorine gas is used to remove a silicon germanium sidewall spacer with high selectivity to exposed insulating layers. This etch process is also isotropic. An additional benefit of using a gaseous fluorine ambient is incorporation of fluorine in isolation regions (48) surrounding the transistors, thereby reducing the dielectric constant. Improved insulating properties of the isolations regions can allow increased integration.

Abstract: A P-type pocket layer is formed in the surficial portion of a semiconductor substrate, a sidewall insulating film having a thickness of as thin as 10 nm or around is formed, and P is implanted therethrough to thereby form an N-type extension layer in the surficial portion of the p-type pocket layer. Then, a sidewall insulating film is formed, and P is implanted to thereby form an N-type source and a drain diffusion layer. P, having a larger coefficient of diffusion than that of conventionally-used As, used in the formation of the pocket layer can successfully moderate a strong electric field in the vicinity of the channel, and can consequently reduce leakage current between the drain and the semiconductor substrate and thereby reduce the off-leakage current, even if the gate length is reduced to 100 nm or shorter.

Abstract: A disposable spacer for use in a semiconductor device fabrication process is formed of a germanium-silicon alloy. The germanium-silicon alloy may include a first portion (x) of germanium and a second portion (1−x) of silicon, wherein x is greater than about 0.2.

Abstract: Subjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gate electrode and a gate insulating film. LDD region is formed by using the first gate electrode as a mask, and a source region and a drain region are formed by using the second gate electrode as a mask. By removing a portion of the second gate electrode, a structure in which a region where LDD region and the second gate electrode overlap with a gate insulating film interposed therebetween, and a region where LDD region and the second gate electrode do not overlap, is obtained.

Abstract: In methods for fabricating MOS transistors with notched gate electrodes, a notched gate electrode may be readily fabricated using a damascene process for filling a stair-shaped opening formed in a multi-layered insulation layer. In this manner, the width and a height of the notch region of the gate electrode may be readily adjusted and controlled.

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

Abstract: This invention relates to a process of forming a transistor with three vertical gate electrodes and the resulting transistor. By forming such a transistor it is possible to maintain an acceptable aspect ratio as MOSFET structures are scaled down to sub-micron sizes. The transistor gate electrodes can be formed of different materials so that the workfunctions of the three electrodes can be tailored. The three electrodes are positioned over a single channel and operate as a single gate having outer and inner gate regions.

Abstract: Method for forming contact electrodes in a semiconductor device are disclosed. An example method comprises sequentially forming a pad oxide layer, a pad nitrate layer, a dummy oxide layer, and a capping nitride layer on a substrate. These layers and the substrate are then patterned to form a trench. The trench us filled with an insulating material to form a device isolation stripe. The resulting structure is then patterned to form a trench. Spacers are formed on the sidewalls of the trench and ions are implanted into the substrate beneath the trench to form local channel portions. A gate insulating layer and a gate electrode are then formed by deposition. Thereafter, the dummy oxide layer and the capping nitride layer are removed and source/drain portions are defined. Contact electrodes are then formed by deposition of a metal layer.

Abstract: A method for fabricating a memory unit with T-shaped gate. A semiconductor substrate forming a dielectric layer, a first opening, and a second opening is provided in a CMOS process. A silicate glass spacer is formed on the sidewall of the first opening and is thermally oxidized to form a light doped area under the silicate glass spacer. The silicate glass spacer is removed. An insulating spacer is formed on the sidewall of the first opening. A first spacer is formed on a sidewall of the second opening. N-type conducting spacers are formed respectively on sidewalls of the insulating spacer and the first spacer. Gate dielectric layers are formed respectively in the first opening and the second opening. A P-type conducting layer fills with the first opening and the second opening, and a second spacer is formed on a sidewall of a conducting spacer of the second opening.

Abstract: Within a method for forming a spacer layer from a second layer formed of a second material laminated upon a first layer formed of a first material, in turn formed over a topographic feature, there is employed a three step etch method. The three step etch method employs: (1) a first etch method having a first enhanced etch selectivity for the second material with respect to the first material; (2) a second etch method having a second substantially neutral etch selectivity for the second material with respect to the first material; and (3) a third etch method having a third enhanced etch selectivity for the first material with respect to the second material. In accord with the three step etch method, the spacer layer is fabricated with enhanced dimensional control.

Abstract: A gate oxide film is formed on a substrate. Next, gate interconnections, each including a first silicon film, a silicide film and a dielectric film, are formed on the gate oxide film. Next, an impurity is implanted into the substrate while the gate interconnections are taken as a mask, thereby forming a first diffusion layer. Next, a second silicon film is formed over the entire surface of the substrate so as to cover the gate interconnections. Next, the second silicon film is thermally oxidized, thereby forming a thermal oxide film. An interlayer dielectric film is formed on the thermal oxide film.

Abstract: A method is provided for forming polysilicon line structures, such as gate electrodes of field effect transistors, according to which oxide spacers are removed from the sidewalls of the poly gate lines before depositing the liner oxide. Accordingly, after formation of the final spacers, the polysilicon line sidewalls are no longer covered with spacer oxide but all silicide pre-cleans can clear the poly sidewalls completely which thus leads to improved silicidation conditions, resulting in gate lines exhibiting very low sheet resistivity.

Abstract: A method for forming a MOSFET having an elevated source/drain structure is described. A sacrificial oxide layer is provided on a substrate. A polish stop layer is deposited overlying the sacrificial oxide layer. An oxide layer is deposited overlying the polish stop layer. An opening is formed through the oxide layer and the polish stop layer to the sacrificial oxide layer. First polysilicon spacers are formed on sidewalls of the opening wherein the first polysilicon spacers form an elevated source/drain structure. Second polysilicon spacers are formed on the first polysilicon spacers. The oxide layer and sacrificial oxide layer exposed within the opening are removed. An epitaxial silicon layer is grown within the opening. A gate dielectric layer is formed within the opening overlying the second polysilicon spacers and the epitaxial silicon layer. A gate material layer is deposited within the opening.

Abstract: A method of making a Silicon-on-Insulator (SOI) transistor includes forming a body layer that is fully depleted when the SOI transistor is in a conductive state and forming first p+ regions adjacent each of the SOI transistor source/drain regions to adjust the SOI transistor threshold voltage. To suppress punch-through current, an additional implant step is carried out to form second p+ regions adjacent first implant regions.

Abstract: A split gate flash memory. A drain is disposed in the bottom of a trench formed in a substrate. A source is disposed in the substrate outside the trench. A striped floating gate is disposed at a sidewall of the trench, wherein one side of the striped floating gate is near the bottom of the trench, and the other side of the striped floating gate protrudes above the substrate. A control gate winds along the floating gate, wherein one side of the control gate is near the bottom of the trench, and the other side of the control gate in outside the trench. A metal bit line connects to the drain.

Abstract: A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

Abstract: A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

Abstract: Many integrated circuits, particularly digital memories, include millions of field-effect transistors which operate simultaneously and thus consume considerable power. One way to reduce power consumption is to lower transistor threshold, or turn-on, voltage, and then use lower-voltage power supplies. Although conventional techniques of lowering threshold voltage have enabled use of 2-volt power supplies, even lower voltages are needed. Several proposals involving a dynamic threshold concept have been promising, but have failed, primarily because of circuit-space considerations, to yield practical devices. Accordingly, the present invention provides a space-saving structure for a field-effect transistor having a dynamic threshold voltage. One embodiment includes a vertical gate-to-body coupling capacitor that reduces the surface area required to realize the dynamic threshold concept. Other embodiments include an inverter, voltage sense amplifier, and a memory.

Abstract: A method for fabricating a memory unit with T-shaped gate. A semiconductor substrate forming a dielectric layer, a first opening, and a second opening is provided in a CMOS process. A silicate glass spacer is formed on the sidewall of the first opening and is thermally oxidized to form a light doped area under the silicate glass spacer. The silicate glass spacer is removed. An insulating spacer is formed on the sidewall of the first opening. A first spacer is formed on a sidewall of the second opening. N-type conducting spacers are formed respectively on sidewalls of the insulating spacer and the first spacer. Gate dielectric layers are formed respectively in the first opening and the second opening. A P-type conducting layer fills with the first opening and the second opening, and a second spacer is formed on a sidewall of a conducting spacer of the second opening.

Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

Abstract: A semiconductor fabrication process and structure in which a semiconductor channel structure (140) having first and second major surfaces perpendicular to a semiconductor substrate (102) is formed overlying and electrically isolated from the substrate (102). First and second gate dielectrics (120, 142) are formed on the channel structure's first and second major surfaces respectively. First and second gate dielectrics (120, 142) differ in at least one characteristic. First and second gate electrodes (116, 152) are formed in contact with the first and second gate dielectrics (120, 142) respectively. The first and second gate electrodes (116, 152) differ in at least one characteristic. First and second gate dielectrics (120, 142) may have different dielectric constants while first and second gate electrodes (116, 152) may have different doping and conducting properties.

Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function.

Abstract: The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1−xGex, x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.

Abstract: A gate electrode contact spacer (144) for a vertical DRAM device (100) and a method for forming the same. Memory cells (118) are formed within deep trenches (116) of a workpiece (112). A temporary spacer adjacent gate electrode contacts (132) and pad nitride layer are removed. A spacer material is deposited over exposed portions of the workpiece (112) and over the top and sides of the gate electrode contacts (132). The spacer material is removed from the horizontal surfaces of the DRAM device (100), including the exposed portions of the workpiece (112) and the top of the gate electrode contacts (132). Spacers (144) having sidewalls sloping downwardly away from the gate electrode contacts (132) are left remaining on the gate electrode contact (132) sides, preventing voids from forming during a subsequent array top oxide deposition. Spacers may also be formed adjacent top regions of isolation trenches simultaneously with the formation of spacers (144).

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.

Abstract: Within a method for fabricating a split gate field effect transistor (FET) device there is employed a two step etch method for forming a floating gate electrode. Within the two step etch method there is employed a patterned first masking layer and a blanket second masking layer to assist in providing the floating gate electrode with a sharply pointed tip within at least either an upper edge of the floating gate electrode or sidewall of the floating gate electrode. The sharply pointed tip provides the split gate field effect transistor (FET) device with enhanced data erasure performance.

Abstract: Within a method for forming a spacer layer from a second layer formed of a second material laminated upon a first layer formed of a first material, in turn formed over a topographic feature, there is employed a three step etch method. The three step etch method employs: (1) a first etch method having a first enhanced etch selectivity for the second material with respect to the first material; (2) a second etch method having a second substantially neutral etch selectivity for the second material with respect to the first material; and (3) a third etch method having a third enhanced etch selectivity for the first material with respect to the second material. In accord with the three step etch method, the spacer layer is fabricated with enhanced dimensional control.

Abstract: A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of suicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

Abstract: A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Therefore, the present invention can obtain an effect such as using a SOI substrate or a SIMOX substrate and can prevent a lowering in an electrical characteristic of the device, by using a bulk substrate made of a single crystal silicon but forming an insulating layer into which oxygen is injected below a LDD region.

Abstract: A floating gate with sharp corner is disclosed. Wherein the sharp level of the sharp corners is control by the deposition thickness of the conductive spacers. The method comprises forming a first dielectric layer on the semiconductor substrate as a gate dielectric. A first conductive layer is formed on the first dielectric layer, and a second dielectric layer is then formed thereon. The second dielectric layer and the first conductive layer are next patterned. Subsequently, conductive spacers with sharp corners are created by well know anisotropical etching. A tunneling dielectric layer is then formed on the surface of a floating gate consisting of the spacers and patterned structure. A second conductive layer is formed on the tunneling dielectric layer as a control gate.

Abstract: A method of fabricating dual gate oxide thicknesses comprising the following steps. A substrate is provided having a first pillar and a second pillar. A gate dielectric layer is formed over the substrate and the first and second pillars. First and second thin spacers are formed over the gate dielectric layer covered side walls of the first and second pillars respectively. The second pillar is masked leaving the first pillar unmasked. The first thin spacers are removed from the unmasked first pillar. The mask is removed from the masked second pillar. The structure is oxidized to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar. The second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar.

Abstract: An exemplary embodiment relates to a method of finFET patterning. The method can include patterning a fin structure above a substrate, forming amorphous carbon spacers along lateral sidewalls of the fin structure, depositing an oxide layer and polishing the oxide layer to expose top portions of the fin structure and the amorphous carbon spacers, removing amorphous carbon spacers, and depositing polysilicon where the amorphous carbon spacers were located.

Abstract: A semiconductor device includes a T-shaped gate electrode. The T-shaped electrode may have a metal upper layer and a semiconductor lower layer with a diffusion barrier therebetween. The metal upper layer may be used as a gate mask to control implantation of ions in a semiconductor substrate. Gate metal-semiconductor portions may be electrically coupled to both the metal upper portion and the semiconductor lower portion thereby to reduce electrical resistance in the T-shaped electrode. A method of forming source and drain regions in the semiconductor device includes using the T-shaped gate electrode as an implant mask.

Abstract: Within a method for fabricating a field effect transistor (FET) device there is provided a series of ion implant methods which provide the field effect transistor (FET) device with both: (1) a source region asymmetrically doped with respect to a drain region; and (2) an asymmetrically doped channel region. The field effect transistor (FET) device is fabricated with enhanced performance.

Abstract: The present invention relates to a silicon-on-insulator (SOI) substrate, a method for fabricating the SOI substrate and a SOI MOSFET using the SOI substrate to easily migrate the design applied to a conventional bulk silicon substrate to the SOI design and to remove a floating body effect. The SOI substrate includes a mono-silicon substrate, a buried oxide layer formed over the surface of the mono-silicon substrate, and a thin mono-silicon layer formed over the surface of the buried oxide layer. Conductive layers are formed at through holes of the buried oxide layer positioned between the predetermined regions of the thin layer and the substrate for body contacts. Therefore, additional layout spaces are not needed for body contacts and the constant body contact resistance can allow the conventional circuit design applied to die bulk silicon substrate to be migrated to the circuit design applied to the SOI substrate without any modifications.

Abstract: A method for blocking formation of a reacted metal layer on a structure in an integrated circuit. The integrated circuit has a source region, a drain region, a gate, an isolation area formed of a material, and a protective layer formed of substantially the same material as the isolation area. The protective layer overlies at least the source region and the drain region. The method is accomplished while reducing an amount of the material of the isolation area that is removed when the material of the protective layer is removed. A blocking layer is deposited on the integrated circuit. The blocking layer is formed of a material that is substantially different from the material of the isolation area and the protective layer. The blocking layer is patterned to selectively cover portions of the blocking layers that overlie at least the structure and selectively expose portions of the blocking layer that overlie at least the source region, the drain region, and the gate.

Abstract: A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon spacers.

Abstract: An interconnect structure having refractory sidewalls 240 for enhanced yield, performance and reliability. The primary purpose of the refractory metal 240 is to getter sidewall impurities, residual polymers, and corrosive species by-products from the plasma etch and cleanup processes used to pattern interconnects. In a preferred embodiment, the refractory metal 240 reacts with the conducting layer 210 to form an intermetallic 245 which further enhances the endurance of the metallization against stress-induced rupturing and via-induced electromigration. The disclosed structures and methods are particularly advantageous in “zero-overlap” designs, and aggressive pitch patterns where linewidth and corrosion control are critical, but are also advantageous in “Damascene” pattern definition applications.

Abstract: The present invention relates to an integrated circuit having a MOS capacitor. In one embodiment, a method of forming an integrated circuit comprises forming an oxide layer on a surface of a substrate, the substrate having a plurality of isolation islands. Each isolation island is used in forming a semiconductor device. Patterning the oxide layer to expose predetermined areas of the surface of the substrate. Depositing a nitride layer overlaying the oxide layer and the exposed surface areas of the substrate. Implanting ions through the nitride layer, wherein the nitride layer is an implant screen for the implanted ions. Using the nitride layer as a capacitor dielectric in forming a capacitor. In addition, performing a dry etch to form contact openings that extend through the layer of nitride and through the layer of oxide to access selected device regions formed in the substrate.

Abstract: A method of using amorphous carbon as spacer material in a disposable spacer process can include forming amorphous carbon spacers at lateral side walls of a gate structure over a substrate, implanting dopants in the substrate to form source and drain regions, ashing away the amorphous carbon spacers, and implanting dopants to form shallow structures in the substrate.

Abstract: A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad oxide layer and a nitride layer sequentially on a silicon substrate, which has trench isolations. Then, a polysilicon layer and an oxide layer are deposited in order on all areas. Subsequently, an etched-back using the nitride layer a stopping layer is achieved. After that the nitride layer is removed thereby, forming a gate hollow region. After the pad oxide layer is removed, an oxynitride layer is regrown to be as the gate oxide. Thereafter, a silicon is deposited on all areas and refills in the gate hollow region. A planarization process is again performed using the oxide layer as an etch-stopping layer. Subsequently, the oxide layer is removed. S/D/G ion implanted into the polysilicon layer and the silicon layer. Then, the nitride spacers are removed to form dual recessed spaces.

Abstract: A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device.

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

Abstract: Low-resistance gate transistor and method for fabricating the same, in which a metal sidewall is formed at sides of a gate polysilicon layer to reduce the resistance and the height of a gate, thereby improving the characteristics of a semiconductor device, the low-resistance gate transistor of the present invention including a gate oxide film formed on a semiconductor substrate; a gate formed on the gate oxide film; a first gate sidewall having a vertical pattern in contact with a side of the gate at both sides of the gate and a horizontal pattern formed on the gate oxide film extended from the vertical pattern; second gate sidewalls formed of a material having a resistivity lower than the gate, each having one side in contact with the vertical pattern of the first gate sidewall and a bottom in contact with the horizontal pattern of the first gate sidewall with a round surface; an insulating layer formed on an entire surface including the gate and the first and second gate sidewalls; and, source/drain regions

Abstract: A high-voltage transistor and fabrication process in which the fabrication of the high-voltage transistor can be readily integrated into a conventional CMOS fabrication process. The high-voltage transistor of the invention includes a channel region formed beneath a portion of the gate electrode after the gate electrode has been formed on the surface of a semiconductor substrate. In a preferred embodiment, the channel region is formed by the angled ion implantation of dopant atoms using an edge of the gate electrode as a doping mask. The high-voltage transistor of the invention further includes a drain region that is spaced apart from the channel region by a portion of a well region and by an isolation region residing in the semiconductor substrate. By utilizing the process of the invention to fabricate the high-voltage transistor, the transistor can be integrated into an existing CMOS device with minimal allocation of additional substrate surface area.

Abstract: A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon spacers.

Abstract: Disclosed is a method for forming a gate electrode of a semiconductor device, the method comprises the steps of: stacking a gate oxide film, a doped first silicon film, a diffusion preventing film, a metal film having a high melting point and a mask insulating film on a semiconductor substrate; forming a gate electrode by patterning a resultant stack structure; forming a second silicon film on an entire surface of a resultant structure; forming an oxidation preventing film on an entire surface of a resultant structure; forming a spacer on a side wall of the gate electrode by anisotrophically etching the oxidation preventing film and the second silicon film; and forming a gate reoxide film on the semiconductor substrate by oxidizing the semiconductor substrate.