Abstract: The present invention includes forming a first oxide layer as a sacrificial dielectric layer on a semiconductor substrate. A nitride layer is formed on the sacrificial dielectric layer. Then, the sacrificial dielectric layer and the nitride layer are patterned to form an opening. Next, a second oxide layer is formed on the nitride layer and along a surface of the opening. Side wall spacers are created by etching. Then, a gate dielectric layer is formed on the exposed semiconductor substrate. A first polysilicon layer is deposited on the nitride layer. Subsequently, the first polysilicon layer is polished by CMP, followed by removing the nitride layer, the spacers and the sacrificial dielectric layer. A tunneling dielectric layer and a control gate are respectively formed on a surface of the floating gate.

Abstract: A first MISFET is formed in a first active region on the surface of a semiconductor substrate. The drain region of the first MISFET has a lightly doped drain structure with a low concentration region and a high concentration region. The side wall spacer conformingly covers the side wall of the gate electrode and the surface of the low concentration region in the drain region. A second MISFET is formed in a second active region. The side wall spacer of the second MISFET covers the side wall of the gate electrode and do not extend further to the surfaces of the source and drain regions. An interlayer insulating film covers the said first MISFET and second MISFET and is made of material having an etching resistance different from that of the side wall spacers of the first MISFET and second MISFET.

Abstract: Low-resistance gate transistor and method for fabricating the same, in which a metal sidewall is formed at sides of a gate polysilicon layer to reduce the resistance and the height of a gate, thereby improving the characteristics of a semiconductor device, the low-resistance gate transistor of the present invention including a gate oxide film formed on a semiconductor substrate; a gate formed on the gate oxide film; a first gate sidewall having a vertical pattern in contact with a side of the gate at both sides of the gate and a horizontal pattern formed on the gate oxide film extended from the vertical pattern; second gate sidewalls formed of a material having a resistivity lower than the gate, each having one side in contact with the vertical pattern of the first gate sidewall and a bottom in contact with the horizontal pattern of the first gate sidewall with a round surface; an insulating layer formed on an entire surface including the gate and the first and second gate sidewalls; and, source/drain regions

Abstract: A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. An epitaxy process can form the channel region. A silicon-on-insulator can be used.

Abstract: A method of fabricating a semiconductor device, having an asymmetrical dual-gate MOSFET with a silicon-germanium (SiGe) channel, involving: patterning a silicon-on-insulator (SOI) wafer with a photoreist layer, wherein the SOI structure comprises a silicon dioxide (SiO2) layer, a silicon (Si) layer deposited on the SiO2 layer, and a silicon nitride (Si3N4) layer deposited on the Si layer; initiating formation of a SiGe/Si/SiGe sandwich fin structure from the SOI structure; completing formation of the SiGe/Si/SiGe sandwich fin structure; depositing a thick gate material layer on the SiGe/Si/SiGe sandwich fin structure; forming an asymmetrical dual-gate; and completing fabrication of the semiconductor device, and a device thereby formed.

Abstract: The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1−xGex,x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.

Abstract: A semiconductor nonvolatile memory device using SA-STI cells improved in quality and suitable for increasing the degree of integration is provided with a semiconductor substrate having in its surface a channel formation region; an element isolation insulating film buried in a trench formed in the semiconductor substrate so as to divide the channel formation region into a plurality of regions; a gate insulating film formed on the channel formation region; a floating gate provided with a first floating gate formed at an upper layer of the gate insulating film and second floating gates formed at facing sides of the same; an inter-layer insulating film formed at an upper layer of the first floating gate and the second floating gates; a control gate formed at an upper layer of the inter-layer insulating film; and a source-drain region former connected to the channel formation region.

Abstract: A semiconductor device with a gate spacer containing a conductive layer, and a manufacturing method. A first spacer insulation layer is formed on a semiconductor substrate where a gate electrode is formed. Then, the first spacer insulation layer is etched to cover the side walls of the gate electrode. A conductive spacer film is subsequently formed on the resultant structure and is over-etched to form a conductive spacer that covers the first spacer insulation layer. In this step, the gate electrode is partially consumed to make the top of the first spacer insulation layer higher than the gate electrode. Also, an upper portion of the first spacer insulation layer is not comparatively etched due to an etching selectivity. This structure avoids shorts between the conductive spacer and the gate electrode. A second spacer insulation layer is then formed on the conductive spacer.

Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: In an integrated circuit with low threshold voltage differences of the transistors and a manufacturing process for such an integrated circuit, MOS transistors of different lengths but having threshold voltages that are substantially the same are made by avoiding dopant peaks at the channel edges by an angled nitrogen implantation, so that implantation paths at those edges are occupied by nitrogen atoms.

Abstract: An improved method for making an integrated circuit. That method includes forming a first dielectric layer on a substrate, etching a trench into that layer, then filling the trench with a conductive material. The conductive material is then electropolished to form a recessed conductive layer within the first dielectric layer.

Abstract: In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At least a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.

Abstract: A method of fabricating an integrated circuit (IC) with source and drain extension regions. Advantageously, the source and drain extension regions are formed without damage related to integrated circuit implant techniques. Damage is avoided by using solid phase doping to form extension regions. Generally, a doped material is provided adjacent to a transistor gate structure and the IC is annealed. During the annealing process, dopants from the doped material diffuse into the semiconductor substrate to form the source and drain extension regions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs).

Abstract: There is disclosed a method of manufacturing a transistor in a semiconductor device by which, when forming an elevated channel using an epitaxy technology for further expanding the applied region of a buried channel PMOS transistor, indium ions having the high amount of atoms and a low diffusion speed after growth of an epitaxial layer are implanted to distribute them into a boron epitaxial layer and a lower portion. Thus, it can obtain a desired threshold voltage Vt in a device and can improve degradation in a short channel.

Abstract: In accordance with an embodiment of the present invention, a method of forming a memory cell includes: forming a floating gate over a first portion of a silicon body region, the floating gate being insulated from the underlying first portion of the body region; forming a second layer polysilicon over the floating gate and a second portion of the body region, the second layer polysilicon being insulated from the underlying floating gate and the second portion of the body region; and forming a masking layer over the second layer polysilicon, the masking layer having a width along a first dimension parallel to the surface of the body region such that the masking layer extends over an entire width of the floating gate along the first dimension but does not extend beyond edges of steps of the second layer polysilicon formed due to the presence of the floating gate. Among many other advantages, such method provides a means of accurately controlling the cell channel length.

Abstract: Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example, to semiconductor interconnects, polysilicon gate, and capacitor applications. The inventive method provides additional means of obtaining suitable sheet resistivity and resistances for deep submicron applications. Techniques are disclosed for improving the conductivities of a silicided gate structure, a silicided interconnect structure, and capacitor component structures, each of such are situated on a substrate assembly, such as a semiconductor wafer.

Abstract: An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.

Abstract: A TFT of the present invention includes an insulating substrate, a first conductive film layer which is to be a gate electrode provided on the insulating substrate, a first insulating film layer which is to be a gate insulating film layer provided on the first conductive film layer, a non-doped semiconductor layer formed on the first insulating film layer, and a second conductive film layer which is to be a source electrode formed on a source region of the semiconductor layer and a drain electrode formed on a drain region of the semiconductor, wherein a junction is formed by implanting an n-type impurity in the source region of the semiconductor layer and the drain region of the semiconductor.

Abstract: A method is taught for forming a rectangular or near rectangular polysilicon sidewall structure, which can be used as an ultra narrow MOSFET gate electrode. The method employs the use a step on a sacrificial oxide against which the polysilicon sidewall is formed. An etch stop, such as a gate oxide is formed alongside the step. A polysilicon layer is deposited over the step followed by a silicon nitride layer. Next a flowable layer is deposited and cured. In a first embodiment the flowable layer is deposited to completely cover the polysilicon layer. Next the wafer is planarized to exposed the polysilicon layer over the high part of the step an to a level wherein the polysilicon/silicon nitride interface is driven away from the step to a distance which determines the final width of the final sidewall structure. The residual flowable layer is then removed and a silicon oxide hardmask is grown over the exposed polysilicon.

Abstract: Low-resistance gate transistor and method for fabricating the same, in which a metal sidewall is formed at sides of a gate polysilicon layer to reduce the resistance and the height of a gate, thereby improving the characteristics of a semiconductor device, the low-resistance gate transistor of the present invention including a gate oxide film formed on a semiconductor substrate; a gate formed on the gate oxide film; a first gate sidewall having a vertical pattern in contact with a side of the gate at both sides of the gate and a horizontal pattern formed on the gate oxide film extended from the vertical pattern; second gate sidewalls formed of a material having a resistivity lower than the gate, each having one side in contact with the vertical pattern of the first gate sidewall and a bottom in contact with the horizontal pattern of the first gate sidewall with a round surface; an insulating layer formed on an entire surface including the gate and the first and second gate sidewalls; and, source/drain regions

Abstract: A non-volatile semiconductor memory device includes memory cells each having a duplicate gate structure in which a floating gate and a control gate are stacked.

Abstract: A structure having shallow-implanted elevated source/drain regions is formed with doped sidewall spacers. Diffusion of dopants from the sidewall spacers forms a doped region extending from underneath the gate electrode, along the edge of the epitaxial layer, to the doped (and uppermost) regions of the elevated source/drain. Low junction capacitance, is achieved because the shallow implant of the elevated source/drain regions places the junction inside the source/drain region itself. Low source/drain resistance is achieved because the diffused doped region provides a doped path between the shallow implanted region of the elevated source/drain and the channel region. Low source/drain junction depth is achieved because a second spacer can prevent dopant from being implanted through any faceted areas of the epitaxial layer. The doped extensions of the source/drain regions also have exceptionally low junction depth.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. A first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, the first silicon layer, and the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and the first dielectric layer is removed. A second silicon layer is formed on the semiconductor substrate and on the first silicon layer. Another doping step is performed to dope the second silicon layer. A series of process is then performed to form a metal silicide layer on the second silicon layer and also to diffuse and activate the doped dopants.

Abstract: A method of manufacturing a semiconductor device having shallow p-n junctions and silicide regions, capable of meeting both requirements of a high annealing temperature and a low annealing temperature. A lamination of two films made of materials having different etching characteristics is formed on the surface of a silicon substrate, covering an insulated gate electrode structure. The upper film is anisotropically etched to form side wall spacers. Impurity ions are implanted into a surface layer of the silicon substrate and sufficiently activated to a first level. The lower film is removed by using as a mask the side wall spacers, and a metal film capable of being silicided is deposited to perform a first silicidation reaction. The insulated gate electrode is exposed and impurity ions are implanted shallowly in the surface layer of the silicon substrate.

Abstract: A process for making split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an interpoly dielectric layer.

Abstract: A semiconductor device includes a gate structure formed on a substrate in which an LDD structure is formed, wherein gate structure includes a Schottky electrode making a Schottky contact with a channel region in the substrate, a low-resistance layer provided above the Schottky electrode, and a stress-relaxation layer interposed between the Schottky electrode and the stress-relaxation layer. The low-resistance layer and said stress-relaxation layer form an overhang structure with respect to the Schottky electrode.

Abstract: A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate, preferably of silicon, having a gate insulator thereover, preferably of silicon dioxide, forming a junction, preferably a silicon/silicon dioxide interface, and a gate electrode, preferably of doped polysilicon, over the partially fabricated device. Deuterium is implanted into the structure and the deuterium is caused to diffuse through the device. The device fabrication is then completed.

Abstract: A method for making a ULSI MOSFET chip includes forming the gate of a transistor on a silicon substrate, covering the gate with a SiON protective layer, and then implanting a pre-amorphization high dose Si or Ge implant into the substrate. Next, dopant is pre-implanted into the substrate to promote subsequent formation of source and drain extensions, with the SiON layer protecting the gate from the pre-amorphization high dose Si or Ge and from the dopant. Undoped polysilicon and polygermanium is then deposited onto the substrate adjacent the gate at relatively low temperatures (600° C.) to establish elevated source and drain regions without excessively thermally stressing the chip. The SiON layer is removed from the gate, and the gate and elevated source and drain regions are implanted with dopant, followed by rapid thermal annealing to form the source and drain extensions in the substrate below the gate. The gate and elevated source and drain regions are then silicidized.

Abstract: For fabricating a field effect transistor, a gate structure is formed on a gate dielectric on an active device area of a semiconductor substrate. A liner layer of a non-dielectric material is formed on sidewalls of the gate dielectric, and on a drain extension area and a source extension area of the active device area of the semiconductor substrate. First spacers of dielectric material are formed on the liner layer at sidewalls of the gate structure and over the drain and source extension areas. A contact junction dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form a drain contact junction and a source contact junction. The first spacers of dielectric material are etched using a first type of etching reactant that etches the first spacers but not the liner layer such that the gate dielectric is not exposed to the first type of etching reactant.

Abstract: Disclosed is a technique to provide an integrated circuit substrate with a transistor gate member that has opposing sidewalls. A first spacer extends from one of the sidewalls and a second spacer extends from another of the sidewalls. A source region and a drain region of the substrate are doped, with the first and second spacers correspondingly masking first and second regions of the substrate. The first and second spacers are removed after doping and the first and second regions are exposed. The exposed first and second regions are then doped. The substrate is heated after this second doping stage to simultaneously activate dopant in the source region, the drain region, the first region, and the second region. A third spacer is then formed on the first region and a fourth spacer is then formed on the second region. A suicide contact is established with at least the transistor member, the source region, or the drain region after formation of the third and fourth spacers.

Abstract: In one embodiment, a spacer layer (22) is formed overlying a gate electrode (16), which is formed on a semiconductor substrate (12). The spacer layer (22) is then etched to form a sidewall spacer (24). A scanning electron microscope (SEM) is then used to measure the width of the sidewall spacer (24). The measured value for the width of the sidewall spacer (24) is then used to adjust a subsequent integrated circuit fabrication process, such as a spacer etch process, an implant process, or an anneal process. As a result, transistors with improved drain saturation currents are fabricated.

Abstract: A implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: The present invention is directed to a metal oxide semiconductor transistor having a fully overlapped lightly doped drain (LDD) structure which offers the advantages of conventional fully overlapped LDD transistors but which significantly reduces the drain-to-gate overlap capacitance associate therewith. To achieve fully overlapped LDD construction and reduced drain-to-gate overlap capacitance, the metal oxide semiconductor transistor of the present invention employs a gate electrode comprising a main gate region formed from heavily doped polysilicon and depleted sidewall polysilicon spacers formed from undoped or depleted polysilicon. In the MOS transistor of the present invention, the lightly doped regions are fully over-lapped by the combination of the depleted sidewall polysilicon spacers and the main gate region.

Abstract: Polystringers that cause NAND-type memory core cells to malfunction are covered by ONO fence material. ONO fence is removed so that polystringers may then be removed more readily. A SiON layer, tungsten silicide layer, second polysilicon layer, ONO dielectric, and first polysilicon layer are successively removed from between NAND-type flash memory core cells leaving ONO fence that shields some first polysilicon layer material from removal. The device is next exposed to an hydrogen-fluoride solution to remove oxide-based materials, particularly ONO fence. Thereafter, the polystringers are exposed and may thus be removed more readily.

Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: A method of etching silicon nitride spacers beside a gate structure comprising: providing a gate electrode over a gate oxide layer on a substrate. A liner oxide layer is provided over the substrate and the gate electrode. A silicon nitride layer is provided over the liner oxide layer. The invention's nitride etch recipe is performed in a plasma etcher to anisotropically etch the silicon nitride layer to create spacers. The nitride etch recipe comprises a main etch step and an over etch step. The main etch step comprises the following conditions: a Cl2 flow between 35 and 55 molar %, a He flow between 35 and 55 molar %, a backside He pressure between 4 and 10 torr; and a HBr flow between 7.5 and 12.5 molar %; a pressure between 400 to 900 mTorr; at a power between 300 and 600 Watts. The etch recipe provides a spacer width to nitride layer thickness ratio of about 1:1 and does not pit the Si substrate surface.

Abstract: A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spacer regions are formed on sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided. Portions of source and drain extension regions in the semiconductor substrate adjacent the gate structure are also silicided.

Abstract: A method of manufacturing a flash memory having a dual floating gate structure. A source/drain region is formed in a substrate. A first conductive layer is formed on the substrate and between the source/drain region. A first dielectric layer is located between the substrate and the first conductive layer. A floating gate mask is formed on the substrate and the first conductive layer to expose a portion of the first conductive layer. The portion of the first conductive layer and a portion of the first dielectric layer beneath the exposed conductive layer are removed. The floating gate mask is removed. A conformal second dielectric layer and a second conductive layer are formed over the substrate in sequence. The second conductive layer and the second dielectric layer are formed to respectively form a control gate and a third dielectric layer.

Abstract: In a DMOS field effect transistor according to the present invention, a drift region of a first conductivity type is formed on a semiconductor substrate. A gate electrode is formed over the drift region, interposing a gate insulating layer between the drift region and the gate electrode. The gate electrode includes a gate conductive layer and a conductive spacer formed on the side wall of the gate conductive layer. A body region is formed to be self-aligned by the gate conductive layer. The source region is formed to be self-aligned by the conductive spacer. Therefore, a doping profile in a channel region of the body region has a form in which a uniform doping density value is maintained. Therefore, although the threshold voltage of the device is lowered by reducing the peak doping density, the density of impurities in the channel region is not decreased. Therefore, a punch-through characteristic is not deteriorated.

Abstract: A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.

Abstract: The present invention provides a method of forming a self-aligned contact hole on a semiconductor wafer. The semiconductor wafer comprises a substrate, two gates positioned on the substrate, at least a doped area between the gates on the substrate and spacers on each of two opposite walls of each gate wherein the spacers between the gates are joined and cover the doped area. The method comprises forming a dielectric layer on the surface of the semiconductor wafer, the dielectric layer covering the gates and the spacers. A first etching process is performed to remove the dielectric layer above the doped area down to a predetermined depth to form an opening, the bottom of the opening comprising the spacers and an upper portion of the gates. Poly-silicon spacers are then formed on the interior walls of the opening, the poly-silicon spacers covering an upper portion of the spacers and the upper portion of the gates.

Abstract: A method is provided for forming a MOS transistor in a highly integrated semiconductor device. In this method a gate pattern is initially formed over a semiconductor substrate. A first dielectric film is then formed over the gate pattern at a first temperature at which deformation or oxidation of a conductive material film forming the gate pattern is prevented. A denser second dielectric film is then formed over the first dielectric film at a second temperature higher than the first temperature. The second and first dielectric film are then anisotropically etched in sequence to form bi-layered spacers on the side walls of the gate pattern, including the first and second dielectric films. Because the deformation of the conductive material film forming the gate pattern is suppressed by forming the first dielectric film at a low temperature, the resistance of the gate electrodes resulting from this fabrication process remains low.

Abstract: Sidewall spacers comprised of a second polycrystalline silicon film are formed on the sides of a first polycrystalline silicon film in such a way that a relationship of b≦a=x<c/2 is satisfied where x is the thickness of the sidewall spacers, a is a distance from the surface of the first insulating film to the surface of the first polycrystalline silicon film, b is the thickness of the second polycrystalline silicon film at a time of formation thereof and c is a distance between adjoining first polycrystalline silicon films.

Abstract: A process for forming a self-aligned contact, (SAC), structure, on an active device region in a semiconductor substrate, exposed at the bottom of a SAC opening in an insulator layer, has been developed. The process features increasing the area of the active device region, used to accommodate the overlying SAC structure, via the selective removal of the thick spacer component, of a composite spacer, located on the sides of silicon nitride capped, gate structures, performed after definition of a heavily doped source/drain region. The thick spacer component can be a polysilicon shape overlying a thin silicon oxide shape, or the thick spacer component can be a silicon oxide shape, overlying a silicon nitride shape.

Abstract: A method of fabricating a semiconductor device wherein a first material is provided on a first surface which has a surface and a sidewall. A sidewall structure of predetermined thickness, extending away from the sidewall, is formed with a second material different from the first material. The sidewall structure can be formed on a pair of adjacent sidewalls, the sidewall structure filling the space between the sidewall pair. Optionally, portions of the sidewall structure are removed and a second sidewall deposition of the same or different thickness can be added on exposed portions of the sidewall and the sidewall structure, thereby providing a disposition of different sidewall structure thickness. Additional portions of the sidewall structure can be removed. A third material different from the second material is formed covering exposed portions of the first surface, sidewall structure and first material. The first and third materials can be the same.

Abstract: A method of fabricating a silicide layer on a gate electrode is described. A gate oxide layer is formed on a substrate. A gate electrode is formed on a portion of the gate oxide layer. A spacer is formed on a sidewall of the gate electrode to cover the other portion of the gate oxide layer. The spacer is removed to expose a portion of the gate oxide layer. A metallic layer is formed over the substrate to cover the gate electrode and the gate oxide layer. An annealing step is performed to transform the metallic layer in contact with the gate electrode and the source/drain region into a silicide layer. The remaining metallic layer is removed.

Abstract: A semiconductor device and a method for fabricating the same are disclosed, in which floating body effect is reduced by applying a bias to a body in an SOI MOSFET. The semiconductor device includes first and second impurity ion implanting layers of a conductivity type formed in a semiconductor substrate having a buried oxide film and surface silicon layers thereon, first and second transistors of a conductivity type respectively formed on the first and second impurity ion implanting layers, having source/drain regions and a gate, trenches formed between the first and second transistors, single crystal silicon layers connected to any one of the source/drain regions of the respective transistors and the first and second impurity ion implanting layers at sides of the trenches, and carrier exhausting electrodes connected to the first and second impurity ion implanting layers at one sides of the respective transistors, for exhausting carrier generated by ionization impact in the respective transistors.

Abstract: A method for fabricating a self-aligned ultra short channel. The method uses double spacers as a hard mask, so that DRAM with the ultra short channel is formed in a self-aligned process. This method not only reduces the channel length, but also adjusts the dopants in lightly doped drains (LDD) at a side of the storage node opening and at the side of the bit line, respectively, so as to optimize the device property.

Abstract: A process for forming a vertical semiconductor device having increased source contact area comprises forming a gate and a well region in a silicon substrate. Using dopant of a second conductivity type, a shallow source region is formed in the well region, and a first oxide layer is deposited over the gate and the source and well regions. The first oxide layer of oxide is etched to form a first oxide on the substrate adjacent the gate, a thin nitride layer is deposited over the gate and source regions, and a second oxide layer is deposited over the nitride layer and etched to form a second oxide spacer separated from the first oxide spacer and substrate by the nitride layer. These spacers are used as a mask to selectively remove the thin nitride layer from the gate and substrate and portions of the gate polysilicon and source region and thereby form in the source region a recessed portion comprising vertical and horizontal surfaces.

Abstract: Semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable amorphous silicon spacers on the sidewalls of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the disposable spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface.