Abstract: A semiconductor processing method of forming a conductive polysilicon line relative to a substrate includes, a) providing a line of silicon on a substrate, the line having an outer top surface and outwardly exposed opposing outer sidewall surfaces, the line ultimately comprising conductively doped polysilicon; b) masking the line outer top surface with a masking material; c) with the masking material in place, depositing a metal layer atop the substrate and over the masking material and the outwardly exposed line outer sidewall surfaces; d) annealing the line to impart a silicidation reaction between the metal and opposing silicon sidewalls to form opposing metal silicide runners extending along the line sidewalls, the masking material preventing a silicidation reaction from occurring between the metal and line outer top surface; and e) stripping the metal layer from atop the line. Such a line is preferably used as a bottom gate for a thin film transistor.

Abstract: In accordance with the present invention, a method for forming a halo implant for semiconductor devices includes the steps of providing a substrate having a gate stack formed thereon. The gate stack includes a gate conductor. The gate stack extends a distance in a first direction on a surface of the substrate. Dopants of a first conductivity and dosage are provided at an acute angle relative to a normal to the surface of the substrate. The dopants are also directed at an angle of between about 30 degrees to about 60 degrees relative to the first direction such that the dopants are implanted below the gate conductor to form a halo implant for preventing current leakage for a semiconductor device.

Abstract: A fabrication method for a gate spacer. The method comprises provision of a substrate with a gate formed thereon, after which a SiNx spacer is formed on the gate sidewall. The substrate is then covered with a SiOx layer. A part of the SiOx layer is removed until the surface of the SiOx layer is lower than the top surface of the gate. A portion of the SiNx layer is removed to expose the top edge of the gate spacer and to increase the exposed area of the gate. The SiOx layer is consequently removed.

Abstract: A flash memory device and fabrication method simplify the fabrication process of a semiconductor EEPROM device through a self-aligning process. The device includes a semiconductor substrate in which source and drain regions are defined, a first insulation layer formed on the semiconductor substrate, a first conductive layer pattern formed on a portion of the first insulation layer, sidewall spacers formed of a second conductive layer neighboring each sidewall of the first conductive layer pattern and covered by second and third insulation layers, and a third conductive layer pattern formed on the insulation layers and connected with the first conductive layer pattern.

Abstract: A method for fabricating a semiconductor device according to the present invention can facilitate the device to be operated at a high speed by restricting an increase of a resistance of a gate electrode. The method for fabricating the semiconductor device includes a step of forming a gate insulation film on a semiconductor substrate, a step of forming a conductive film on the gate insulation film, a step of forming a conductive film post by patterning the conductive film, a step of forming a first silicide layer at sidewalls of the conductive film post, a step of forming a first impurity layer in the semiconductor substrate at both sides of the conductive film post, a step of forming a sidewall spacer beside the first silicide layer formed at the sidewalls of the conductive film post, and a step of forming a second impurity layer in the semiconductor substrate outside the sidewall spacer.

Abstract: After a gate insulating film, a gate electrode and an on-gate protective layer have been formed in this order on an Si substrate, lightly-doped source/drain regions are formed in the substrate. First and second sidewalls are formed on the sides of the gate electrode and then heavily-doped source/drain regions are formed by implanting dopant ions using these sidewalls as a mask. After the second sidewall has been selectively removed, pocket implanted regions are formed and an overall protective film is deposited. Thereafter, an interlevel dielectric film is deposited, contact holes are formed to reach the heavily-doped source/drain regions and then plug electrodes are formed. Since the second sidewall has already been removed when the overall protective film is deposited, the gap between adjacent gate electrodes is not completely filled in.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer of the first silicon layer and of the anti-reflection layer. A portion of the gate insulator layer is removed to have undercut spaces under the first silicon layer. A dielectric layer is then formed on the semiconductor substrate, on the sidewalls of the gate region, and within the undercut spaces. A spacer structure containing first type dopants is then formed on the sidewalls of the gate region. Following the removal of the anti-reflection layer, a second silicon layer containing second type dopants is formed over the semiconductor substrate and the first silicon layer.

Abstract: A non-volatile semiconductor memory device includes memory cells each having a duplicate gate structure in which a floating gate and a control gate are stacked.

Abstract: A method of fabricating a semiconductor device an object of which is to form a semiconductor device having a DMOS with high withstanding pressure and high driving capacity and a highly precise polycrystalline silicon resistor. In the method of fabricating a semiconductor device, by patterning a second polycrystalline silicon resistor using anisotropic etching, the size precision is improved. Further, during the patterning, side spacers are formed on gate electrode side walls formed of first polycrystalline silicon at the same time. The body of the DMOS is doped with the gate electrode and the spacers being the mask. A source region is doped with the gate electrode being the mask after the spacers are removed.

Abstract: A semiconductor process includes forming a spacer support structure on an upper surface of a semiconductor substrate. The semiconductor substrate includes a channel region that is laterally displaced between first and second source/drain regions. A. The spacer support structure includes a substantially vertical sidewall that is laterally aligned over a boundary between the first source/drain region and the channel region of the semiconductor substrate. A gate dielectric is then grown and a transistor gate fabricated by forming a first spacer structure on the sidewall of the spacer support structure. The first spacer structure includes a substantially vertical first sidewall in contact with the spacer support structure sidewall and further includes a second sidewall that is laterally aligned over a boundary between the channel region and the second source/drain region of the semiconductor substrate.

Abstract: A flash memory is disclosed including a second conductivity-type substrate having first conductivity-type first and second impurity regions spaced apart from each other by a predetermined distance; a second conductivity-type floating gate formed above part of the first impurity region; a first conductivity-type floating gate formed over the second conductivity-type floating gate; and an insulating layer and first conductivity-type control gate sequentially formed on the first conductivity-type floating gate.

Abstract: A method for fabricating complementary metal-oxide-semiconductor (CMOS) devices and circuits resulting therefrom are provided. The method includes forming the source and drain regions of the CMOS device by out-diffusion of ions injected into a conductive spacer. The method also includes forming the gate electrode after the source and drain regions have been activated by heat treatment. By forming the gate electrode after heat treating the source and drain regions, the material used to form the gate electrode is not distorted due to heat.

Abstract: An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, an MDD area and a heavy concentration source/drain area. Conversely, the PMOS transistor include an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provide lower source/drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.

Abstract: A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high adhesive strength to the gate insulating film is disposed. The polysilicon side wall (5) is brought into a close contact with the tungsten nitride (6b) on the side surface of the tungsten (6c). With this structure improved is adhesive strength of a metal wire or a metal electrode which is formed on an insulating film of a semiconductor device.

Abstract: A Metal Oxide Silicon Field Effect Transistor (MOSFET) and method includes a gate electrode pattern formed over a gate insulation layer on a semiconductor substrate. A pair of first impurity regions are respectively formed in an upper side surface of the substrate and adjacent to a side of the gate electrode pattern. A pair of first side wall spacers are respectively formed adjacent to a side wall of the gate electrode pattern, and a pair of air gaps are respectively formed between the gate electrode pattern and each of the side wall spacers. The MOSFET and method solve an increase problem of a fringing capacitor between a source and a gate electrode by forming an air gap along a side of the gate electrode. Further, a semiconductor chip area becomes decreased by forming a source and drain in a vertical structure. The source and drain formed of a side wall spacer further prevents a short channel effect from occurring. In addition, a cost reduction is achieved by adopting a self-alignment process.

Abstract: A method is provided for forming a split-gate flash memory cell having a sharp poly tip which substantially improves the erase speed of the cell. The poly tip is formed without the need for conventional oxidation of the polysilicon floating gate. Instead, the polysilicon layer is etched using a high pressure recipe thereby forming a recess with a sloped profile into the polysilicon layer. The recess is filled with a top-oxide, which in turn serves as a hard mask in etching those portions of the polysilicon year not protected by the top-oxide layer. The edge of the polysilicon layer formed by the sloping walls of the recess forms the sharp poly tip of this invention. The sharp tip does not experience the damage caused by conventional poly oxidation processes and, therefore, provides enhanced erase speed for the split-gate flash memory cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

Abstract: A semiconductor device having a reduced polysilicon gate electrode width is provided along with a process for manufacturing such a device. In accordance with the present invention, a semiconductor device may be formed by forming an oxidation-resistant barrier layer over a substrate. At least one polysilicon block is formed over the barrier layer. A dopant is implanted through the barrier layer into the substrate. The polysilicon block is oxidized to grow an oxide layer on exposed surfaces and thereby reduce the width of the block. The oxide layer then can be removed to form a gate electrode having a reduced width. Plural implantations and oxidation-removal can be carried out as desired.

Abstract: A method for forming a SAC opening is provided. As a self-aligned contact (SAC) opening is formed in a dielectric layer on a semiconductor substrate to expose one of source/drain regions in the substrate, a misalignment of the SAC opening may occur to expose a portion of the gate structure. The gate structure has a gate, which is covered by a cap layer on the top, a thin oxide layer on each sidewall of the gate and the cap layer, and a spacer on the thin oxide layer. The SAC opening causes a clearance between the spacer and the gate since a portion of the thin oxide layer is removed. The method contains forming an insulating layer over the substrate to fill the clearance. An etching back process is performed to remove the insulating layer so that a remaining portion of the insulating layer fills the clearance to fully isolate the gate.

Abstract: A gate electrode comprises a conductive gate electrode body and gate side walls. The channel region beneath the gate electrode has an NUDC structure having a p.sup.- impurity region and p.sup.+ impurity regions. The p.sup.- impurity region is formed before the gate electrode body. After the formation of the gate electrode body, the p.sup.+ impurity regions are formed by ion implantation before the gate side walls. The ion implantation is carried out perpendicular to the substrate so that the implanted ions will not reach further around the center of the channel region. Of the gate oxide films over the channel region, the thickness of the gate oxide films at both ends of the channel region is thinner than that of the gate oxide film in the middle of the channel length so as to suppress lowering of the current drivability.

Abstract: A layer of polysilicon is deposited over an oxide layer on top of a silicon substrate, with core field oxide and active regions, and patterned. An oxide mask is then added. Next, the oxide mask and the layer of polysilicon are removed from above the core field oxide regions. Next, a second layer of polysilicon is deposited and etched to form polysilicon spacers. Later, an ONO dielectric, a third polysilicon layer, a tungsten silicide layer, and SiON layers are successively formed and patterned. The polysilicon spacers effectively seal any recesses that may occur in the edges of the first polysilicon layer to prevent harboring of subsequently added polysilicon material. Accordingly, NAND-type flash memory core cells cannot be electrically shorted by polysilicon material, so called "polystringers", present in such recesses.

Abstract: A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions and central conductive portion. The edge conductive portions provide high potential barriers against the active regions, thereby reducing threshold voltage roll off and leakage current.

Abstract: Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays.

Abstract: A split-gate source side injection flash memory structure that utilizes the polysilicon spacers formed on the sidewalls of the control gate and the floating gate, and the difference in concentration and depth between the source region and the drain region. By applying suitable operating voltage to the polysilicon spacers above the respective source region and drain region, operation of the flash memory can be properly controlled. Because a source-side injection is obtained in this invention, hence a higher programming efficiency is achieved.

Abstract: A method to form a "mushroom shaped" gate structure 18 22 44A 70 that increases the top gate silicide contact area and improves the salicide process, especially TiSi.sub.2 salicide. The novel upper gate extensions 44A increase the top gate surface area so that the silicide gate contacts 70 will have a low resistivity. The invention includes forming a gate stack 18 22 26 comprised of a gate oxide layer 18, a center gate portion 22 and a hard mask 26. Next, we form a first insulating layer 40 over the gate stack 22 26 18. The hard mask 26 and a first thickness of the first insulating layer 40 are removed to expose sidewalls of the center gate portion 22. A second conductive layer 44 is formed over the first insulating layer 46 and the center gate portion 22. The second conductive layer 44 is etched to form critical rounded upper gate extensions 44A on the sidewalls of the center gate portion 22. Lower rectangular sidewall spacers 52 are formed on the sidewalls of the center gate portion 22.

Abstract: An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. A mask is formed, from a material resistant to oxidation, upon a conductive gate layer and portions of the conductive gate layer are oxidized to form a gate conductor laterally disposed between a pair of oxide regions. As a result, the gate conductor has an ultra narrow lateral dimension. Source and drain impurity areas are formed self-aligned with sidewall surfaces of the oxide regions. In an embodiment, the oxide regions are removed and lightly doped drain regions are formed self-aligned with sidewall surfaces of the gate conductor. Following LDD formation, the mask is removed, spacers are formed laterally adjacent the gate conductor sidewall surfaces, and a metal silicide is formed upon upper surfaces of the gate conductor and the source and drain impurity areas.

Abstract: Process for forming physical gate length dependent implanted regions in a semiconductor substrate. The process includes steps of first providing a semiconductor substrate (e.g. a silicon wafer) with a gate oxide layer on its surface, followed by the formation of a polysilicon gate layer on the gate oxide layer. An additional oxide layer is subsequently formed on the polysilicon gate layer. The resulting oxide/polysilicon stack is then patterned to form a patterned oxide/polysilicon stack layer that includes a patterned additional oxide layer and a patterned polysilicon gate layer. Next, a conformal silicon nitride layer is formed over the patterned oxide/polysilicon stack layer. The conformal silicon nitride layer is then etched (e.g. by an anisotropic etch) to form silicon nitride spacers on the sidewalls of the patterned oxide/polysilicon stack layer.

Abstract: A method for making a self-aligned isolated flash memory core without damaging tunnel oxide layers between memory element stacks and the silicon substrate supporting the stacks includes depositing three sidewall layers on the stacks, prior to etching isolation trenches between the stacks, to thereby shield the tunnel oxide during isolation trench etching.

Abstract: A multiple LOCOS (local oxidation) process shapes a surface of a substrate to form a series of planar regions which are vertically separated from each other. One exemplary process forms a hard mask layer for each LOCOS operation. Another exemplary process includes forming a silicon nitride mask layer and repeatedly changing the pattern of that mask layer. Each change in the pattern corresponds to a planar region to be formed; and after each change, oxide is grown in openings through the mask layer. The growth of oxide consumes part of the substrate and provides a vertical separation between the planar level corresponding to the pattern and a next higher planar level. Regions of the substrate once exposed by a mask pattern can remain exposed so that subsequent LOCOS operations maintain previously established separations between levels. A hard mask layer can include a polysilicon layer which protect a silicon nitride layer from conversion to oxide during the repeated LOCOS operations.

Abstract: An insulating film is formed on the surface of the base of a semiconductor, and a portion of the insulating film is removed to cause the surface to appear outside. The exposed surface is terminated with hydrogen, and then energy beams are applied to selectively remove the terminating hydrogen. Metal is selectively deposited on the portion terminated with left hydrogen atoms.

Abstract: A field effect transistor which is not susceptible to mask edge detects at its gate spacer oxides. The transistor is formed upon a semiconductor substrate through successive layering of a gate oxide, a gate electrode and a gate cap oxide. A pair of curved gate spacer oxides are then formed covering opposite edges of the stack of the gate oxide, the gate electrode and the gate cap oxide. The semiconductor substrate is then etched to provide a smooth topographic transition from the gate spacer oxides to the etched semiconductor surface. Source/drain electrodes are then implanted into the etched semiconductor substrate and annealed to yield the finished transistor. A second embodiment of the field effect transistor possesses a polysilicon gate. Alter removal of the gate cap oxide, a metal layer may be deposited and sintered upon the polysilicon gate and the source/drain electrodes. The metal salicide layers formed upon the electrodes of the transistor have limited susceptibility to parasitic current leakage.

Abstract: A gate conductor structure and method for forming the structure are provided whereby the overall gate length can be made with less susceptibility to lithography variations. The gate conductor is produced by defining a sidewall surface region and then forming the gate conductor material on that sidewall surface a closely controlled, defined lateral distance therefrom. The gate conductor length is therefore dependent primarily upon deposition technology rather than both deposition and lithography. Deposition can be controlled at the defined sidewall surface more closely than mask alignment, thin film development and etching processes of conventional designs. The gate conductor is formed from the sidewall surface such that the sidewall surface demonstrates a greater likelihood of forming a thicker sidewall spacer on one surface of the gate conductor than the opposing gate conductor surface.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, a portion of the first silicon layer, and a portion of the anti-reflection layer. A shield layer is then formed over the semiconductor substrate, on the gate insulator layer, and on the first silicon layer. A spacer structure containing first conductivity type dopants is then formed on the gate region. Following the removal of the anti-reflection layer, a second silicon layer containing second conductivity type dopants is formed over the semiconductor substrate and the first silicon layer. Finally, a thermal process is performed to the semiconductor substrate for diffusing the first conductivity type dopants and the second conductivity type dopants into the semiconductor substrate.

Abstract: Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.

Abstract: Semiconductor memory device and method is provided for a stacked gate type flash semiconductor memory device. The semiconductor memory device improves programming and erasing operation efficiency. A gate oxide layer and a floating gate are formed to be stacked on a substrate. A first dielectric layer and a control gate are formed to be stacked on the floating gate. A second dielectric layer is formed on both sides of the floating gate and first and second semiconductor sidewalls are formed on the second dielectric layer on the both sides of the floating gate. Impurity regions are formed in the substrate at the both sides of the floating gate and a wire layer is formed to contact with the semiconductor sidewalls and each of the impurity regions.

Abstract: The method includes forming a gate oxide on a substrate. A stacked-amorphous-silicon (SAS) layer is then formed on the gate oxide. An anti-reflective coating (ARC) layer is formed on the SAS layer. Next, a gate structure is patterned by etching. A silicon oxynitride layer is formed on the substrate, and covered the gate structure. A BSG sidewall spacers are formed on the side walls of the gate structure. A selective epitaxial silicon is grown on the substrate by using ultra high vacuum chemical vapor deposition. Then, an ARC layer is removed to expose the top of the SAS layer. Then, a blanket ion implantation is carried out to implant p type dopant into the SAS layer, the epitaxial silicon and silicon substrate. A SALICIDE layer, a polycide layer are respectively formed on the SAS layer and the epitaxial silicon. Further, the extended source and drain are formed in the step. A thick oxide layer is formed over the substrate and gate structure for isolation. Then, contact holes are generated in the oxide layer.

Abstract: An insulated gate semiconductor device (10) having a gate structure (45) that includes a conductive spacer (32) and an extension region (46) extending from the conductive spacer (32). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate dielectric (23) is then formed over the major surface (12) adjacent to the sidewalls (22). The conductive spacer (32) is formed on the gate dielectric (23). The extension region (46) is then formed using selective growth or deposition and patterning of polysilicon adjacent the conductive spacer (32).

Abstract: An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.

Abstract: The present invention has the object of offering a semiconductor production method which simplifies the fabrication of gate electrodes for MOS-type semiconductor elements and allows a high yield to be maintained. For this purpose, it has steps of forming a field-shield gate insulation film on a semiconductor substrate, forming polycrystalline silicon films having an etching rate which is greater at an upper side than a lower side thereon, and etching the polycrystalline silicon films under conditions which allow for side etching with the silicon oxide film as a mask, so as to make gradually tapered inclines on side walls of field-shield gate electrode.

Abstract: A non-volatile memory having a control gate (14) and a sidewall select gate (28) is illustrated. The sidewall select gate (28) is formed in conjunction with a semiconductor doped oxide (20) to form a non-volatile memory cell (7). The semiconductor element used to dope the oxide layer (20) will generally include silicon or germanium. The non-volatile memory cell (7) is programmed by storing electrons in the doped oxide (20), and is erased using band-to-band tunneling.

Abstract: A differential amplifier (10) includes three unilateral field effect transistors (12, 14, 16) formed in a common well (40) of a semiconductor material. Each of the three unilateral field effect transistors (12, 14, 16) has an asymmetric channel doping profile. The performance of the differential amplifier (10) is significantly improved by properly orienting the three unilateral field effect transistors (12, 14, 16).

Abstract: A semiconductor processing method of forming a conductive polysilicon line relative to a substrate includes, a) providing a line of silicon on a substrate, the line having an outer top surface and outwardly exposed opposing outer sidewall surfaces, the line ultimately comprising conductively doped polysilicon; b) masking the line outer top surface with a masking material; c) with the masking material in place, depositing a metal layer atop the substrate and over the masking material and the outwardly exposed line outer sidewall surfaces; d) annealing the line to impart a silicidation reaction between the metal and opposing silicon sidewalls to form opposing metal silicide runners extending along the line sidewalls, the masking material preventing a silicidation reaction from occurring between the metal and line outer top surface; and e) stripping the metal layer from atop the line. Such a line is preferably used as a bottom gate for a thin film transistor.

Abstract: A novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories includes a polyspacer floating gate. The EEPROM structure also includes a select gate covering a part of the channel of the EEPROM cell, with a polysilicon spacer adjacent to the select gate. The polysilicon spacer implements a floating gate that holds charge to program the EEPROM cell. In one embodiment, a isolation layer separates the select gate and the floating gate. The isolation layer and the floating gate extends over the remaining part of the channel. A second isolation layer is formed over select gate and the floating gate. A control gate is formed on the isolation layer. Between the drain and the control gate is the second isolation layer. A lightly doped drain (LDD) structure is formed at the drain adjacent.

Abstract: On a silicon substrate in which boron (B) has been introduced, an n.sup.+ polysilicon film and a tungsten silicide film are sequentially deposited, with a gate oxide film being interposed between the substrate and the polysilicon film, to form a gate electrode. A sidewall of p.sup.+ polysilicon is formed at each side of said gate electrode. A source/drain diffusion layer of an n.sup.+ region is self-aligned with a side edge portion of the gate electrode including the sidewall. The formation of the sidewall is performed after the source/drain diffusion layers have been formed using a dummy sidewall. The gate structure thus formed has a steep potential gradient in the lateral direction of channel region. In the field effect transistor thus formed, the short channel effect is efficiently suppressed.

Abstract: A method for fabricating a CMOSFET includes the steps of forming a first well of a first conduction type and a second well of a second conduction type on a substrate of the first conduction type; forming gate electrodes having sides on the first well and the second well; forming semiconductor sidewall spacers of the first conduction type at the sides of the gate electrodes; forming a semiconductor layer of the second conduction type over the first well; implanting impurity ions of the first conduction type into the second well; and annealing the semiconductor substrate to form lightly doped shallow impurity regions of the first conduction type in the first and second wells under the semiconductor sidewall spacers, and heavily doped deep impurity regions of the second conduction type in the first well, and simultaneously activating the impurity ions in the second well to formed heavily doped deep impurity regions of the first conduction type in the second well.

Abstract: Method for creating a doped polysilicon layer of accurate shape on a sidewall of a semiconductor structure. According to the present method, a doped polysilicon film covering at least part of said semiconductor structure and of said sidewall is formed. This polysilicon film then undergoes a reactive ion etching (RIE) process providing for a high etch rate of said polysilicon film to approximately define the shape of the polysilicon layer on said sidewall. Then, said polysilicon film undergoes a second reactive ion etching process. This second reactive ion etching process is a low polysilicon etch rate process such that non-uniformities of the surface of said polysilicon film are removed by sputtering.

Abstract: A semiconductor device (83)including a transistor (85) with a nonuniformly doped channel region can be formed with a relatively simple process without having to use high dose implants or additional heat cycles. In one embodiment, a polysilicon layer (14) and silicon nitride layer (16) are patterned at the minimum resolution limit. The polysilicon layer is then isotropically etched to form a winged gate structure (32). A selective channel implant step is performed where ions are implanted through at least one of the nitride wings of the winged gate structure (32) but are not implanted through the polysilicon layer (14). Another polysilicon layer (64)is conformally deposited and etched such that the polysilicon (74) does not extend beyond the edges of the nitride wings.

Abstract: Methods of forming field effect transistors having oxidation-controlled gate lengths include the steps of forming an insulated gate electrode on a face of semiconductor substrate. The gate electrode has exposed ends thereof which define an initial gate length. Source and drain region dopants are then implanted into first portions of the face, using the insulated gate electrode as an implant mask. The implanted first portions of the face and the exposed ends of the insulated gate electrode are then thermally oxidized to form a relatively thick oxide layer. During this step, the implanted dopants are diffused and bird's beak oxide extensions are formed at the upper and bottom corners of the gate electrode. The bird's beak oxide extensions are preferably formed to increase the separation distance between the gate electrode and the source and drain regions and thereby reduce the gate-source/drain capacitance and inhibit parasitic hot electron injection from the drain region.

Abstract: A method for forming an asymmetrical LDD structure is described. A polysilicon gate electrode is formed overlying a layer of gate silicon oxide on the surface of a semiconductor substrate. The surfaces of the semiconductor substrate and the gate electrode are oxidized to form a surface oxide layer. Polysilicon spacers are formed on the sidewalls of the gate electrode wherein one side of the gate electrode is a source side and the other side of the gate electrode is a drain side. The polysilicon spacer on the source side of the gate electrode is removed. First ions are implanted to form heavily doped source and drain regions within the semiconductor substrate not covered by the gate electrode and the polysilicon spacer on the drain side of the gate electrode. Then the drain side polysilicon spacer is removed.

Abstract: A gate-drain overlapped device, comprising: a first conductive type substrate; a gate insulating film formed on the substrate; a gate comprising a gate conductive line patterned on the gate insulating film, and a conductive layer coated on the gate conductive line and extending to a predetermined length on the gate insulating film; and a drain/source region comprising a second conductive type low density diffusion region in the substrate below the extending area of the conductive layer and a second conductive type high density diffusion region in contact with the low density diffusion region in the substrate, which is significantly improved in the resistance of a polysilicon gate conductive line and in uniform electrical properties.

Abstract: A method for making a variable length LDD spacer structure is disclosed. A first insulation layer (i.e., gate oxide) is formed on a semiconductor device having a P-well and an N-well provided in a substrate. A first and a second polysilicon gate are formed on the P-well and the N-well respectively wherein the first insulation layer is interposed between the wells and the gates. A second insulation layer is formed over the first and second gates. N-type impurity ions are selectively implanted to form lightly doped N-type diffusion regions in the P-well. Similarly, P-type impurity ions are selectively implanted to form lightly doped P-type diffusion regions in the N-well. A polysilicon spacer is formed on both side walls of each of the gates. Each spacer covers a portion of the lightly doped N-type and P-type diffusion regions. N-type impurity ions are selectively implanted in a portion of the lightly doped N-type diffusion regions not covered by the spacers.