Abstract: An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400° C. to 600° C.

Abstract: Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided.

Abstract: A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed.

Abstract: A SiC Schottky barrier diode (SBD) is provided having a substrate and two or more epitaxial layers, including at least a thin, lightly doped N-type top epitaxial layer, and an N-type epitaxial layer on which the topmost epitaxial layer is disposed. Multiple epitaxial layers support the blocking voltage of the diode, and each of the multiple epitaxial layers supports a substantial portion of the blocking voltage. Optimization of the thickness and dopant concentrations of at least the top two epitaxial layers results in reduced capacitance and switching losses, while keeping effects on forward voltage and on-resistance low. Alternatively, the SBD includes a continuously graded N-type doped region whose doping varies from a lighter dopant concentration at the top of the region to a heavier dopant concentration at the bottom.

Abstract: An SiC semiconductor device is provided, which comprises: a substrate made of silicon carbide and having a principal surface; a drift layer made of silicon carbide and disposed on the principal surface; an insulating layer disposed on the drift layer and including an opening; a Schottky electrode contacting with the drift layer through the opening; a termination structure disposed around an outer periphery of the opening; and second conductivity type layers disposed in a surface part of the drift layer, contacting the Schottky electrode, surrounded by the termination structure, and separated from one another. The second conductivity type layers include a center member and ring members. Each ring member surrounds the center member and is arranged substantially in a point symmetric manner with respect to the center member.

Abstract: A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.

Abstract: Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT).

Abstract: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the creation of a new class of solid state chemical sensors. Detention of the following chemical species was established: hydrogen, deuterium, carbon monoxide, and molecular oxygen. The detector (1b) consists of a Schottky diode between an Si layer and an ultrathin metal layer with zero force electrical contacts.

Abstract: A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.

Abstract: A method of forming an ohmic contact on a substrate composed of a wide-band gap semiconductor material includes: depositing a transition metal group metal on the substrate; annealing the substrate at a high temperature to cause a solid state chemical reaction between the substrate and the deposited metal that forms a modified layer in the substrate having modified properties different than the substrate, and by-products composed of a silicide and a nanocrystalline graphite layer; selectively etching the substrate to remove one or more of the by-products of the solid state chemical reaction from a surface of the substrate; and depositing a metal film composed of a transition group metal over the modified layer on the substrate to form the ohmic contact. The modified layer permits formation of the ohmic contact without high temperature annealing after depositing the metal film.

Abstract: A semiconductor device has an active region composed of a group III–V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.

Abstract: A method for producing a light-emitting semiconductor component having a thin-film layer sequence (14), in which a photon-emitting active zone (17) is formed. The thin-film layer sequence (14) is formed on a growth substrate. A reflection contact layer (40) is formed having contact with the thin-film layer sequence. A diffusion barrier layer (42) is applied to the reflection contact layer (40), and a solder contact layer (44) is applied to the diffusion barrier layer (42). The reflection contact layer (40), after it has been formed and before the diffusion barrier layer (42) is applied, is subjected to heat treatment for the purpose of producing an ohmic contact, and the surface of the reflection contact layer (40) is cleaned with a first etching solution after the heat treatment. As an alternative, the reflection contact layer (40) is subjected to heat treatment after the application of the solder contact layer (44) to the diffusion barrier layer (42) for the purpose of producing an ohmic contact.

Abstract: A method for passivating a III-V material Schottky layer of a field effect transistor. The transistor has a gate electrode in Schottky contact with a gate electrode contact region of the Schottky layer. The gate electrode is adapted to control a flow of carriers between a source electrode of the transistor and a drain electrode of such tarnsistor. The transistor has exposed surface portions of the Schottky layer beween the source electrode and the drain electrode adjacent to the gate electrode contact region of the Schottky layer. The method includes removing organic contamination from the exposed surface portions of the Schottky layer using a oxygen plasma. The contamination removed surface portions of the Schottky layer are exposed to a solution of ammonium sulfide and NH4OH. After removal of the solution, the exposed regions are dried in a nitrogen enviroment. A layer of passivating material is deposited over the dried surface portions.

Abstract: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

Abstract: A process and related product in which ohmic contacts are formed in High Electron Mobility Transistors (HEMTs) employing compound substrates such as gallium nitride. An improved device and an improvement to a process for fabrication of ohmic contacts to GaN/AlGaN HEMTs using a novel two step resist process to fabricate the ohmic contacts are described. This novel two-step process consists of depositing a plurality of layers having compounds of Group III V elements on a substrate; patterning and depositing a first photoresist on one of the layers; etching recessed areas into this layer; depositing ohmic metals on the recessed areas; removing the first photoresist; patterning and depositing a second photoresist, smaller in profile than the first photoresist, on the layer; depositing more ohmic metal on the layer allowing for complete coverage of the recessed areas; removing the second photoresist, and annealing the semiconductor structure.

Abstract: A semiconductor device and a manufacturing method therefor are provided, the semiconductor device having a good reverse recovery characteristic, and having no reduction in breakdown voltage because no defect occurs in the upper main surface of a Si substrate even when wires are bonded onto an anode electrode. A semiconductor device includes a Si substrate including an N+ cathode layer and an N? layer. An impurity such as platinum whose barrier height is less than that of silicon is introduced into upper regions of the N? layer where P anode layers are not formed, thereby forming Schottky junction regions. A barrier metal is formed between the Si substrate and an anode electrode.

Abstract: A method of epitaxially growing backward diodes and diodes grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n junction in order to steepen the voltage drop at the junction, and thereby increase the electric field. By tailoring the p and n doping levels as well as adjusting the thin, highly doped layer, backward diodes may be consistently produced and may be tailored in a relatively easy and controllable fashion for a variety of applications. The use of the thin, highly doped layer provided by the present invention is discussed particularly in the context of InGaAs backward diode structures, but may be tailored to many diode types.

Abstract: A Schottky barrier diode and process of making is disclosed. The process forms a metal contact pattern in masked areas on a silicon carbide wafer. A preferred embodiment includes on insulating layer that is etched in the windows of the mask. An inert edge termination is implanted into the wafer beneath the oxide layer and adjacent the metal contacts to improve reliability. A further oxide layer may be added to improve surface resistance to physical damage.

Abstract: A high electron mobility transistor is constructed with a substrate, a lattice-matching buffer layer formed on the substrate, and a heavily doped p-type barrier layer formed on the buffer layer. A spacer layer is formed on the barrier layer, and a channel layer is formed on the spacer layer. The channel layer may be of uniform composition, or may be made from two or more sublayers. A Schottky layer is formed over the channel layer, and source and drain contacts are formed on the Schottky layer. The substrate may be gallium arsenide, indium phosphide, or other suitable material, and the various semiconductor layers formed over the substrate contain indium. The transistor's transition frequency of the transistor is above 200 GHz.

Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.

Abstract: A method for manufacturing a hetero-junction field effect transistor (HFET) device, which includes sequentially forming a non-doped GaN semiconductor layer and an AlGaN semiconductor layer on a substrate, separating devices from each other by etching the substrate, forming a photoresist layer pattern on the AlGaN semiconductor layer and forming gate electrodes by depositing a material on the substrate using the photoresist layer pattern, treating the surface of the AlGaN semiconductor layer, and forming a photoresist layer pattern on the substrate and forming ohmic electrodes by depositing a metal on the substrate using the photoresist layer pattern, is provided. Accordingly, it is possible to overcome a difficulty in aligning the gate electrode with the ohmic electrodes and prevent a substrate from having a step difference introduced by the ohmic electrodes because the gate electrode is formed before the ohmic electrodes are formed.

Abstract: A method for passivating a III-V material Schottky layer of a field effect transistor. The transistor has a gate electrode in Schottky contact with a gate electrode contact region of the Schottky layer. The gate electrode is adapted to control a flow of carriers between a source electrode of the transistor and a drain electrode of such transistor. The transistor has exposed surface portions of the Schottky layer beween the source electrode and the drain electrode adjacent to the gate electrode contact region of the Schottky layer. The method includes removing organic contamination from the exposed surface portions of the Schottky layer using a oxygen plasma. The contamination removed surface portions of the Schottky layer are exposed to a solution of ammonium sulfide and NH4OH. After removal of the solution, the exposed regions are dried in a nitrogen enviroment. A layer of passivating material is deposited over the dried surface portions.

Abstract: A Thin Film Transistor (TFT) manufacture method, comprising manufacture of a gate, a gate isolation layer, a channel layer, and a source/drain. Wherein, the manufacture of the channel layer comprises: forming a first a-Si layer by using a low deposition rate (LDR) (Chemical Vapor Deposition, CVD); forming a second a-Si layer by using a high deposition rate (HDR); and forming an N+Mixed a-Si layer. When the first a-Si layer is formed in the present invention, the flux ratio of H2/SiH4 is adjusted to a range from 0.40 to 1.00 to increase the number of defects in the first a-Si layer. When the TFT is irradiated by the light, the photo leakage current generated in the channel layer is trapped in the defects in the first a-Si layer. Therefore, the TFT photo leakage current can be significantly reduced.

Abstract: The proposed invention is related to a method for forming a gate with metal silicide. In short, the proposed method comprises the following steps: providing a substrate; forming a first dielectric layer on the substrate; forming a polysilicon layer on the first dielectric layer; forming a metal silicide layer on the polysilicon layer; forming a second dielectric layer on the metal silicide layer; etching the second dielectric layer, the metal silicide layer, the polysilicon layer and the first dielectric layer to form a gate; performing a thermal nitridation process to form a metal nitride layer on the sidewall of the metal silicide layer; and performing a thermal oxidation process to eliminate edge defects.

Abstract: The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source of at least one transistor of a field effect transistor integrated circuit. The use of one or more Schottky barriers is useful for reducing the susceptibility of latch-up for circuits having two opposite type transistors, i.e., two opposite polarity carriers, in which the two transistors are in close enough proximity to experience latch-up. This can allow the spacing between n- and p-type transistors to be reduced, thus reducing the area of the circuit. The subject invention can also allow the elimination of a metal contact by utilizing the metal layer used to form the metal-semiconductor junction in a complementary IGFET structure, to further reduce the circuit area. The subject invention is applicable to complementary metal oxide silicon (CMOS) devices.

Abstract: A high electron mobility transitor has a channel layer overlain by an electron supply layer held in contact with a gate electrode, and source/drain electrodes form ohmic contact together with cap layers, and resistive etching stopper are inserted between the cap layers and the electron supply layers for preventing the electron supply layer from over-etching, wherein extremely thin delta-doped layers are formed between the etching stopper layers and the electron supply layer so that the resistance between the electron supply layer and the source/drain electrodes are reduced.

Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.

Abstract: A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide.

Abstract: On an In-containing compound semiconductor are sequentially formed Zn (p-type dopant-containing layer), Ta (high-melting metal layer) and a low-resistance conductor layer in this order as a Schottky electrode, and the resulting assemblage is annealed to diffuse Zn into the semiconductor to thereby convert the surface of the semiconductor layer only in a region in contact with the Schottky electrode metal into a p-type layer. The p-type dopant-containing layer can be, instead of Zn, a compound between Zn and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy. The high-melting metal layer can be, instead of Ta, an intermetallic compound between Ta and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy.

Abstract: In a semiconductor device, a first semiconductor layer is formed on a semiconductor substrate. A second semiconductor layer is formed on a part of the first semiconductor layer, and a third semiconductor layer is formed on a part of the second semiconductor layer. A first electrode is formed on the third semiconductor layer, and a second electrode is formed on the first semiconductor layer in contact with the second semiconductor layer and apart from the semiconductor layer, thus forming a diode.

Abstract: A method of making a flat capacitor includes forming at least one recess on an inside surface of a metal foil blank, leaving a surrounding peripheral flange. A coating performing as an electrode of the capacitor is applied to the inside surface of the metal foil blank and an ion-permeable separator is placed on that inside surface of the metal foil blank. A substantially planar anode with a protruding lead is placed in the recess with the lead extending through a hole of the metal foil blank. Thereafter, the metal foil blank is folded along a line intersecting the hole so that the anode is sandwiched between parts of the separator and the separator is in contact with the coating on the inside surface of the metal foil blank. In the folding process, parts of the peripheral flange of the metal foil blank are brought into contact with each other and these parts are sealed to each other to form a hermetically sealed metal foil case of the capacitor.

Abstract: A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage.

Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

Abstract: Metallic films are formed on a silicon substrate on which an insulation film and a conductive portion are exposed. The metallic films include a first metallic film directly contacting the insulation film and the conductive portion and a second metallic film disposed on the first metallic film as a stress adjustment film to control a stress at an interface between the first metallic film and the underlying member. Accordingly, an adhesion between the first metallic film and the insulation film can be controlled to be smaller than that between the first metallic film and the conductive portion. Then, the metallic film is removed from the insulation film by an adhesive sheet selectively while remaining on the conductive portion. As a result, the metallic film can be patterned stably and readily at low cost.

Abstract: An electrical contact for a silicon carbide component comprises a material that is in thermodynamic equilibrium with silicon carbide. The electrical contact is typically formed of Ti3SiC2 that is deposited on the silicon carbide component.

Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: A method of forming a fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET). The method includes forming a T-shaped gate electrode formed at least in part in a recess formed in a layer of semiconductor material and over a body region that is disposed between a source and a drain. The method includes spacing the gate electrode from the body by a gate dielectric made from a high-K material.

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Abstract: A MESFET has a conduction channel provided with a first doping profile in a first portion which extends between the source and the gate, and a second doping profile in a second portion which extends between the gate and the drain. A background p-type region is provided beneath the first portion, but not necessarily behind the second portion.

Abstract: Method and apparatus are provided for a semiconductor device including a junction and contact having a diffusion barrier to control silicidation of a silicon substrate. A dopant is applied in excess of an amount required to form a junction and the dopant chemically reacts with a metal to form a compound which serves as a barrier layer to prevent silidication in the substrate.

Abstract: A method for isolating a source and a drain in an MOS transistor by forming an insulation layer adjacent to the source and an insulation layer adjacent to the drain, and an apparatus produced from such a method.

Abstract: Methods are provided for producing a compound semiconductor substrate including: a mica substrate; and a III-V group compound semiconductor layer containing nitrogen as its main component grown on the mica substrate.

Abstract: This invention describes an improved method of making electrical contact to porous silicon using intercalated conductive materials. The intercalation process may use gaseous, liquid or solid components to form conductive contacts to the silicon structures of the porous silicon. The intensity of the light emitted by porous silicon layers and devices can therefore be increased by the improved electrical interconnection between the mechanically, chemically and thermally fragile porous silicon and the device electrodes. The intercalation process uses conductive materials that interpenetrate the structures of the porous silicon thereby providing the improved electrical properties. Increasing the surface area over which electrical contact is made increases the junction area which allows increased electrical current flow across the junction. The increased electrical current flow across the junction provides an increased number of electrical charge carriers undergoing radiative recombination.

Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1˜1016 to 1˜1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer. Otherwise, in the steps of manufacturing the high electron mobility field effect transistor, after a silicon nitride film has been formed on a GaAs buried layer in which a second recess is formed and in a region on the inside of a first recess formed in a GaAs contact layer, the GaAs buried layer is still heated.

Abstract: A component is produced on a substrate made of SiC. The component has at least one ohmic contact and at least one Schottky contact. The component is brought to a temperature of more than 1300° C. at least during the growth of an epitaxial layer. To ensure that the production of the ohmic contact does not lead to impairment of other structures on the component and that the ohmic contact, for its part, is insensitive with respect to later method steps at high temperatures, the first metal is applied to the substrate for the ohmic contact before the epitaxial layer is grown.

Abstract: A method for manufacturing a light-emitting device which using group III nitride group semiconductors and a quantum well structure, comprising forming a well layer (e.g. an InGaN layer), forming a cap layer on the well layer, the cap layer having almost the same compositions as the well layer at a temperature similar to that at which the well layer was formed. Further, and the cap layer is formed at a crystal growth rate which is faster than the crystal growth rate of the well layer and removing the cap layer using a thermal cracking (or decomposition) process during the temperature ramp up associated with the formation of the next group III nitride compound semiconductor layer. After the cap layer is removed, the group III nitride compound semiconductor layer is formed on the exposed well layer.

Abstract: A vertical Schottky diode including an N-type silicon carbide layer of low doping level formed by epitaxy on a silicon carbide substrate of high doping level. The periphery of the active area of the diode is coated with a P-type epitaxial silicon carbide layer. A trench crosses the P-type epitaxial layer and penetrates into at least a portion of the height of the N-type epitaxial layer beyond the periphery of the active area. The doping level of the P-type epitaxial layer is chosen so that, for the maximum voltage that the diode is likely to be subjected to, the equipotential surfaces corresponding to approximately ¼ to ¾ of the maximum voltage extend up to the trench.

Abstract: When a device using GaN semiconductors is made on a hard and chemically stable single-crystal substrate such as sapphire substrate or SiC substrate, a semiconductor device and its manufacturing method ensure high-power output or high-frequency operation of the device by thinning the substrate or making a via hole in the substrate. When a light emitting device using GaN semiconductors is made on a non-conductive single-crystal substrate such as sapphire substrate, the semiconductor device and its manufacturing method reduce the operation voltage of the light emitting device by making a via hole to the substrate. More specifically, after making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less.