Abstract: A component is produced on a substrate made of SiC. The component has at least one ohmic contact and at least one Schottky contact. The component is brought to a temperature of more than 1300° C. at least during the growth of an epitaxial layer. To ensure that the production of the ohmic contact does not lead to impairment of other structures on the component and that the ohmic contact, for its part, is insensitive with respect to later method steps at high temperatures, the first metal is applied to the substrate for the ohmic contact before the epitaxial layer is grown.

Abstract: A bilayer interlayer dielectric having a spun-on low k gap filled layer is capped with a higher k dielectric layer. Prior to the capping, the spun-on low k dielectric layer is planarized to reduce or eliminate the systematic variation in the relative thickness of the layers due to pattern density effects on the thickness of the spun-on low k dielectric layer. By removing the variations in the relative thickness of the low k dielectric layer and the capping layer, the effective dielectric constant of the uniformly thick composite interlayer dielectric is independent of location on the circuit, preventing differences in circuit speed and the creation of clock skew in the circuit.

Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.

Abstract: A semiconductor device has an improved schottky barrier junction. The device includes: a substrate; an epitaxial layer covering the substrate and lightly doped with a dopant selected from a group consisting of a rare earth element and an oxidant of a rare earth element; and a metal layer covering the epitaxial layer and forming said schottky barrier junction with said epitaxial layer.

Abstract: A III-V semiconductor structure and it producing method is provided. The method for forming a III-V semiconductor structure having a Schottky barrier layer includes the steps of (a) providing a III-V substrate, (b) treating the first barrier layer with a sulfuric acid solution, (c) forming a Schottky barrier layer on the III-V substrate, and (d) forming a metal layer on the second barrier layer. The Ill-V semiconductor structure includes a III-V substrate, a Schottky barrier layer, and a metal layer. The Schottky barrier layer is made of Al2(SO4)3 and In2(SO4)3.

Abstract: Group III-V composites, which is used to manufacture Schottky contacts having the characteristics of higher energy gap, higher carriers mobility, etc., are applied for manufacturing high-speed devices. Therefore, in there years, Group III-V composite Schottky contacts are continuously being developed. In the invention, the surface treatment of composite semiconductor is used for reduce a surface state and oxidation, thereby increased the Schottky barriers of the Group III-V composite (such as, GaAs, fnP, InAs and InSb) Schottky contacts. During experiments. a phosphorus sulphide/ammonia sulphide solution and hydrogen fluoride solution are used for the surface treatment to increase the amount of sulphur contained on the surfaces of substrates, reduce the surface state and remove various oxides. Furthermore. ultra-thin and really stable sulphur fluoride/phosphorus fluoride layers having high energy gaps are formed on various substrates.

Abstract: Metallic osmium on SiC (either .beta. or .alpha.) forms a contact that remains firmly attached to the SiC surface and forms an effective barrier against diffusion from the conductive metal. On n-type SiC, Os forms an abrupt Schottky rectifying junction having essentially unchanged operating characteristics to at least 1050.degree. C. and Schottky diodes that remain operable to 1175.degree. C. and a barrier height over 1.5 ev. On p-type SiC, Os forms an ohmic contact with specific contact resistance of <10.sup.-4 ohm-cm.sup.2. Ohmic and rectifying contacts to a TiC layer on a SiC substrate are formed by depositing a WC layer over the TiC layer, followed by a metallic W layer. Such contacts are stable to at least 1150.degree. C. Electrodes connect to the contacts either directly or via a protective bonding layer such as Pt or PtAu alloy.

Abstract: On a channel layer, there are disposed a gate electrode and a first contact layer of which a side surface is brought into contact with the gate electrode on the source side and of which a side surface is apart from the gate electrode on the drain side. Provided on the first contact layer is a second contact layer on which ohmic source and drain electrodes are arranged. A connection wiring is disposed on an upper end of the gate electrode. Specifically, there are provided a thin contact layer and a thick contact layer such that the thin contact layer is brought into contact with the gate electrode. Therefore, the problems of the contact resistance of the ohmic electrode and the gate parasitic capacitance are removed and both drawbacks can be improved at the same time.

Abstract: A process for producing a semiconductor device includes the following sequential steps: producing a semiconductor body having an Al.sub.x Ga.sub.1-x As layer with an upper surface, where x.ltoreq.0.40; applying a contact metallization made of a non-noble metallic material to the Al.sub.x Ga.sub.1-x As layer; precleaning a semiconductor surface to produce a hydrophilic semiconductor surface; roughening the upper surface of the Al.sub.x Ga.sub.1-x As layer by etching with an etching mixture of hydrogen peroxide.gtoreq.30% and hydrofluoric acid.gtoreq.40% (1000:6) for a period of from 1 to 2.5 minutes; and re-etching with a dilute mineral acid. According to another embodiment, 0.ltoreq.x.ltoreq.1 and the upper surface of the Al.sub.x Ga.sub.1-x As layer is roughened by etching with nitric acid 65% at temperatures of between 0.degree. C. and 30.degree. C.

Abstract: A manufacturing method of a junction field effect transistor, promising a low ON resistance, high maximum drain current and linearity with a high transmission gain and also enabling the gate length to be reduced, makes a channel layer by sequentially epitaxially growing an undoped GaAs layer, n.sup.+ -type GaAs layer and n-type GaAs layer on a semi-insulating GaAs substrate via a GaAs buffer layer. Through an opening formed in a diffusion mask in form of a SiN.sub.x film on the n-type GaAs layer, Zn is diffused into the n-type GaAs layer to form a p.sup.+ -type gate region. From above the diffusion mask, a gate metal layer is deposited, and patterned to make a gate electrode in the opening of the diffusion mask in self-alignment with the p.sup.+ -type gate region.

Abstract: An improved GaAs MESFET includes a source contact ohmically coupled to a buffer layer or substrate to stabilize band bending at the interface of the active layer and buffer layer or substrate when an RF signal is applied to a gate electrode.

Abstract: A method for fabricating a field effect transistor (FET) with a T-like gate structure includes forming a silicon nitride layer over a silicon substrate and patterning it to form an opening that exposes the substrate. A dielectric layer is formed on a lower portion of each side-wall of the opening so that the opening has a T-like free space. A doped polysilicon layer fills the T-like free space through only one deposition. After performing a planarization on the doped polysilicon layer, a titanium metal layer is formed over the substrate. A self-aligned titanium silicide is formed over the substrate other than the dielectric layer surface through a rapid thermal process (RTP). A selective etching process is performed to remove the remaining titanium metal layer. After removing the dielectric layer a RTP is performed again to reform the crystal structure of the titanium silicide layer so as to reduce its resistance. A T-like gate structure is formed.

Abstract: On a semiconductor substrate, a channel layer, an electron supply layer, a third semiconductor layer, a second etching stopper layer, a second semiconductor layer and a first etching stopper layer and a first semiconductor layer are grown in sequential order to form E-type and D-type FETs. The third semiconductor layer and the second semiconductor layer have equal layer thickness, and the second etching stopper layer and the first etching stopper layer have the equal layer thickness. Thus, Vth of the E-type and D-type FETs can be controlled at the predetermined value with high reproduction ability.

Abstract: A II-VI group compound semiconductor device includes a semiconductor substrate, a Zn.sub.X Mg.sub.1-X S.sub.Y Se.sub.1-Y (0.ltoreq.X.ltoreq.1, 0.ltoreq.Y.ltoreq.1) semiconductor layer formed on the semiconductor substrate, and an electrode layer formed on the semiconductor layer, the electrode layer containing an additive element of Cd or Te and a metal which can form a eutectic alloy with the additive element, thus achieving an electrode layer having a small contact resistance, especially an electrode layer with an ohmic contact.

Abstract: A diode for sensing hydrogen and hydrocarbons and the process for manufacturing the diode are disclosed. The diode is a Schottky diode which has a palladium chrome contact on the C-face of an n-type 6H Silicon carbide epilayer. The epilayer is grown on the C-face of a 6H silicon carbide substrate. The diode is capable of measuring low concentrations of hydrogen and hydrocarbons at high temperatures, for example, 800.degree. C. The diode is both sensitive and stable at elevated temperatures.

Abstract: The specification describes methods for making T-shaped metal gates for Schottky gate devices such as MESFETs and HEMTs. The method uses a bi-level photoresist technique to create a T-shaped feature for the gate structure. The metal gate is evaporated into the photoresist T-shaped feature and a lift-off process is used to remove unwanted metal. The photoresist is the dissolved away leaving the T-shaped gate. An important aspect of the process is the use of a plasma treatment of the first patterned resist level to harden it so that it is unaffected by the subsequent deposition and patterning of the second level resist.

Abstract: Method for manufacturing a T-gate useful for reducing a gate resistance, improving through-put, and simplifying an MMIC (monolithic microwave integrated circuit) process is disclosed, the method including the steps of depositing a first photoresist layer on a semiconductor substrate and patterning the first photoresist layer so as to expose a predetermined portion of the surface of the substrate; successively forming a seed metal layer and a second photoresist layer on the entire surface inclusive of the exposed substrate and patterning the second photoresist layer so as to define a gate electrode region; plating Au on the seed metal layer on the gate electrode region so as to form a gate electrode; and removing the first and second photoresist layers and the seed metal layer except the gate electrode.

Abstract: In the present invention, a vertical type MOSFET and a Schottky barrier diode which are used as a switching device of a DC--DC converter are formed on the same semiconductor substrate. Further, a barrier metal which is required for the Schottky barrier diode is also formed on an electrode portion of the vertical type MOSFET. In addition, a Schottky barrier diode forming region is formed to have low impurity concentration than a vertical type MOSFET forming region.

Abstract: A semiconductor device exploiting a quantum interference effect is disclosed. The device comprises: a channel region connected multiply with multiplicity of n (n.gtoreq.3) and having (n-1)-fold rotational symmetry around an axis of the channel region; a gate electrode surrounding a side wall of the channel region; and source and drain electrodes electrically connected to one and another end of the channel region along the axis. Electrons move in an effective channel region along or around the axis from the source toward the drain. Electron interference in the effective channel region is controlled by a magnetic field applied in the axis direction and/or the gate electrode.

Abstract: Mixer circuitry having a semiconductor body formed therein mixer circuitry having an oscillator having a heterojunction bipolar transistor and a mixer having a Schottky diode. The heterojunction transistor has a collector region formed in one portion of doped layer of the semiconductor body and the diode has a metal electrode is Schottky contact with another portion of such doped layer. The mixer is includes a diode and a DC biasing circuit, comprising a constant current, for biasing such diode to predetermined operating point substantially invariant with power of an input signal fed to such mixer.

Abstract: A method of fabricating semiconductor devices including forming a plurality of layers of semiconductor material on the surface of a substrate, forming a mask without using a resist on the layers which can be disassociated in-situ, removing an unmasked portion of the layers to form a semiconductor device with a gate region and opposed exposed source and drain surfaces, selectively growing source and drain contact regions on the exposed source and drain surfaces respectively, the contact regions defining opposed sidewalls adjacent the gate region, disassociating the mask, forming sidewall spacers on the sidewalls, forming a metal contact on the source, drain and gate regions with the spacers preventing intercontact therebetween, and depositing a passivating layer over the semiconductor device, with all of the previous steps being performed in-situ in a modular equipment cluster.

Abstract: A dual gate field effect transistor with an ultra thin channel of substantially uniform width formed by a self-aligned process utilizing selective etching or controlled oxidation between different materials to form a vertical channel extending between source and drain regions, having a thickness in the range from 2.5 nm to 100 nm.

Abstract: A method of fabricating semiconductor devices with a passivated surface includes providing first cap and etch stop layers and second cap and etch stop layers with a contact layer thereon so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually etched to define an electrode contact area and to expose the inter-electrode surface area. Portions of the first etch stop and cap layers remaining in the contact area are selectively removed and a metal contact is formed in the contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.

Abstract: A method of defining a line width includes forming a spacer (45) over a layer (42) and using the spacer (45) as an etch mask (57) while etching the layer (42). In this manner, a width (47) of the spacer (45) is used to define a width or line width (47) for the layer (42). Another method of using a spacer to define a line width includes forming a spacer (14) over a substrate (11), depositing a layer (15) over the substrate (11) and the spacer (14), planarizing the layer (15) to expose the spacer (14), and removing the spacer (14) to form an opening (19) over the substrate (11), wherein the opening (19) has a width or line width (17) of the spacer (14).

Abstract: Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices are obtained by forming an amorphous silicon carbide termination region in a monocrystalline silicon carbide substrate, at a face thereof, adjacent and surrounding a silicon carbide device. The amorphous termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize the substrate face. The device contact or contacts act as an implantation mask to provide a self-aligned termination region for the device. The terminated devices may exhibit voltage breakdown resistance which approaches the ideal value for silicon carbide.

Abstract: There is provided a semiconductor element having a Schottky electrode which forms a Schottky junction with an active layer formed on a compound semiconductor substrate characterized in that a modified layer is formed in at least a portion of a region of the active layer on which region the Schottky electrode is formed and a vicinity of that region.

Abstract: A power GaAs Schottky diode with a chemically deposited Ni barrier having a reverse breakdown voltage of 140 V, a forward voltage drop at 50 A/cm.sup.2 of 0.7 V at 23.degree. C., 0.5 V at 150.degree. C. and 0.3 V at 250.degree. C. and having a reverse leakage current density at -50 V of 0.1 .mu.A/cm.sup.2 at 23.degree. C. and 1 mA/cm.sup.2 at 150.degree. C. The high-voltage high-speed power Schottky semiconductor device is made by chemically depositing a nickel barrier electrode on a semiconductor which includes gallium arsenide and then etching the device to create side portions which are treated and protected to create the Schottky device.