Abstract: A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at least the poly gate electrode. The fabrication environment is placed at an elevated temperature. The gate structure may be one of two gate structures included in a dual gate device such as a CMOS device, in which case the respective gates may be formed at different heights (thicknesses) to insure that the silicide forms to the proper phase. The source and drain regions are preferably silicided as well, but in a separate process performed while the gate electrodes are protected by, for example a cap of photoresist or a hardmask structure.

Abstract: An LED array chip (2), which is one type of a semiconductor light emitting device, includes an array of LEDs (6), a base substrate (4) supporting the array of the LEDs (6), and a phosphor film (48). The array of LEDs (6) is formed by dividing a multilayer epitaxial structure including a light emitting layer into a plurality of portions. The phosphor film (48) covers an upper surface of the array of the LEDs (6) and a part of every side surface of the array of LEDs (6). Here, the part extends from the upper surface to the light emitting layer.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.

Abstract: A resistive random access memory and a method for fabricating the same are provided. The method includes providing a bottom electrode formed on a substrate. A metal oxide layer is formed on the bottom electrode. An oxygen atom gettering layer is formed on the metal oxide layer. A top electrode is formed on the oxygen atom gettering layer. The previous mentioned structure is subjected to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, thus leaving a plurality of oxygen vacancies of the metal oxide layer.

Abstract: A fabricating method of a polysilicon layer is disclosed which can be applied for fabricating a semiconductor device such as a SRAM and so on.

Abstract: The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tungsten is deposited in high aspect ratio features. The methods involve depositing a nucleation layer by a combined PNL and CVD process. The substrate is first exposed to one or more cycles of sequential pulses of a reducing agent and a tungsten precursor in a PNL process. The nucleation layer is then completed by simultaneous exposure of the substrate to a reducing agent and tungsten precursor in a chemical vapor deposition process. In certain embodiments, the process is performed without the use of a borane as a reducing agent.

Abstract: Provided are: a method of manufacturing semiconductor device which has multilayer interconnection in a damascene structure and a conductive barrier film such as CoWP film, and which has more excellent electric characteristics than a conventional one. To this end, when a via hole reaching a lower wiring is formed, a reaction layer formed between a conductive barrier film and the lower wiring and remaining on the surface of the lower wiring is removed. Thus, at an interface where a lower surface of the via and the lower wiring are joined, the reaction layer, formed between the conductive barrier film and the lower wiring, does not exist, so that the via resistance can be sufficiently reduced.

Abstract: A low on-resistance silicon carbide semiconductor device is provided that includes an ohmic electrode of low contact resistance and high adhesion strength formed on a lower surface of silicon carbide. The silicon carbide semiconductor device includes: at least an insulating film 7, formed on an upper surface of silicon carbide; and at least an ohmic electrode 12, formed of an alloy comprising nickel and titanium, or a silicide comprising nickel and titanium, and which is formed on the lower surface of the silicon carbide.

Abstract: The present invention relates to a method of forming contact plugs of a semiconductor device. According to the method, a first insulating layer is formed over a semiconductor substrate in which a cell region and a peri region are defined and a first contact plug is formed in the peri region. The first insulating layer is etched using an etch process, thus forming contact holes through which junctions are exposed in the cell region and the first contact plug is exposed in the peri region. Second contact plugs are formed in the contact holes. The second contact plug formed within the contact hole of the peri region are removed using an etch process. A spacer is formed on sidewalls of the contact holes. Third contact plugs are formed within the contact holes.

Abstract: A thin film transistor (TFT) that can prevent damage to a silicon layer under a gate electrode in an annealing process by using a first gate electrode having high thermal resistance and a second gate electrode having high reflectance and a method of manufacturing the TFT are provided. The method of manufacturing a TFT includes forming a double-layered gate electrode which includes a first gate electrode formed of a material having high thermal resistance and a second gate electrode formed of a metal having high optical reflectance on the first gate electrode, and forming a source and a drain by annealing doped regions on both sides of a silicon layer under the gate electrode by radiating a laser beam onto the entire upper surface of the silicon layer.

Abstract: Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers.

Abstract: According to one aspect of the invention, there is provided a qsemiconductor device fabrication method having: forming a film on a semiconductor substrate; forming a mask comprising a predetermined pattern on the film; etching one of the film and the semiconductor substrate by using the mask; and performing at least one of the steps of performing a treatment using one of an aqueous solution of at least one of ammonia and amine, the amine being selected from primary amine, secondary amine, tertiary amine, and quaternary amine, a treatment using a liquid chemical containing fluorine and at least one of amine, the amine being selected from primary amine, secondary amine, tertiary amine, and quaternary amine and fluorine, and a treatment using a liquid chemical containing at least ammonia and fluorine and including a pH of not less than 6, particularly, not less than 9.

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract: A method of optimally filling a through via within a through wafer via structure with a conductive metal such as, for example, W is provided. The inventive method includes providing a structure including a substrate having at least one aperture at least partially formed through the substrate. The at least one aperture of the structure has an aspect ratio of at least 20:1 or greater. Next, a refractory metal-containing liner such as, for example, Ti/TiN, is formed on bare sidewalls of the substrate within the at least one aperture. A conductive metal seed layer is then formed on the refractory metal-containing liner. In the invention, the conductive metal seed layer formed is enriched with silicon and has a grain size of about 5 nm or less. Next, a conductive metal nucleation layer is formed on the conductive metal seed layer. The conductive metal nucleation layer is also enriched with silicon and has a grain size of about 20 nm or greater.

Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.

Abstract: Since VF and IR characteristics of a Schottky barrier diode are in a trade-off relationship, there has heretofore been a problem that an increase in a leak current is unavoidable in order to realize a low VF. Moreover, there has been a known structure which suppresses the leak current in such a manner that a depletion layer is spread by providing P+ regions and a pinch-off effect is utilized. However, in reality, it is difficult to completely pinch off the depletion layer. P+ type regions are provided, and a low VF Schottky metal layer is allowed to come into contact with the P+ type regions and depletion regions therearound. A low IR Schottky metal layer is allowed to come into contact with a surface of a N type substrate between the depletion regions. When a forward bias is applied, a current flows through the metal layer of low VF characteristic. When a reverse bias is applied, a current path narrowed by the depletion regions is formed only in the metal layer portion of low IR characteristic.

Abstract: A hole is formed in an insulating layer. A semiconductor substrate is heated at a temperature of equal to or more than 330° C. and equal to or less than 400° C. Tungsten-containing gas and at least one of B2H6 gas and SiH4 gas are introduced into a reaction chamber to thereby form a first tungsten layer. Subsequently, at least one of H2 gas and inert gas is introduced into the reaction chamber, the temperature of the semiconductor substrate is raised to equal to or more than 370° C. and equal to or less than 410° C. with 30 or more seconds, and tungsten-containing gas is introduced into the reaction chamber to thereby form a second tungsten layer on the first tungsten layer.

Abstract: A capacitor includes a first electrode, a dielectric layer, and a second electrode. The capacitor also includes a buffer layer formed over at least one of an interface between the first electrode and the dielectric layer and an interface between the dielectric layer and the second electrode, wherein the buffer layer includes a compound of a metal element from electrode materials of one of the first and second electrodes and a metal element from materials included in the dielectric layer.

Abstract: A process (200) for making integrated circuits with a gate, uses a doped precursor (124, 126N and/or 126P) on barrier material (118) on gate dielectric (116). The process (200) involves totally consuming (271) the doped precursor (124, 126N and/or 126P) thereby driving dopants (126N and/or 126P) from the doped precursor (124) into the barrier material (118). An integrated circuit has a gate dielectric (116), a doped metallic barrier material (118, 126N and/or 126P) on the gate dielectric (116), and metal silicide (180) on the metallic barrier material (118). Other integrated circuits, transistors, systems and processes of manufacture are disclosed.

Abstract: An interlayer insulation layer is formed on a semiconductor substrate to cover a lower wiring layer that is also formed on the semiconductor substrate. A contact hole to expose a surface of the lower wiring layer is formed by etching the interlayer insulation film. A wetting layer is formed on an inner wall of the contact hole. An anti-deposition layer is formed around an entrance of the contact hole to prevent an aluminum layer from being deposited around the entrance of the contact hole. The contact hole is filled with the aluminum layer.

Abstract: A method of depositing a metallization structure (1) comprises depositing a TaN layer (4) by applying a power supply between an anode and a target in a plurality of pulses to reactively sputter Ta from the target onto the substrate (2) to form a TaN seed layer (4). A Ta layer (5) is deposited onto the TaN seed layer (4) by applying the power supply in a plurality of pulses and applying a high-frequency signal to a pedestal supporting the substrate (2) to generate a self-bias field adjacent to the substrate (2).

Abstract: Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided. In some embodiments, the method includes forming a metallized contact to an active area in a silicon substrate in a peripheral circuitry area and a metallized contact to a polysilicon plug in a memory cell array area by forming a first opening to expose the active area at the peripheral circuitry area, chemical vapor depositing a titanium layer over the dielectric layer and into the first opening to form a titanium silicide layer over the active area in the silicon substrate, removing the titanium layer selective to the titanium silicide layer, forming a second opening in the dielectric layer to expose the polysilicon plug at the memory cell array area, and forming metal contacts within the first and second openings to the active area and the exposed polysilicon plug.

Abstract: The present invention in one embodiment provides a method of forming an interconnect comprising, providing a interlevel dielectric layer atop a substrate, the interlevel dielectric layer including at least one tungsten (W) stud extending from an upper surface of the interlevel dielectric to the substrate; recessing an upper surface of the at least one tungsten (W) stud below the upper surface of the interlevel dielectric to provide at least one recessed tungsten (W) stud; forming a first low-k dielectric layer atop the upper surface of the interlevel dielectric layer and the at least one recessed tungsten (W) stud; forming a opening through the first low-k dielectric layer to expose an upper surface of the at least one recessed tungsten stud; and filling the opening with copper (Cu).

Abstract: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.

Abstract: Methods of controllably producing conductive tantalum nitride films are provided. The methods comprise contacting a substrate in a reaction space with alternating and sequential pulses of a tantalum source material, plasma-excited species of hydrogen and nitrogen source material. The plasma-excited species of hydrogen reduce the oxidation state of tantalum, thereby forming a substantially conductive tantalum nitride film over the substrate. In some embodiments, the plasma-excited species of hydrogen react with and removes halide residues in a deposited metallic film.

Abstract: A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate, forming an opening in the protective film exposing at least a part of the pad electrode, bringing a measurement terminal into contact with the exposed surface of the pad electrode, etching the surface of the pad electrode after the measurement terminal is brought into contact therewith, and forming a hydrogen absorbing film on the protective film and the pad electrode exposed through the opening.

Abstract: It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. A manufacturing method includes the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second conductive layer; processing the second conductive layer by dry etching with the use of the mask; and processing the first conductive layer by wet etching with the mask left, wherein the etching rate of the second conductive layer is higher than that of the first conductive layer in the dry etching, and wherein the etching rate of the second conductive layer is the same as or more than that of the first conductive layer in the wet etching.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a refractory metal alloy layer over a silicon-containing conductive layer. The refractory metal alloy layer is constituted of a first refractory metal and a second refractory metal. Thereafter, a cap layer is formed on the refractory metal alloy layer. A thermal process is performed so that the refractory metal alloy layer reacts with silicon of the silicon-containing conductive layer to form a refractory metal alloy salicide layer. Afterwards, an etch process with an etch solution is performed to removes the cap layer and the refractory metal alloy layer which has not been reacted and to form a protection layer on the refractory metal alloy salicide layer.

Abstract: A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to comply with process requirements for achieving a minimum pitch between neighboring metal lines, while in other areas having less critical constraints with respect to minimum pitch, a reduced resistivity may be obtained at reduced lateral dimensions compared to conventional strategies. For this purpose, the dielectric material of the metallization layer may be appropriately patterned prior to forming respective trenches or the etch behavior of the dielectric material may be selectively adjusted in order to obtain differently deep trenches.

Abstract: An exemplary method includes: providing a substrate with exposed metal and dielectric surfaces, performing a reducing process on the metal and dielectric surfaces, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for selective metal layer deposition.

Abstract: In a method for manufacturing a semiconductor device having a dual damascene structure, a semiconductor substrate formed by stacking a trench mask and a via hole resist mask on an insulating film is loaded into a processing chamber, and a via hole is formed by etching the insulating film through the via hole resist mask. Then, the via hole resist mask is removed by an ashing process and a protective film is formed on an underlayer of the insulating film; Thereafter, a trench is formed by etching the insulating film through the trench mask, and the semiconductor substrate is unloaded from the processing chamber after the via hole forming step, the resist mask removing step, the protective film forming step and the trench forming step are completed in the processing chamber.

Abstract: In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed on a patterned inter-level dielectric layer. A (Cu) seeding layer is then formed on the diffusion barrier layer, and a grain growth promotion layer is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed.

Abstract: Provided is a manufacturing method of a semiconductor device wherein the generation of voids is prevented in aluminum-based electrodes or the like. The method is suitable for manufacturing a semiconductor device adapted for vehicles, which is required to have a high reliability. However, it is very difficult that power semiconductor devices such as power MOSFETs, in particular, trench gate type power MOS devices are formed without having any void since the thickness of aluminum-based electrodes thereof is as large as about 3500 to 5500 nm (2.5 ?m or more). In the present invention, a method is provided wherein at the time of forming an aluminum-based electrode metal film positioned over a wafer and having a thickness of 2.5 ?m or more over a highland/lowland-repeated region in a line and space form by sputtering, the temperature of the wafer is set to 400° C. or higher and lower than 500° C.

Abstract: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an optional silicon precursor compound.

Abstract: A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the barrier layer, depositing a metal layer on the adhesion layer, removing the metal layer using a CMP process until at least a portion of the adhesion layer is exposed, and removing portions of the adhesion layer and the barrier layer sited substantially outside of the trench using a dissolution process. The dissolution process applies an electrolyte solution to those portions of the adhesion layer and the barrier layer sited substantially outside of the trench to dissolve and remove them.

Abstract: A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO2 film provided on the silicon substrate, copper films embedded in the SiO2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO2 film, and SiON films covering an upper face of the TiN films.

Abstract: The invention provides a method for forming a metal silicide layer. The method comprises steps of providing a substrate and forming a nickel-noble metal layer over the substrate. A grain boundary sealing layer is formed on the nickel-noble metal layer and then an oxygen diffusion barrier layer is formed on the grain boundary sealing layer. Thereafter, a rapid thermal process is performed to transform a portion of the nickel-noble metal layer into a metal silicide layer. Finally, the oxygen diffusion barrier layer, the grain boundary sealing layer and the rest portion of the nickel-noble metal layer are removed.

Abstract: A nitride semiconductor device is provided which reduces the contact resistance at the interface between a P-type electrode and a nitride semiconductor layer. A nitride semiconductor device includes a P-type nitride semiconductor layer and a P-type electrode formed on the P-type nitride semiconductor layer. The P-type electrode is formed by successive laminations of a metal layer of a metal having a work function of 5.1 eV or more, a Pd layer of palladium, and a Ta layer of tantalum on the P-type nitride semiconductor layer.

Abstract: A method for forming a metal carbide layer begins with providing a substrate, an organometallic precursor material, at least one doping agent such as nitrogen, and a plasma such as a hydrogen plasma. The substrate is placed within a reaction chamber; and heated. A process cycle is then performed, where the process cycle includes pulsing the organometallic precursor material into the reaction chamber, pulsing the doping agent into the reaction chamber, and pulsing the plasma into the reaction chamber, such that the organometallic precursor material, the doping agent, and the plasma react at the surface of the substrate to form a metal carbide layer. The process cycles can be repeated and varied to form a graded metal carbide layer.

Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

Abstract: A semiconductor device fabrication apparatus is cleaned after a conductive layer is formed on a metal oxide layer of a substrate. The substrate is disposed on a heater in a process chamber of the apparatus, and the conductive layer is formed by introducing source gases into the chamber. Then the substrate is transferred out of the process chamber. At least one by-product of a reaction between the source gases and the metal oxide layer adheres to a surface inside the chamber, such as to a region or regions of the heater. Once the semiconductor substrate has been transferred outside the process chamber of the semiconductor fabrication apparatus, the by-product(s) is/are removed by evaporation. The by-product(s) can be evaporated using gas, such as one of the source gases, so that the process chamber can remain closed.

Abstract: A method of depositing copper directly onto a tantalum alloy layer of an on-chip copper interconnect structure, which includes electrodepositing copper from a neutral or basic electrolyte onto a surface of a tantalum alloy layer, in which the tantalum alloy layer is deposited on a substrate of the on-chip copper interconnect structure, and in which the copper nucleates onto the surface of the tantalum alloy layer without use of a seed layer to form a copper conductor.

Abstract: A method for forming a strained metal nitride film and a semiconductor device containing the strained metal nitride film. The method includes exposing a substrate to a gas containing a metal precursor, exposing the substrate to a gas containing a silicon precursor, exposing the substrate to a gas containing a nitrogen precursor activated by a plasma source at a first level of plasma power and configured to react with the metal precursor or the silicon precursor with a first reactivity characteristic, and exposing the substrate to a gas containing the nitrogen precursor activated by the plasma source at a second level of plasma power different from the first level and configured to react with the metal precursor or the silicon precursor with a second reactivity characteristic such that a property of the metal silicon nitride film formed on the substrate changes to provide the strained metal silicon nitride film.

Abstract: A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.

Abstract: A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.

Abstract: A method for forming a metallization contact in a semiconductor device includes (a) forming an insulating layer on a semiconductor substrate including an active device region or a lower metal wire; (b) forming a contact hole to expose a portion of the active device region or lower metal wire by etching a portion of the insulating layer; (c) depositing a first TiN layer on the insulating layer and inside the contact hole by a PVD process using a first carrier gas composition of nitrogen (N2) and argon (Ar); (d) depositing a second TiN layer on the first TiN layer by a PVD process using a second carrier gas composition of nitrogen (N2) and argon (Ar); and (e) forming a metal layer on the second TiN layer.

Abstract: In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating a liquid tantalum precursor containing tertiaryamylimido-tris(dimethylamido) tantalum (TAIMATA) to a temperature of at least 30° C. to form a tantalum precursor gas and exposing the substrate to a continuous flow of a carrier gas during an atomic layer deposition process. The method further provides exposing the substrate to the tantalum precursor gas by pulsing the tantalum precursor gas into the carrier gas and adsorbing the tantalum precursor gas on the substrate to form a tantalum precursor layer thereon. Subsequently, the tantalum precursor layer is exposed to at least one secondary element-containing gas by pulsing the secondary element-containing gas into the carrier gas while forming a tantalum barrier layer on the substrate.

Abstract: The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR1)(NR2R3)3, wherein each R1, R2, and R3 is independently hydrogen or an organic group, with the proviso that at least one of R1, R2, and R3 is a silicon-containing organic group. Such systems and methods can be useful for depositing tantalum silicon nitride layers on substrates.

Abstract: A method for fabricating a thin film transistor (TFT) is provided. A substrate having a gate, a dielectric layer, a channel layer and an ohmic contact layer formed thereon is provided. Next, a metal layer is formed over the substrate covering the ohmic contact layer. Next, the metal layer and the ohmic contact layer are simultaneously etched by a wet etching process to form a source/drain and expose the channel layer. Because the wet etching process can be used to selectively etch the ohmic contact layer, damage to the underlying channel layer may be negligible. Thus, the reliability of the device may be promoted. Furthermore, the process may be simplified, the production yield and the throughput of TFT may be increased.