Abstract: A layered trace configuration comprising a conductive trace capped with a silicide material which allows for removal of oxide polymer residues forming in vias used for interlayer contacts in a multilayer semiconductor device and eliminates or greatly reduces the formation of metal polymer residues in the vias. The formation of an interlayer contact according to one embodiment of the present invention comprises providing a trace formed on a semiconductor substrate and a silicide layer capping the conductive layer. An interlayer dielectric is deposited over the silicide capped trace and the substrate. A via is etched through the interlayer dielectric, wherein the etch is selectively stopped on the silicide layer. Any residue forming in the via is removed and a conductive material is deposited in the via to form the interlayer contact.

Abstract: A chemical vapor deposition (CVD) method for forming a doped silicate glass dielectric layer within a microelectronics fabrication. There is first positioned within a reactor chamber a substrate employed within a microelectronics fabrication. There is then stabilized within the reactor chamber with respect to the substrate a first flow of a silicon source material absent a flow of a dopant source material. There is then deposited upon the substrate within the reactor chamber a doped silicate glass dielectric layer through a chemical vapor deposition (CVD) method. The doped silicate glass dielectric layer is formed employing a second flow of the silicon source material, a flow of an oxidant source material and the flow of the dopant source material. There may subsequently be formed through the doped silicate glass dielectric layer an anisotropically patterned via through an anisotropic patterning method.

Abstract: A method for fabricating a via that uses a hard etching mask for etching the via. A photoresist layer used to pattern the hard etching mask is removed before starting the via etching. The hard etching mask includes a TiN etching mask, a silicon nitride etching mask, and a oxide/TiN etching mask. For each different etching mass, the TiN etching mask is not necessarily removed after etching; the silicon nitride etching mask is removed after etching; the oxide layer in the oxide/TiN etching mask is sacrificial layer.

Abstract: A method for fabricating an SOI substrate is provided, which has an active substrate formed as a thin film. The method comprises the steps of: using a both-side polishing apparatus to polish both sides of a supporting substrate 1; bonding an active substrate 2 onto the supporting substrate 1. to form a bonded-wafer; removing an unbonded portion formed at the circumference of the bonded-wafer; flat grinding the active substrate 2 to reduce the thickness thereof; etching the active substrate 2 by spin etching; and processing the active substrate to be a thin film by PACE processing.

Abstract: A method for forming a plurality of self-aligned via holes applied to a semiconductor device is disclosed. The method includes steps of (a) providing a substrate forming thereon a conducting layer forming thereon a sacrificial layer; (b) partially removing the sacrificial layer while retaining a plurality of sacrificial via pillars, and removing portions of the conducting layer under the removed sacrificial layer; (c) forming a first insulating layer between the plurality of the sacrificial via pillars, and then planarizing the first insulating layer to expose tops of the plurality of sacrificial via pillars; and (d) removing the plurality of the sacrificial via pillars while retaining the first insulating layer to form the plurality of the self-aligned via holes. By the above-described method, the formed via holes are self-aligned to the underlying metal lines and pads and less photolithography equipment requirement is needed to define fine via holes.

Abstract: A process for improving the uniformity of the thickness of a semiconductor substrate utilizing plasma assisted chemical etching is disclosed. The process includes measuring the thickness of a semiconductor substrate at discrete points on the front surface, computing a dwell time versus position map based on the measured thickness data, mathematically inverting the position map to allow material to be removed from the back surface, and selectively removing material from the back surface of the substrate by plasma assisted chemical etching to improve the thickness uniformity of the substrate.

Abstract: A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.

Abstract: A method of removing an outer layer from an inner surface during semiconductor fabrication. A portion of the outer layer (50) may be anisotropically etched. A remaining portion of the outer layer (55) may then be wet etched without impairing the inner surface (12).

Abstract: A method for manufacturing a charge storage electrode that utilizes the tendency for implanted phosphorus ions in a hemispherical grain (HSG) polysilicon layer to gather near the grooves so that the rate of oxidation there increases. Utilizing this property, a solution including an oxidizing agent and an etching agent mixed in a specified ratio is employed to etch the hemispherical grained polysilicon layer so that the grooves in the hemispherical polysilicon layer is deepened. Therefore, the surface area of the charge storage electrode is increased, and hence capacitance of the charge storage structure becomes greater. Moreover, the method used in this invention is compatible with the conventional processes and can be produced in batches. Therefore, production cost is low.

Abstract: The gate oxide film is prevented from being thinned partially. The semiconductor substrate (wafer) can be etched (processed) under excellent conditions. The impurities on the wafer surface can be analyzed and further reduced. In the first aspect, the substrate is irradiated with ultraviolet rays in contact with an F-containing aqueous solution, so that the oxide film and the substrate can be etched at roughly the same etching speed under excellent controllability without deteriorating the planarization of the substrate. In the second aspect, the substrate is etched by irradiating ultraviolet rays during exposure to an acid aqueous solution, so that surface metallic contamination and particles can be removed without deteriorating the wafer surface roughness. Further, the impurity elements in the outermost surface layer of the wafer can be analyzed at high precision by analyzing elements contained in the acid aqueous solution used for the etching.

Abstract: An improved and new method for forming a planarized integrated cirsuit structure has been developed. The method uses a combination of etchback and chemical/mechanical polishing (CMP), in which the etchback process uses a tailored mask to compensate for non-unifomity of material removal by the subsequent chemical/mechanical (CMP) process, thereby resulting in improved planarization and superior thickness uniformity.

Abstract: This invention describes a method of forming alignment marks which will be preserved after contact holes in a dielectric have been filled with barrier metal and contact metal and the wafer has been planarized. The alignment marks are formed by filling alignment lines, formed in the dielectric when the contact holes are formed, with barrier metal and contact metal. The alignment lines and contact holes are filled with metal at the same time. After the wafer has been planarized, using a method such as chemical mechanical polishing, a small thickness of the dielectric is etched back using vertical dry anisotropic etching which will not remove either the contact metal or barrier metal. This leaves barrier metal and contact metal extending above the plane of the dielectric forming alignment marks. These alignment marks are preserved after subsequent processing steps, such as deposition of a layer of electrode metal.

Abstract: A method for cleaning polymer film residues from in-process integrated circuit devices is disclosed. Specifically, a method for forming a contact via in an integrated circuit is disclosed in which the formation of a metallization conductive element is exposed through a dry anisotropic etch. During the etch, a polymer film residue forms from masking materials, and coats the newly-formed via. The polymer film may have metals incorporated metals therein from the metallization conductive element. A fluorine based etchant is used to remove the polymer film. Protection of the metallization conductive element during the cleaning process is accomplished with passivation additives comprising straight, branched, cyclic, and aromatic hydrocarbons. Attached to the hydrocarbons are functional groups comprising at least 3 hydroxyls.

Abstract: A process for forming via openings (24) between two aluminum-containing interconnects (15) which includes removing a veil material (22) formed during etching of an insulating layer (12), where the veil material (22) is then removed by a combination process of a first dry etch followed by an aqueous organic solvent exposure. The first dry etch uses oxygen containing and fluorine-containing gases, and is performed during the resist removal. This combination process effectively removes the veil (22), even for the heaviest of veil formation, without adversely affecting the insulating layer (12) or the underlying interconnect (15) that includes aluminum. The temperature of the aqueous organic solvent may be reduced, decreasing the amount of volatile organic compound emissions from the solvent while maintaining solvent strength.

Abstract: The present invention provides a method of removing photoresist from a wafer surface having a bonding pad using a three step clean composed of (1) a wet cleaning the substrate, (2) a F-containing gas high temperature plasma treatment which prevents the corrosion of aluminum contact pad, and (3) completely striping the photoresist strip using an O.sub.2 dry ash. The invention eliminates metal bonding pad corrosion and the completely removes residual photoresist from keyholes.

Abstract: A method for surface treatment of a substrate is described in which a gas discharge at or about atmospheric pressure produces activated gas or active species which are then used for surface treatment of a substrate. When the discharge gas contains oxygen, for example, surface treatment forms a metal oxide film on a metal circuit on a substrate. If, however, the gas contains hydrogen or an organic substance, a metal oxide film, such as a transparent electrode formed on the surface of a liquid crystal panel, is reduced. Alternatively, by causing discharge to take place adjacent to the surface of a liquid, or bubbled through a liquid, a liquid may be used for surface treatment of a substrate without risk of thermal or electrical damage to the substrate.

Abstract: Methods of forming metal silicide layers include the steps of forming electrically conductive lines that comprise the steps of forming a layer of polysilicon on a semiconductor substrate and then forming a layer of metal silicide on the polysilicon layer, opposite the substrate. The layer of metal silicide and the layer of polysilicon are then patterned as an electrically conductive line having sidewalls. The semiconductor substrate is then exposed to a cleaning agent that selectively etches the patterned layer of metal silicide at a faster rate than the patterned layer of polysilicon. The patterned layer of metal silicide is then thermally oxidized to define recess spacers extending adjacent sidewalls of the electrically conductive line. An electrically insulating layer is then formed on the electrically conductive line and on the recess spacers. The electrically insulating layer is then anisotropically etched to define insulating spacers on the recess spacers.

Abstract: A method of forming an isolating region of a semiconductor device including the steps of: forming first insulating layers which vary in width on a substrate; forming trenches which vary in width on the substrate by using the first insulating layers as a mask; forming second insulating layers on the trenches and the first insulating layers; exposing the predetermined portions of the first insulating layers by etching the second insulating layers; and wet-etching the first insulating layers and the non-etched portions of the second insulating layers. In the present invention, an isolating region in the narrow trench is formed without voids by regulating the deposition/etching ratio during the formation of an insulating layer in a trench.

Abstract: A DRAM capacitor is formed using a process that avoids high temperature processing steps and which emphasizes low cost processes. An interlayer dielectric, typically CVD TEOS oxide, is provided over the transfer FET and bit line contact of the DRAM cell. The interlayer dielectric is planarized and an etch stop layer is provided over the planarized surface of the etch stop layer. A contact via is formed to expose a source/drain region for the transfer FET. Doped polysilicon is provided to fill the contact via and to form a first layer of doped polysilicon over the etch stop layer. The first polysilicon layer is patterned to form a plate aligned over the contact via using a first photoresist mask and etching. The first photoresist mask is left in place over the plate and a first layer of selective oxide is deposited over the etch stop layer so that the first selective oxide layer does not deposit over the photoresist mask.

Abstract: Methods are disclosed for manufacturing silicon stencil masks for use in charged-particle-beam microlithography. According to the method, a boron-doped layer is formed on a silicon substrate, a mask pattern is formed on the boron doped layer, and the boron-doped layer is etched according to the mask pattern to form voids in the boron-doped layer. The voids do not extend completely through the thickness of the boron-doped layer. In subsequent steps, a silicon nitride layer is applied and etched to form openings in which the silicon substrate is etched away to form struts. Because the boron-doped layer is not completely etched through in the earlier etching step, the mask is much more resistant to fracture in a subsequent cleaning step. In a final step after cleaning, the boron-doped layer is etched to extend the voids completely through the thickness of the boron-doped layer.

Abstract: The present invention relates to a method of manufacturing an opening through a dielectric layer. The method comprises treating a polished dielectric layer with a wet etch selectively enchancing composition, such as buffered HF, prior to the formation of a patterned photoresist to improve the lateral-to-vertical wet etch ratio.

Abstract: An etching method for performing dry-etching on a III-V group compound semiconductor or a II-VI group compound semiconductor in a dry-etching apparatus comprising a plasma source for creating a plasma of density of about 10.sup.10 cm.sup.-3 or greater, using a mixed gas containing a gas including a halogen element and a gas including nitrogon. The etching conditions are as follows: (a flow rate of the gas containing said halogen gas)/(a flow rate of said nitrogen gas) .gtoreq.1; and an internal pressure during etching reaction is about 1 mTorr or greater.

Abstract: A process is described for etching contact holes though a dielectric layer down to a silicon surface. Initial etching, until the silicon is exposed, is performed in a suitable plasma environment under high RF power. This results in damage to the newly exposed silicon surface. Said damage is repaired by exposing the silicon and the photoresist to an atmosphere that includes carbon tetrafluoride and atomic oxygen. The latter oxidizes the damaged layer, allowing it to be removed by the former. Much of the photoresist is also removed by the atomic oxygen, any that still remains being then removed using a wet etch. At the user's option, the silicon may be allowed to overetch during the high RF power application and/or a low power RF step may be introduced to partially remove silicon surface damage prior to the atomic oxygen treatment.

Abstract: A method for preparing a sample for TEM is described. The method is particularly well suited for examining the active region of an FET. After removing the various layers present above the active region, the polysilicon gate is exposed and then selectively removed. In a key feature of the invention, care is taken to ensure that the regions of field oxide on either side of the active region are left fully intact. After using a laser to mark the area of interest for later ease of identifcation, the silicon is etched down to a few thousand Angstroms, followed by ion milling to further reduce the thickness over the area of interest. Because of the support provided by the field oxide, very thin layers can be exposed without the danger of them pulling away from the silicon.

Abstract: A process for fabricating bottom electrodes for storage capacitors of memory cell units of a DRAM is disclosed. The process employs the use of a protective dielectric layer that serves as an etching shield in the process of fabrication of the capacitor electrode. The HSG-Si layer that substantially increases the surface area of the capacitor electrode can be protected from etching damage, thereby avoiding short-circuiting phenomena found in the conventional fabrication processes. Improved data retention time capability of the DRAM memory cells can thus be obtained utilizing the fabrication process of the invention.

Abstract: A method of plasma etching photoresist and sidewall polymer with an etch gas mixture comprising a fluorine containing gas (CF.sub.4 or NF.sub.3) and H.sub.2 O demonstrating very aggressive ashrate of photoresist but maintains an exceptionally low etch rate for titanium nitride and other metals is provided. The very low TiN etch rate permits the inventive method to effectively breakdown sidewall polymer without removing any significant amount of these metals. The invention is particularly suited for stripping sidewall polymer from etched via holes and from etched metal lines. Vias fabricated with this technique exhibit exceptionally low resistance.

Abstract: A method for forming a contact hole in a phosphosilicate glass layer includes the steps of forming a phosphosilicate glass layer, reflowing the phosphosilicate glass layer, removing a surface portion of the phosphosilicate glass layer, and forming the contact hole in the phosphosilicate glass layer. In particular, the surface portion of the phosphosilicate glass layer can be on the order of about 1000 .ANG. thick, and the step of removing the surface portion can include etching the surface portion. Furthermore, the step of forming the contact hole can include the step of selectively wet etching the phosphosilicate glass layer followed by the step of selectively dry etching the phosphosilicate glass layer.

Abstract: A method for forming a gate with a tapered spacer is disclosed. The method includes forming a polysilicon layer on a substrate, and then forming a first oxide layer on the polysilicon layer. A photoresist layer is formed on the first oxide layer, where the photoresist layer defines a gate region, and then portions of the oxide layer and the polysilicon layer are removed using the photoresist layer as a mask, thereby forming a gate. A second oxide layer is formed on the substrate and the first oxide layer. Afterwards, the second oxide layer is isotropically etched so that the slope of the second oxide layer near the upper corners of the gate is reduced. Finally, the second oxide layer is anisotropically etched back to form spacers on the sidewalls of the gate.

Abstract: A method of forming a stable type of dielectric film of flash EEPROM by preventing forming of unusual type of oxide film. The method of manufacturing dielectric film comprising the steps of: forming a first polysilicon film, a first dielectric film and a second polysilicon film on the active region of a semiconductor substrate sequentially; patterning said second polysilicon film, the first dielectric film and the first polysilicon film in the same size respectively; forming a curved surface on the side wall of the first dielectric film using wet etching technique in order to accelerate the growth of second dielectric film on the side wall of the first polysilicon film during the subsequent oxidation process; and forming the second dielectric film on the exposed surfaces of the patterned first polysilicon film, first dielectric film, and second polysilicon film using thermal oxidation process.

Abstract: A method for forming within a microelectronics fabrication a via through a microelectronics layer formed of a material susceptible to sequential etching employing a fluorine containing plasma etch method followed by an oxygen containing plasma etch method. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a microelectronics layer formed of a material susceptible to sequential etching employing a fluorine containing plasma etch method followed by an oxygen containing plasma etch method. There is then formed upon the microelectronics layer a patterned photoresist layer. There is then etched through use of the fluorine containing plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the microelectronics layer to form a patterned microelectronics layer having a via formed through the patterned microelectronics layer.

Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

Abstract: The present invention is related to a method for increasing utilzable surface area of a rugged polysilicon layer in a semiconductor device. The present method includes steps of: (a) providing a pre-grown rugged polysilicon layer which is composed of polysilicon with first dopants doped therein; (b) forming another polyslicon layer on the pre-grown rugged polysilicon layer; (c) removing a portion of the another polysilicon layer by an anisotropic etching process to expose an upper surface of the pre-grown rugged polysilicon layer; and (d) etching the resulting pre-grown rugged polysilicon layer which an etching selectivity ratio of the pre-grown rugged polysilicon layer to the another polysilicon layer being greater than one, to obtain the rugged polysilicon layer having increasing utilizable surface area. A semiconductor device containing the rugged polysilicon layer created according to the present invention can work well in a relatively dense and small semiconductor chip.

Abstract: A method for removing a metal-fluoropolymer residue from an integrated circuit structure within an integrated circuit. There is first provided an integrated circuit having formed therein a metal-fluoropolymer residue. The metal-fluoropolymer residue is formed from a first plasma etch method employing a fluorocarbon containing etchant gas composition within the presence of a conductor metal layer within the integrated circuit. The metal-fluoropolymer residue is then exposed to a second plasma etch method employing a chlorine containing etchant gas composition to form from the metal-fluoropolymer residue a chlorine containing plasma treated metal-fluoropolymer residue. Finally, the chlorine containing plasma treated metal-fluoropolymer residue is removed from the integrated circuit through a stripping method sequentially employing an aqueous acid solution followed by an organic solvent.

Abstract: The present invention provides a process for fabricating an SOI substrate with no peripheral scratches and with enhanced fabrication efficiency. The present process includes bonding a semiconductor wafer of an active substrate 1 and a semiconductor base wafer 2 to form a bonded wafer 4; surface-grinding the active substrate 1; spin etching the surface-ground active substrate 1; and PACE processing the etched active substrate 1 to form the active substrate into a thin film and simultaneously, to remove the non-bonded peripheral portion of the bonded wafer 4.

Abstract: A device-isolating trench having a taper at its upper portion is formed in a silicon semiconductor substrate. Then, a silicon oxide film is formed on the inner wall of the trench and the surface of the semiconductor substrate near the trench by an oxidizing method, and polycrystalline silicon is buried in the trench.

Abstract: A refractory metal layer on a silicon oxide layer is exposed to gaseous etchant containing SF.sub.6, Cl.sub.2 and CO so as to be patterned; F radical and Cl radical effectively etch the refractory metal, and a reaction product of CO gas does not allow the dry etching to sidewardly proceed so that the dry etching achieves good anisotropy, a large etching rate and a large selectivity to silicon oxide.

Abstract: A semiconductor processing method of forming a contact opening includes providing a substrate having a node location to which electrical connection is to be made. A layer comprising doped silicon dioxide is formed over the node location. Thereafter, both O.sub.2 and O.sub.3 are flowed simultaneously to the substrate along with tetraethylorthosilicate to the substrate to form a continuous layer comprising undoped silicon dioxide on the layer comprising doped silicon dioxide. During the flowing, a ratio of O.sub.3 to O.sub.2 flows is increased to form an outer portion of the continuous layer comprising undoped silicon dioxide to have a higher etch rate for a selected wet etch chemistry than an inner portion of said continuous layer. A common contact opening is anisotropically dry etched into the layer comprising undoped silicon dioxide and into the layer comprising doped silicon dioxide over the node location to outwardly expose the node location.

Abstract: A method for preventing bubble formation over source/drain active areas in p-channel MOSFETs is described. Bubble formation occurs when the source/drain areas and silicon containing gate electrodes are implanted with BF.sub.2.sup.+ molecule ions following an anisotropic LDD spacer etch using a plasma. It is found that the plasma causes the silicon surface to become prone to adsorption of BF.sub.2.sup.+ molecule ions during the source/drain/gate implantation. These adsorbed species are released and form bubbles during reflow of a subsequently deposited glass layer. The invention performs the spacer etch only partially with the anisotropic plasma and completes the spacer formation with a wet etch. The active silicon and gate electrode surfaces are thus not damaged by the plasma. Consequently adsorption of BF.sub.2.sup.+ molecule ions is inhibited and bubble formation does not occur during reflow.

Abstract: A layer of silicon dioxide is formed conformably over a substrate having a surface with non-planar topography. The layer of silicon dioxide is then implanted with a species that affects the etch rate of the silicon dioxide when etched in an HF based etchant. The implant energy, dose, and direction are chosen such that only a selected portion of the layer of silicon dioxide is implanted with the implant species. The layer of silicon dioxide is then etched in an HF based etchant. The HF etchant etches both doped and undoped silicon dioxide, but the implanted silicon dioxide is removed at a faster rate or slower rate, depending on the implant species, than the unimplanted silicon dioxide. This allows the formation of specialized silicon dioxide structures due to the selectivity of the etch as between the implanted and unimplanted portions of the layer of silicon dioxide, without any damage to silicon.

Abstract: A method for processing a layer of a silicon-based material on a wafer by which a sidewall protective film may be removed sufficiently and efficiently. An etching gas capable of yielding chlorine- or bromine-based chemical species and oxygen-based chemical species is used for dry etching a polycide film formed on a gate insulating film, plasma processing with an oxygen-based gas is then carried out for ashing the resist mask and removing carbonaceous components in the sidewall protective film. In addition, the sidewall protective film is oxidized so that the composition to that of stoichiometrically stable SiO.sub.2 is approached. Subsequently, the modified sidewall protective film is removed by processing with a dilute hydrofluoric acid solution. Since this sufficiently removes the sidewall protective film, it becomes possible to reduce the amount of dust and to improve coverage of a film to be formed by the next step.

Abstract: A process for producing dual layer polysilicon structures without the formation of residual polysilicon stringers and the resulting structure. Dielectric sidewalls are formed upon a first polysilicon structure to prevent the formation of overhang regions during subsequent oxidation that will harbor residual polysilicon stringers formed by the deposition of a second polysilicon structure on top of the first polysilicon structure.

Abstract: A method of manufacturing a semiconductor device comprising a buried channel field effect transistor, which method comprises the formation of a stack of layers on a substrate (1) with an active semiconductor layer (13, 14) having a non-zero aluminium (Al) content, a semiconductor cap layer (4) without aluminium (Al), a masking layer (100) provided with a gate opening (51); a first selective etching step by means of a fluorine (F) compound in the cap layer (4) down to the upper surface (22) of the active layer (13, 14) on which a stopper layer (3) of aluminum fluoride (AlF.sub.

Abstract: A method of etching vias without directional etching damage to the substrate. A pattern image is formed on an insulating layer of known thickness over a substrate. A conformal layer is formed on the pattern image. A vertical contact hole through the conformal layer and into the insulating layer is produced by directional etching. The directional etch also leaves conformal sidewall spacers of a defined width. The depth of the vertical contact hole is equal to the thickness of the insulating layer minus the width of the conformal spacer. The insulating layer is then removed by an isotropic wet etch to achieve a near vertical edge contact hole without directional etching damage to the substrate. The sidewall spacers may also be removed by etching prior to removal of the insulating layer.

Abstract: A pressure sensor (11) and its method of fabrication include etching a V-groove (19) in a first surface (16) of a first substrate (12), bonding a second substrate (24) to the first substrate (12), thinning the second substrate (24) to form a diaphragm (32) overlying the V-groove (19), and etching a port (38) from the second surface (18) of the first substrate (12) to the V-groove (19). Tetra-methyl-ammonium-hydroxide is preferably used to anisotropically etch the V-groove (19), and an anisotropic plasma reactive ion etch is preferably used to etch the port (38).

Abstract: Stripping and cleaning agent for removing dry-etching photoresist residues, and a method for forming an aluminum based line pattern using the stripping and cleaning agent. The stripping and cleaning agent contains (a) from 5 to 50% by weight of an organocarboxlic ammonium salt or an amine carboxylate, represented by the formula [R.sup.1 ]m[COONH.sub.p (R.sup.2)q]n, where R.sup.1 is hydrogen, or an alkyl or aryl group having from 1 to 18 carbon atoms; R.sup.2 is hydrogen, or an alkyl group having from 1 to 4 carbon atoms; m and n independently are integers of from 1 to 4, p is integer of from 1 to 4, q is integer of from 1 to 3, and p+q=4 and (b) from 0.5 to 15% by weight of a fluorine compound. The inventive method is advantageously applied to treating a dry-etched semiconductor substrate with the stripping and cleaning agent. The semiconductor substrate comprises a semiconductor wafer having thereon a conductive layer containing aluminum.

Abstract: A method is described for forming tapered contact via holes in large scale integrated circuit structures which avoids the formation of a re-entrance profile. The re-entrance profile can form at the entrance to the contact via hole when a dry etch is used as a first etching step by redepositing material removed during the dry etch at the entrance of the contact via hole. This re-entrance profile makes the angle of entrance into the contact via hole greater than 90.degree. and the step coverage of metal filling the hole poor. This invention uses wet etching with a greater lateral etch rate than vertical etch rate as a first etching step in the formation of the contact via hole and avoids the formation of the re-entrance profile. The edges of the resulting contact via hole are smooth and the entrance angle into the contact via hole is substantially less than 90.degree.. The step coverage of metal later filling the contact via hole is substantially improved.

Abstract: The present invention relates to a method of manufacturing a semiconductor device including a process of removing a photoresist mask or a photosensitive polyimide mask remaining after implanting impurity ions into a semiconductor layer or the like, and has an object to prevent generation of oxides of impurities and photoresist explosion and arranging it so that no residue remains. The present invention comprises the steps of forming a mask composed of photosensitive organic matter on a layer, implanting impurity ions into the layer through the mask, and removing the mask through processing including three steps of: exposing the mask to a plasma activated gas containing hydrogen, exposing to the mask to a plasma activated gas containing oxygen, and exposing the mask to a solution containing nitric acid under conditions sufficient to dissolve alumina which had formed on the mask during exposure of the mask to oxygen.

Abstract: Apparatus and methods for precise processing of thin materials in a process chamber by the use of ellipsometer monitoring is disclosed. The process includes rapidly etching a layer 42 of material covering a semiconductor device. The process includes placing the semiconductor wafer 14 into a processing chamber 10. In a typical operation, the wafer 14 will include a selected substrate 32 having a first thin layer 30 of material covering the substrate 32 and then a second layer 42 of a different material covering the first layer 30. A process such as reactive ion anisotropic etching which rapidly etches the second layer 42 is initiated and this etching is monitored in situ by an ellipsometer in combination with a controller 28 to determine the thickness of the second layer 42' which has been achieved. Once the desired amount of second layer 42 remains, the rapid etching process stops to leave a residual layer 42' such as about 250 .ANG.

Abstract: A method for forming a residue free patterned conductor layer upon a high step height integrated circuit substrate. First, there is provided a semiconductor substrate having formed thereon a high step height patterned integrated circuit layer. Formed upon the high step height patterned integrated circuit layer is a blanket conductor layer, and formed upon the blanket conductor layer is a patterned photoresist layer. The portions of the blanket conductor layer exposed through the patterned photoresist layer are etched through an anisotropic etch process to leave remaining a patterned conductor layer upon the surface of the high step height patterned integrated circuit layer and conductor layer residues at a lower step level of the high step height patterned integrated circuit layer. The patterned photoresist layer is then reflowed to cover exposed edges of the patterned conductor layer.

Abstract: A metal selective polymer removal process is disclosed which prevents metal lift-off for use especially suited for ULSI fabrication.