Abstract: The present invention relates to an electroless-plating liquid useful for forming a protective film for selectively protecting surface of exposed interconnects of a semiconductor device which has an embedded interconnect structure formed by an electric conductor, such as copper or silver, embedded in fine recesses for interconnects formed in a surface of a semiconductor substrate, and also to a semiconductor device in which surfaces of exposed interconnects are selectively protected with a protective film. The electroless-plating liquid contains cobalt ions, a complexing agent and a reducing agent containing no alkali metal.

Abstract: The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps: a) anisotropic etching of the top part of the gate material layer not masked by the gate mask, this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit composed of etching products on the etching sides resulting from the anisotropic etching, b) treatment of the deposit composed of etching products, to make a protection layer reinforced against subsequent etching of the gate material, c) etching of the bottom part of the gate material layer as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make the gate shorter at the bottom than at the top.

Abstract: A semiconductor device includes a semiconductor substrate which has a major surface and a MOS transistor which has a gate and first and second diffusion regions and which is formed on the major surface. The semiconductor device also includes a laminated structure of a SOG layer, wherein the laminated structure is composed of a base layer and a surface layer formed on the base layer and is formed over the MOS transistor and wherein the surface layer is denser than the base layer.

Abstract: A method for removing photoresist is described. A substrate having a photoresist to be removed thereon is provided, and then an ashing process is performed to remove most of the photoresist. The substrate is irradiated with UV light, and the remaining photoresist and polymer are stripped with stripping solvents after UV irradiation.

Abstract: A method of forming a floating gate of a memory cell is provided. A substrate having at least a trench is provided. Next, a tunnel oxide layer is formed on a surface of the trench. Next, a conductive layer is filled in the trench. Next, two-step etching process is carried out to form a first floating gate and a second floating gate having a top corner with sharp edge over the sidewalls of the trench.

Abstract: Disclosed is a method for forming a shallow trench isolation. A pad oxide layer is formed on a semiconductor substrate. First and second stopping layers are sequentially formed on the pad oxide layer. The second stopping layer, the first stopping layer, the pad oxide layer and the semiconductor substrate are etched to form a second stopping layer pattern, a first stopping layer pattern, a pad oxide layer pattern and a trench. A trench inner wall oxide layer is formed at an inner surface portion of the trench. A nitride layer liner is formed on a resulted structure. A field oxide layer is formed in the trench. By selectively removing the second stopping layer pattern, the first stopping layer pattern is exposed. Then, the first stopping layer pattern is removed. Since the chemical mechanical polishing is stopped at the second stopping layer pattern, the first stopping layer pattern is prevented from erosion when the chemical mechanical polishing process is carried out.

Abstract: A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer (60) is formed over the metal silicide layer and a conductive layer (70) formed over the dielectric layer. The formed layers are etched by a combination of multi-step dry and wet process to form high precision integrated circuit capacitors.

Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Abstract: In a method for producing a bonding wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating them at the micro bubble layer as a border, a peripheral portion of a thin film formed on the base wafer is removed after the delamination step. Preferably, a region of 1-5 mm from the peripheral end of the base wafer is removed. In the production of a bonding wafer by the hydrogen ion delamination method, there can be provided a bonding wafer free from problems such as generation of particles from peripheral portion of the wafer and generation of cracks in the SOI layer.

Abstract: A processing system and method for chemical oxide removal (COR), wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.

Abstract: A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.

Abstract: The present invention relates to a method for fabricating a semiconductor device. In more detail of the aforementioned method, a first mask layer covering a cell region is formed on an insulation layer in the cell region. Meanwhile, a second mask layer is formed in a peripheral circuit region with a predetermined distance from the first mask layer. The insulation layer is then etched with use of the first and the second mask layers as an etch mask to form a spacer at both sidewalls of each gate line pattern in the peripheral region and simultaneously form a guard beneath the second mask layer. The first and the second mask layers are removed thereafter. Next, a third mask layer opening the cell region but covering the whole regions including a guard region in the peripheral circuit region is formed. A wet etching process is performed to the insulation layer remaining in the cell region by using the third mask layer as an etch mask.

Abstract: A method of etching nitride over oxide is provided for the formation of vertical profile nitride spacers with high uniformity while maintaining the integrity of underlying thin oxide layers. The method includes providing a first gas flow including a first fluorocarbon and a second fluorocarbon at a first ratio, applying a first quantity of power to the first gas flow to create a first plasma, etching a first portion of a silicon nitride layer with the first plasma, providing a second gas flow including the first fluorocarbon and the second fluorocarbon at a second ratio greater than the first ratio, applying a second quantity of power to the second gas flow to create a second plasma, and etching a second portion of the silicon nitride layer with the second plasma.

Abstract: The invention includes semiconductor processing methods, including methods of forming capacitors. In one implementation, a semiconductor processing method includes providing a semiconductor substrate comprising a layer comprising at least one metal in elemental or metal alloy form. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. At least a portion of the layer is etched in a halogenide, ozone and H2O comprising ambient.

Abstract: A method for fabricating semiconductor microstructures with a combination of etching steps, i.e. local RIE, isotropic, etc. followed by deep anisotropic etching.

Abstract: An electrical and thermal contact which includes an intermediate conductive layer, an insulator component, and a contact layer. The insulator component is fabricated from a thermally insulative material and may be sandwiched between the intermediate conductive layer and the contact layer. The electrical and thermal contact may be fabricated by forming a first conductive layer on a surface of the semiconductor device, depositing a dielectric layer adjacent the first layer, patterning the dielectric layer to define the insulator component, and forming a second conductive layer adjacent the insulator component and in partial contact with the first layer. The first and second layers are respectively patterned to define the intermediate conductive layer and the contact layer. The electrical and thermal contact effectively contains heat within and prevents heat from dissipating from a contacted structure, such as a phase change component that may be switched between two or more electrical states.

Abstract: In a method of forming a self-aligned contact, gates are formed on a semiconductor substrate in a striped pattern. Bit lines are formed in a striped pattern that extends cross-wise to the gates. The bit lines are isolated from one another by a first interlayer insulation layer. Next, a second interlayer insulation layer is formed between the bit lines, and a photoresist film pattern is formed on the second interlayer insulation layer. The photoresist film pattern is used for forming contact holes extending between the gates down to conductive pads. The contact holes are filled to form conductive plugs that contact the conductive pads. The photoresist film pattern is formed as a series of stripes which extend parallel to the gates.

Abstract: A process of forming a bottle-shaped trench. A semiconductor substrate with a trench is provided, on which a pad layer and hard mask layer are sequentially formed. A dielectric layer is formed on the hard mask layer to fill the trench. Part of the dielectric layer is etched to expose the sidewall of the upper portion of the trench. A spacer is formed on the sidewall. The residual dielectric layer in the trench is removed, and the partial trench not covered by the spacer is etched to a bottle shape.

Abstract: Integrated semiconductor devices are manufactured by providing a layered semiconductor structure having an exposed surface and providing a mask on the exposed surface thereby defining a masked region in the layered structure underneath said mask. The mask has a main direction of extension with a width across the main direction and an end portion. The layered structure is etched over a given depth starting from the exposed surface, whereby the masked region is left substantially unaffected by the etching process and has an end surface extending underneath the end portion of the mask. A further layered semiconductor structure is grown around the masked region to produce an integrated layered semiconductor structure having at the end surface an interface between the layered structure and the further grown structure. The mask width is selected to be less than 50 microns.

Abstract: An operating semiconductor layer is formed in such a manner that amorphous silicon layer is formed to be shaped so that it has a wide region and a narrow region and the narrow region is connected to the wide region at a position asymmetric to the wide region, and the amorphous silicon layer is crystallized by scanning a CW laser beam from the wide region toward the narrow region in a state that a polycrystalline silicon layer as a heat-retaining layer encloses the narrow region from a side face through the silicon oxide layer.

Abstract: An aqueous solution containing sulfuric acid and hydrogen peroxide is used for a soft etchant in a soft etching step in a smear removing process performed prior to a catalyst applying process for chemical copper plating after formation of via holes through an insulating layer of a multi-layer substrate by irradiation of laser. The concentration of sulfuric acid is 2.4 times or less than the concentration of hydrogen peroxide. Preferably, the concentration of sulfuric acid is in a range of 9 to 90 g/l, and the concentration of sulfuric acid is lower than the concentration of hydrogen peroxide. More preferably, the concentration of sulfuric acid is in a range of 9 to 18 g/l, and the concentration of hydrogen peroxide is in a range of 33 to 38.5 g/l. As a result, smear can be certainly removed without excessively etching a conductive layer in the smear removing process.

Abstract: Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

Abstract: A method and an apparatus for manufacturing, via a single fabrication line, circuits that are radiation tolerant and also circuits that are radiation intolerant. When production calls for radiation-tolerant circuits, low-pressure chemical vapor deposition is advantageously used to deposit an electrically-insulating material, such as silicon dioxide, in trenches to provide electrical isolation between adjacent semiconductor devices. When production requires radiation-intolerant circuits, as may be required for export, then the trenches are filled via a procedure that deposits an electrically-insulating material that, on exposure to ionizing radiation, generates a suitably large amount of “positive charge traps.” One procedure suitable for creating such positive charge traps is high-density plasma chemical vapor deposition (HDPCVD).

Abstract: A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer (60) is formed over the metal silicide layer and a conductive layer (70) formed over the dielectric layer. The formed layers are etched by a combination of multi-step dry and wet process to form high precision integrated circuit capacitors.

Abstract: A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF3 molecules and the like contained in an etching gas, and compounds thus formed adhere to a surface of a silicon dioxide layer at side walls and a bottom portion of a via hole. As a result, once the material layer is exposed during etching for forming a via hole, thereafter, the etching rate decreases. Accordingly, even if there is misalignment of a via hole pattern with respect to a first wiring pattern when the via hole pattern is formed by lithography, etching of the silicon dioxide layer does not proceed to an underlying silicon substrate. Thus, short circuits are not formed between the first wiring and the silicon substrate via a second wiring layer which is deposited later.

Abstract: An in-process microelectronics device is treated by applying a heated liquid to the surface of the in-process microelectronics device, removing a portion of the liquid from the surface of the in-process microelectronics device and applying anhydrous HF gas to the surface of the in-process microelectronics device.

Abstract: A method of unblinding an alignment mark comprising the following steps. A substrate having a cell area and an alignment mark within an alignment area is provided. An STI trench is formed into the substrate within the cell area. A silicon oxide layer is formed over the substrate, filling the STI trench and the alignment mark. The silicon oxide layer is planarized to form a planarized STI within the STI trench and leaving silicon oxide within the alignment mark to form a blinded alignment mark. A wet chemical etchant is applied within the alignment mark area over the blinded alignment mark to at least partially remove the silicon oxide within the alignment mark. The remaining silicon oxide is removed from within the blinded alignment mark to unblind the alignment mark. A drop etcher apparatus is also disclosed.

Abstract: The present invention relates to etching for removing a carbon thin film formed on a surface of a sample, to prevent a damage on a sample and eliminate the necessity of providing a special device (such as vacuum pump) as is required in plasma etching. A sealed reaction chamber 100A in which a sample 500 formed with a carbon thin film 510 on its surface is to be set, a gas feed means 200A for feeding argon gas which is an inert gas Ar into which a predetermined proportion of oxygen gas O2 has been mixed from one end to the interior of the reaction chamber 100A, an exhaust means 300A for discharging carbon dioxide gas CO2 from the downstream side of the inert gas Ar fed from the gas feed means 200A, and a heating means 400A for heating the sample 500 to 550° C. or higher are provided.

Abstract: A method for eching a recess in a polysilicon region of a semiconductor device by applying a solution of NH4OH in water to the polysilicon.

Abstract: A process for fabricating a microelectromechanical optical component from a silicon substrate is disclosed. The component comprises optical propagation guides; a wall which can move with respect to the propagation guides; and an electrostatic actuator associated with return means formed by at least one beam capable of causing the moving wall to move with respect to the rest of the substrate. The substrate is single-crystal silicon having (111) crystallographic planes parallel to the plane of the substrate. The process comprises a first series of deep reactive ion etching steps during which the heights of the moving wall, of the electrodes of the actuator, and of the beams of the return means of the actuator are defined with different values, and a second wet etching step, making it possible to free the moving wall, the electrodes and the beams from the rest of the substrate.

Abstract: A method of forming a conductive plug in a contact hole comprising: providing a wafer having a conductive layer comprising silicon adjacent a dielectric layer comprising silicon oxide, and a contact hole disposed in the dielectric layer, the contact hole having surfaces that include sidewalls formed in the dielectric layer and a bottom defined by the conductive layer, a contaminant material being disposed over at least a portion of the conductive layer defining the bottom of the contact hole, the dielectric layer having a surface in which the contact hole terminates in an opening opposing the bottom; depositing a layer of a barrier material on the work object, the layer having a substantially uniform thickness from the surface at the opening of the contact hole to the bottom of the contact hole; and depositing a layer of a protective material barrier around at least opening of the contact hole; etching the material at the bottom of the contact hole to expose the contaminant material while retaining protective

Abstract: A semiconductor device having a bump electrode comprising a substrate having a dielectric layer formed thereon, an aluminum contact pad on the substrate wherein at least a portion of the aluminum contact pad is exposed through the dielectric layer on the substrate. The aluminum contact pad is provided with an under bump metallurgy including a aluminum layer formed on the exposed portion of the aluminum contact pad, a nickel-vanadium layer formed on the aluminum layer and a titanium layer formed on the nickel-vanadium layer. A gold bump formed on the titanium layer acts as the bump electrode.

Abstract: An improved and novel method of forming a tiered structure, such as a T-gate structure, including the fabrication of a stabilized resist layer that provides for the prevention of interlayer intermixing with the deposition of subsequent resist layers. The method includes patterning a base resist layer to provide for an opening which will form the stem of the tiered structure and subsequently stabilizing the resist base layer without deforming the stem opening. Next, a resist stack is deposited on an uppermost surface of the stabilized resist layer. Patterning the resist stack provides for an opening on an uppermost layer or portion, and a reentrant profile in a portion of the resist stack adjacent the stabilized resist layer. Metallization and subsequent removal of the resist layers results in a tiered structure, such as a T-gate structure, formed using only low to medium molecular weight, linear polymeric materials such as those used in positive optical resists in optical lithography.

Abstract: Disclosed is a method of forming a thick silicon oxide layer upon or internal to a silicon structure. The method is particularly useful in creating isolation regions within a silicon-containing structure, where such isolation regions can withstand high voltages. The electrically isolating thick silicon oxide layer or isolation regions can be shaped, machined, or etched to provide feedthroughs for vertical or horizontal interconnects. The feedthroughs may be coated with metal or filled with metal to provide the interconnect.

Abstract: A method for forming silicon quantum dots and a method for fabricating a nonvolatile memory device using the same, suitable for high speed and high packing density. The method for forming silicon quantum dots includes the steps of forming a first insulating film on a semiconductor substrate, forming a plurality of nano-crystalline silicons on the first insulating film, forming a second insulating film on the first insulating film including the nano-crystalline silicons, partially etching the second insulating film and the nano-crystalline silicons, and oxidizing surfaces of the nano-crystalline silicons.

Abstract: A cleaning/fluid-feeding head 22 integrates a cleaning head portion 60 and a fluid-feeding head portion 70. The cleaning head portion 60 includes an organic substance cleaning unit 62, an inorganic substance cleaning unit 64, a rinsing unit 66 and a drying unit 68. The organic substance cleaning unit 62, inorganic substance cleaning unit 64 and rinsing unit 66 selectively clean pattern forming regions 108 on a substrate 10 by feeding thereto a first cleaning fluid 74, second cleaning fluid 80 and pure water 88, respectively. The drying unit 68 dries the rinsed pattern forming regions 108 by blowing hot air 96 thereonto. The fluid-feeding head portion 70 selectively feeds a liquid pattern forming material 102 to the cleaned pattern forming regions 108.

Abstract: An article of manufacture comprises a substrate and a layer of N(x)Y(1-x)AIO3 on the substrate where x is a molar fraction greater than zero and less than one, and N is an element selected from La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The article may be an electronic device further comprising an electrode electrically isolated from the substrate by the layer. In particular, the dielectric properties of the layer are such that the layer is especially although by no means exclusively useful for electrically isolating gate electrodes in field effect transistor devices. The layer may be formed on the substrate via molecular beam epitaxy.

Abstract: A method for forming bottle trenches. The method comprises providing a substrate formed with a pad stack layer on the top, and a deep trench with protective layer on the upper portions of sidewalls thereof, implanting ions into the lower portions of sidewalls and bottom of the trench not covered by the protective layer to amorphize the atomic structure of the sidewalls and bottom, oxidizing the amorphous sidewalls and bottom of the trench to form a bottle-shaped oxide layer thereon, and removing the bottle-shaped oxide layer.

Abstract: The invention provides a method for forming a capacitor that enables to form HSG-Si on the entire surface of the exposed surface of a cylindrical bottom electrode. A core pattern is formed on the cylinder core layer on a semiconductor substrate, and an amorphous silicon film is formed so as to cover the core pattern. The amorphous silicon film on the cylinder core layer is removed so that the amorphous silicon film remains on the inside wall of the core pattern, and a bottom electrode comprising the amorphous silicon film is formed on the inside wall of the core pattern. The cylinder core layer that is the component of the core pattern is etching-removed, and then the natural oxide film generated on the surface of the bottom electrode and the amorphous silicon surface layer that is the component of the bottom electrode is etching-removed. Thereafter, HSG-Si is formed on the surface of the bottom electrode.

Abstract: A resist removing composition having a superior capability for removing a resist, polymer, organometallic polymer and etching by-products such as metal oxide, which does not attack underlying layers exposed to the composition and which does not leave residues after a rinsing step. The resist removing composition contains alkoxy N-hydroxyalkyl alkanamide and a swelling agent.

Abstract: According to the present invention, by applying a basic surface-processing agent to a film underlying a resist, the excessive photoacid present at the interface between the resist and the front-end film is neutralized and the pattern shape can be controlled. The present invention provides a method of manufacturing a semiconductor device including the steps of, forming an insulating film on a surface, applying a surface processing agent containing of at least a solvent and a basic component on the insulating film, applying a resist on the insulating film thus applied with the surface processing agent, patterning the resist by lithography, and transferring a resist pattern to the insulating film by a dry etching process.

Abstract: A method for manipulating MEMS devices integrated on a semiconductor wafer and intended to be diced one from the other includes bonding of the semiconductor wafer including the MEMS devices on a support with interposition of a bonding sheet. The method may also include completely cutting or dicing of the semiconductor wafer into a plurality of independent MEMS devices, and processing the MEMS devices diced and bonded on the support in a treatment environment for semiconductor wafers. A support for manipulating MEMS devices is also included.

Abstract: Disclosed is a micromechanical system fabrication method using (111) single crystalline silicon as a silicon substrate and employing a reactive ion etching process in order to pattern a microstructure that will be separated from the silicon substrate and a selective release-etching process utilizing an aqueous alkaline solution in order to separate the microstructure from the silicon substrate. According to the micromechanical system fabrication method of the present invention, the side surfaces of microstructures can be formed to be vertical by employing the RIE technique. Furthermore, the microstructures can be readily separated from the silicon substrate by employing the selective release-etching technique using slow etching {111} planes as the etch stop in an aqueous alkaline solution. In addition, etched depths can be adjusted during the RIE step, thereby adjusting the thickness of the microstructure and the spacing between the microstructure and the silicon substrate.

Abstract: A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer (60) is formed over the metal silicide layer and a conductive layer (70) formed over the dielectric layer. The formed layers are etched by a combination of multi-step dry and wet process to form high precision integrated circuit capacitors.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.

Abstract: A process of removing photoresist, previously subjected to ion implantation, from the surface of a workpiece. The process involves contacting the workpiece with a composition which includes liquid or supercritical carbon dioxide and between about 2% and about 20% of an alkanol having the structural formula CxX2x+1OH, where X is fluorine, hydrogen or mixtures thereof; and x is an integer of 1 to 8, said percentages being by volume, based on the total weight of the composition.

Abstract: A method for passivating a target layer. There is first provided a substrate. There is then formed over the substrate a target layer, where the target layer is susceptible to corrosion incident to contact with a corrosive material employed for further processing of the substrate. There is then treated, while employing a first plasma method employing a first plasma gas composition comprising an oxidizing gas, the target layer to form an oxidized target layer having an inhibited susceptibility to corrosion incident to contact with the corrosive material employed for further processing of the substrate. Finally, there is then processed further, while employing the corrosive material, the substrate. The method is useful when forming bond pads within microelectronic fabrications.

Abstract: A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Abstract: According to this invention, residues generated after selectively removing a low-dielectric-constant film such as SiOC can be effectively removed without damage on an insulating film or metal film. Specifically, residues 126 and 128 generated after forming an interconnect trench in an SiOC film 116 are removed using a fluoride-free weak alkaline amine stripper. After the removing step, the wafer is rinsed with isopropyl alcohol and then dried without drying with pure water.

Abstract: Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly damascene and dual damascene metallization, the method advantageously lines insulating surfaces with a barrier material. The selective formation allows the deposition to be “bottomless,” thus leaving the conductive material at a via bottom exposed for direct metal-to-metal contact when further conductive material is deposited into the opening after barrier formation on the insulating surfaces. Desirably, the selective deposition is accomplished by atomic layer deposition (ALD), resulting in highly conformal coverage of the insulating sidewalls in the opening.