Abstract: Presented is a method of enhancing the rate of removal of a photoresist layer from wafers of semiconductor material after the latter have gone through various process steps to define the patterns of integrated circuits. The method includes heating the wafer and treating it with low-pressure steam in a vacuum environment before starting to remove the photoresist by plasma or wet solutions. This pre-treatment of the photoresists allows the time for removing the photoresist to be reduced substantially and eliminates problems from residue.

Abstract: A cleaning solution for cleaning a semiconductor substrate is formed by mixing an amount of citric acid and an amount of ammonia in deionized water. In one embodiment, the amount of citric acid is in a range from about 0.18% by weight to about 0.22% by weight and the amount of ammonia is in a range from about 0.0225% by weight to about 0.0275% by weight, and the cleaning solution has a pH of about 4. A method for cleaning a semiconductor substrate having a polished copper layer in which a concentrated cleaning solution is mixed with deionized water proximate to a scrubbing apparatus also is described.

Abstract: In a semiconductor device of this invention, a first trench having a uniformly inclined surface at a predetermined angle is formed downward from the surface of a semiconductor substrate. A second trench is formed vertically downward from the first trench. These trenches are filled with an insulating film to form a trench element isolation structure. The inclined surface of the first trench can disperse stepwise the electric field generated at an element isolation end and can relax concentration of electrical charges. The second trench vertically extending downward can reliably isolate elements. The semiconductor device of this invention has a trench element isolation structure made of the insulating film filling the trenches. The outer edge of a portion projecting from the semiconductor substrate is covered with a thermal oxide film formed by heat-treating a polysilicon film. The structure is more resistant to etching, cleaning, and the like.

Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch which produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.

Abstract: This is a method of planarizing a surface of a photoresist layer formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. The following steps are performed. Form a blanket, first photoresist layer above the blanket silicon nitride with a damaged surface caused by the gap. Then strip the first photoresist layer leaving a residual portion of the first photoresist layer in the gap. Next, form a blanket, second photoresist layer above the blanket layer. The gap has a neck with a width from about 200 Å to about 500 Å and the gap has a deep, pocket-like cross-section with a width from about 500 Å to about 1,200 Å below the narrow neck. Partial stripping of the first photoresist layer, which follows, is performed by an etching process including wet and dry processing.

Abstract: A process is disclosed whereby a 5-50-nanometer-thick conformal tungsten coating can be formed over exposed semiconductor surfaces (e.g. silicon, germanium or silicon carbide) within a microelectromechanical (MEM) device for improved wear resistance and reliability. The tungsten coating is formed after cleaning the semiconductor surfaces to remove any organic material and oxide film from the surface. A final in situ cleaning step is performed by heating a substrate containing the MEM device to a temperature in the range of 200-600 ° C. in the presence of gaseous nitrogen trifluoride (NF3). The tungsten coating can then be formed by a chemical reaction between the semiconductor surfaces and tungsten hexafluoride (WF6) at an elevated temperature, preferably about 450° C. The tungsten deposition process is self-limiting and covers all exposed semiconductor surfaces including surfaces in close contact.

Abstract: A method of forming an electrical contact to semiconductive material includes forming an insulative layer over a contact area of semiconductive material. A contact opening is etched through the insulative layer to the semiconductive material contact area. Such etching changes an outer portion of the semiconductive material exposed by the etching. The change is typically in the form of modifying crystalline structure of only an outer portion from that existing prior to the etch. The changed outer portion of the semiconductive material is etched substantially selective relative to semiconductive material therebeneath which is unchanged. The preferred etching chemistry is a tetramethyl ammonium hydroxide solution. A conductive material within the contact opening is formed in electrical connection with the semiconductive material.

Abstract: A method for fabricating funnel-shaped vias in semiconductor devices with an improved profile amelioration of the sharp angles at the onset of the via and at the intersection between the wet etch section (i.e., the bowl-shaped section) and the dry etch section (i.e., the straight section).

Abstract: A method of protecting a tungsten plug from corroding. After a tungsten plug is formed in a substrate, a wire is formed on the substrate to couple with the tungsten plug. The substrate is dipped into an electrolyte solution. The electrolyte solution is acid or alkaline enough to discharge charges accumulated on the wire. Then, a wet cleaning process is performed to remove polymer formed on the wire.

Abstract: A processing solution containing hydrogen peroxide, hydracid fluoride salt, and water is used for pre-cleaning prior to a step of forming a gate oxide film 14 by subjecting a silicon wafer 1 to a heat treatment. Tetraalkyl ammonium fluoride, ammonium fluoride or the like is used as hydracid fluoride salt.

Abstract: A centrifugal spray processor for dispensing a stream of ozonated water toward one or more semiconductor wafers at a non-parallel angle that is inclined from the plane of the surface of the semiconductor wafer. The spray processor includes one or more supports for receiving a plurality of semiconductor wafers and a spray post for dispensing ozonated water from a reservoir onto the semiconductor wafers. The spray post includes a plurality of nozzles that are configured to dispense ozonated water at a generally downward angle toward the surface of the semiconductor wafer. The angle of incidence of the stream of ozonated water from the spray post as measured from the plane of the semiconductor is greater than 0 degrees, and is preferably greater than about 0 degrees and less than or equal to about 30 degrees depending upon the configuration of the spray post and the semiconductor wafers.

Abstract: Disclosed are improved and simplified methods of forming trench isolation regions. A photoresist pattern having an opening therein is directly formed on a bare semiconductor substrate. The bare semiconductor substrate is etched through the opening in the photoresist pattern to form a trench in the substrate. The photoresist pattern is then isotropically etched to enlarge the size of the opening. A spin-on material layer is coated overlying the substrate surface to fill the trench and the enlarged opening, and then etched back until the photoresist pattern is exposed. After removing the photoresist pattern, the spin-on material layer is cured to form a trench isolation region which are less susceptible to edge defects.

Abstract: Provided is a method for producing regularly ordered narrow pores excellent in linearity, and a structure with such narrow pores. A method for producing a narrow pore comprises a step of radiating a particle beam onto a workpiece, and a step of carrying out anodic oxidation of the workpiece having been irradiated with the particle beam, to form a narrow pore in the workpiece.

Abstract: A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure.

Abstract: An etching method includes providing a first insulating material layer on a substrate assembly surface and a second insulating material layer on the first insulating material layer. The first insulating material layer has an etch rate that is greater than the etch rate of the second insulating material layer when exposed to an etch composition. Portions of the first insulating material layer and the second insulating material layer are removed using at least the etch composition. Various types of structures (e.g., contacts, capacitors) are formed with use of the method.

Abstract: The present invention discloses a method for fabricating a semiconductor device. In a process for forming a contact plug, a pad polycrystalline silicon layer pattern is formed at the presumed contact region, and a contact plug is formed according to a selective epitaxial growth (SEG) method using the pad polycrystalline silicon layer pattern as a seed. Accordingly, a higher contact plug is formed by improving a growth rate of the SEG process, and thus a succeeding process can be easily performed. In the SEG process, a contact property is improved by compensating for a semiconductor substrate damaged in a process for forming an insulating film spacer at the sidewalls of a gate electrode. As a result, the property and yield of the semiconductor device are remarkably improved.

Abstract: A substrate processing apparatus (1) for processing wafers (W) has a first processing chamber (2) capable of containing the wafers (W) and a second processing chamber (4) capable of containing the wafers (W). The second processing chamber (4) is formed below and near the first processing chamber (2) and is capable of communicating with the first processing chamber (2). A wafer guide (6) carries the wafers (W) vertically between the first and second processing chambers (2, 4). A shutter (7) is opened to allow the first and second processing chambers (2, 4) to communicate with each other and is closed to isolate the same from each other. A steam supply system (8) including steam supply port, an ozone gas supply system (9) including ozone gas supply port and an IPA supply system (10) including IPA supply port are combined with the first processing chamber (2).

Abstract: A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process, such as an activation anneal or a salicidation anneal of the source and drain of the field effect transistor, using relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and a crystallization enhancing layer is deposited on the bottom wall of the gate opening.

Abstract: The present disclosure pertains to our discovery that a particular sequence of processing steps will lead to the formation of a rounded top corner on a trench formed in a semiconductor substrate.

Abstract: The present invention relates to a method for removing a first dielectric layer of a semiconductor wafer. The first dielectric layer is formed on the surface of a second dielectric layer of the semiconductor wafer. The method comprises performing a chemical mechanical polishing (CMP) process on the first dielectric layer to remove a predetermined thickness of the first dielectric layer, measuring the remaining thickness of the first dielectric layer, providing an etching table having a plurality of thickness ranges of the remaining first dielectric layer and corresponding etching back procedure or parameters of each of the thickness ranges, and performing an etching back process to horizontally remove the remaining first dielectric layer according to the etching back procedure or parameters of the thickness range corresponding to the measured thickness of the remaining first dielectric layer.

Abstract: The invention encompasses methods for cleaning surfaces of wafers or other semiconductor articles. Oxidizing is performed using an oxidation solution which is wetted onto the surface. The oxidation solution can include one or more of: water, ozone, hydrogen chloride, sulfuric acid, or hydrogen peroxide. A rinsing step removes the oxidation solution and inhibits further activity. The rinsed surface is thereafter preferably subjected to a drying step. The surface is exposed to an oxide removal vapor to remove semiconductor oxide therefrom. The oxide removal vapor can include one or more of: acids, such as a hydrogen halide, for example hydrogen fluoride or hydrogen chloride; water; isopropyl alcohol; or ozone. The processes can use centrifugal processing and spraying actions.

Abstract: A wet and vapor acid etching method releases a microelectromechanical systems (MEMS) structure from a substrate by dissolving a sacrificial layer disposed between the MEMS and the substrate. The sacrificial layer may be a silicon dioxide (SiO2) layer having a field portion over which the MEMS does not extend and a support portion over which the MEMS does extend. The field portion of the SiO2 layer is quickly removed using conventional wet hydrofluoric (HF) etching followed by rinsing and drying and then the support portion is removed using conventional vapor HF etching from a solution greater than 45% by weight percent. The wet HF chemical etch quickly removes the large field portion of the sacrificial layer. The HF vapor etch removes the small support portion of the sacrificial layer below the MEMS to release the MEMS from the substrate without stiction thereby preventing damage to the MEMS when released.

Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch which produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.

Abstract: A method for manufacturing a shallow trench isolation structure. A two-stage process is performed to form a trench. An anisotropic etching operation is conducted to form a smaller trench, and then an isotropic etching operation is conducted to form a wider trench underneath. Hence, a portion of trench extends into the substrate below the device-forming regions. An insulating material is deposited to fill the trench. Therefore, the degree of electrical insulation between devices in neighboring active regions is increased without affecting the layout of device on the substrate. Moreover, the degree of overlap between the source/drain region and the substrate is reduced. Hence, junction capacitance is lowered and operating speed of the device is increased.

Abstract: A non-volatile semiconductor memory device and a manufacturing method of the same where an etching residue generating short-circuit between gates is made harmless or a device is miniaturized are obtained. The method includes the steps of forming on a semiconductor substrate, a first gate layer and a second gate layer, forming a second gate electrode by etching the second gate layer, forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask, and removing a residue left on a step portion by isotropic etching.

Abstract: This invention teaches methods and apparatus for forming self-aligned photosensitive material spacers about protruding structures in semiconductor devices. One embodiment of the invention is a method for forming a lightly doped drain (LDD) structure, utilizing disposable photosensitive material spacers. A second embodiment of the invention comprises a method for forming a transistor, having salicided source/drain regions, utilizing photosensitive polyimide spacers for forming the salicided source/drain regions, without disposing of the spacers. A third embodiment of the invention comprises a method for creating an offset from a protruding structure on a semiconductor substrate, using disposable photosensitive material spacers.

Abstract: A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.

Abstract: A process chamber within which a wafer can moved between a transfer position, an etch position and a liquid application position with a single motion system. The process chamber is a spin-type apparatus including a rotatable chuck driven by a spin motor combined with a movable pedestal. The pedestal is preferably movable along with the chuck and the spin motor with a wafer supporting portion of the chuck located in an internal chamber that is defined by a rinse bowl portion of a lower chamber assembly that is sealingly connected to the top cover member. The pedestal is displaceable between any and all of its positions as driven by a single linear motion driving device. In a first position, the pedestal itself can also form an effective seal with the top cover member to create an etching chamber. In a transfer position, the pedestal can be positioned to provide access through a wafer transfer gate, such as by a robot.

Abstract: This invention teaches methods and apparatus for forming self-aligned photosensitive material spacers about protruding structures in semiconductor devices. One embodiment of the invention is a method for forming a lightly doped drain (LDD) structure, utilizing disposable photosensitive material spacers. A second embodiment of the invention comprises a method for forming a transistor, having salicided source/drain regions, utilizing photosensitive polyimide spacers for forming the salicided source/drain regions, without disposing of the spacers. A third embodiment of the invention comprises a method for creating an offset from a protruding structure on a semiconductor substrate, using disposable photosensitive material spacers.

Abstract: The present invention relates to a method for providing patterned recess formation in a previously recessed area of a semiconductor structure, i.e. DRAM trench capacitor, using acid diffusion to selectively activate some, but not all of the acid sensitive material that is filled within the recessed areas of such structures. By employing the method of the present invention, it is possible to recess all the previously recessed areas at the same time providing the same level of recessed acid sensitive material within the previous recessed areas, recess some of the previously recessed areas to a desired level leaving other portions of the structure unrecessed, or recessing the previously recessed areas to contain different levels of the acid sensitive material.

Abstract: Disclosed herein is a method of forming a gate in a semiconductor device capable of preventing a deterioration in the property of a gate electrode formed of a refractory metal in a heat treatment process.

Abstract: A method for planarizing a semiconductor substrate uses a difference in etch selectivity of insulators on the semiconductor substrate. The method comprises the steps of wet-etching the second and first insulating layers at upper edges of the elevated region until portions of the first insulating layer are exposed at the upper edges, forming a third insulating layer on the first and second insulating layers, and wet-etching the third and second insulating layers until an upper surface of the first insulating layer is exposed. During the wet-etching, the second insulating layer is etched faster than the third insulating layer. With this method, the semiconductor substrate has an even surface.

Abstract: A method for preparing a semiconductor substrate for subsequent silicide formation. In one embodiment, the present invention subjects the semiconductor substrate to an ashing environment. In the present embodiment, the ashing environment is comprised of H2O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants on the semiconductor substrate are removed. Next, the present invention subjects a mask covering a polysilicon stack to a mask-removal ashing environment. In the present embodiment, the mask-removal ashing environment is comprised of an O2 plasma. In so doing, the mask covering the polysilicon stack is removed. As a result, the semiconductor substrate and the top surface of the polysilicon stack are prepared for subsequent silicide formation thereon.

Abstract: In a method for preparing a semiconductor device wherein a first silicon oxide film, a second silicon oxide film and a silicon nitride film are sequentially deposited on a silicon substrate, and both silicon oxide films and the silicon nitride film are patterned, a patterned resist 45 is formed on the silicon nitride film, the silicon nitride film is etched with phosphoric acid the resist serving as a mask, and both silicon oxide films are etched with hydrofluoric acid the resist serving as a mask.

Abstract: A method for forming within a semiconductor substrate layer employed within a semiconductor microelectronics fabrication a shallow trench structure with improved surface properties. There is provided a silicon semiconductor substrate layer. There is then formed over the substrate a patterned photoresist etch mask layer containing the trench pattern. There may be an optional layer formed intermediate between the substrate layer and the patterned photoeresist etch mask layer comprising a pad oxide sub-layer and a silicon nitride etch stop sub-layer. There is then etched the trench pattern employing the photoresist etch mask layer into the substrate layer with a first anisotropic subtractive etching environment. There is then further etched the anisotropically etched trench pattern with a second isotropic subtractive etching environment to form the isotropically etched trench with smooth surfaces.

Abstract: A method of fabricating a node contact opening includes formation of a dielectric layer on a substrate. An opening is formed with C4F8/Ar/CH2F2 as an etchant. A portion of the dielectric layer under the opening is etched with CHF3/CO as an etchant until the substrate is exposed. A node contact opening is formed.

Abstract: A method for post plasma etch cleaning a semiconductor wafer is provided. The semiconductor wafer has a plurality of layers formed thereon, and one of the plurality of layers is an oxide layer that has an overlying photoresist mask. The method includes plasma etching a via feature in the oxide layer. The plasma etching is configured to generate a polymer film on sidewalls of the via feature. An ashing operation is then performed to remove the photoresist mask. The method then moves to brush scrubbing the oxide layer and the via feature defined in the oxide layer with first chemicals in a first brush station. Brush scrubbing the oxide layer and the via feature follows with DI water in the first brush station. Then, the oxide layer and the via feature are brush scrubbed with second chemicals in a second brush station. In the same second brush station, the oxide layer and the via feature are scrubbed with DI water.

Abstract: A shallow trench isolation structure having rounded corners is formed at edge-rounding oxidation temperatures employing a two-step trench etching technique. Isotropic etching is first performed, undercutting a pad oxide layer and a barrier nitride layer. Subsequently, anisotropic etching is conducted to form the remainder of the trench. The isotropic etch enables the thermal oxidation to form an oxide liner with rounded edges and reduced stress at relatively low temperatures, e.g. 900° C. or less, even using water vapor as the oxidizing species.

Abstract: The present invention provides a method of fabricating a field-effect transistor comprising the steps of forming a masking layer having an opening therein on laminated compound semiconductor layers, removing a portion of the laminated layers using an etching solution acting through the opening and creating a gate-forming recess having sidewalls tapering in a direction away from the masking layer, filling the gate-forming recess with gate metal and forming a gate electrode, and forming a recess around the gate electrode.

Abstract: A method for forming a resist pattern includes the steps of: forming a dummy pattern on a semiconductor substrate using one type of a photosensitive resist; applying a resist mask on the semiconductor substrate so as to bury the dummy pattern using an opposite type of a photosensitive resist; forming a mixing layer at the interface between the dummy pattern and the resist mask by applying a heat treatment; and dissolving and removing the dummy pattern with an etchant in which the mixing layer and the resist mask are indissoluble so as to form an opening having a space width smaller than a width of the dummy pattern in the resist mask.

Abstract: A method for reducing polymer deposition on vertical surfaces of metal lines etched from a metallization layer disposed above a substrate. The method includes forming a hard mask layer above the metallization layer and providing a photoresist mask above the hard mask layer. The method further includes employing the photoresist mask to form a hard mask from the hard mask layer. The hard mask has patterns therein configured to form the metal lines in a subsequent plasma-enhanced metallization etch. There is also included removing the photoresist mask. Additionally, there is included performing the plasma-enhanced metallization etch employing the hard mask and an etchant source gas that includes Cl2 and at least one passivation-forming chemical, wherein the plasma-enhanced metallization etch is performed without employing photoresist to reduce the polymer deposition during the plasma-enhanced metallization etch.

Abstract: Hydrofluoric acid (HF) mixed with water and often buffered with ammonium fluoride is a standard silicon dioxide wet etchant which is followed by a rinse. An improved silicon dioxide etch is vapor HF which may be followed by a water vapor rinse. The invention discloses a further improved silicon dioxide etch. Following an initial exposure to vapor HF for oxide removal, a first insitu water rinse occurs. A second exposure to vapor HF then occurs and is followed by a second insitu water rinse. Water, rather than water vapor, aids in freeing particles from the wafer surface. During both the water rinses, the wafer may be rotated at increasing speeds to aid in sweeping particles from wafer surface. The process may be practiced in a commercially available reactor and is suitable for ULSI devices having complex topographies, such as, for example, 64 megabit DRAMs employing crown type memory cells.

Abstract: This invention discloses a dual damascene structure supported on a semiconductor substrate. The dual damascene structure includes an etch-differentiating layer disposed above a top surface of the substrate. The dual damascene structure further includes a trench disposed on a top portion in the etch-differentiating layer. The dual damascene structure further includes an etched via disposed in the trench penetrating the etch differentiating layer therethrough above a non-etch-damaged portion of the top surface of the substrate.

Abstract: The present invention proposes a method for fabricating a non-volatile memory device using nano-crystals with an increased etching rate and an increased oxidation rate at the grain boundary, which is used in high-speed and low power consumption device. The method for fabricating a non-volatile memory device using nano-crystal dots comprises following processes. First process is to fabricate a tunneling dielectric 204 and a thin amorphous silicon continuous film. Second process is to fabricate a poly-silicon layer by poly-crystallizing the amorphous silicon film. Third process is to fabricate nano-crystals 212 by etching the poly-silicon layer. Fourth process is to fabricate an interlayer dielectric 214 on the nano-crystals 212. Fifth process is to attach a poly-silicon film to the interlayer dielectric 214 and fabricate a gate 216 and interconnects 220.

Abstract: An element isolation method, in particular, a shallow trench isolation (STI) method for semiconductor devices is disclosed in which a trench is formed to have a stepped structure shaped in such a fashion that it has a smaller width at its lower portion than at its upper portion. This stepped trench structure, which includes at least one step, is capable of obtaining an increased metal contact margin, thereby preventing metal contacts from being short-circuited with wells due to a misalignment thereof.

Abstract: Disclosed is a micromechanical system fabrication method using (111) single crystalline silicon as a silicon substrate and employing a reactive ion etching process in order to pattern a microstructure that will be separated from the silicon substrate and a selective release-etching process utilizing an aqueous alkaline solution in order to separate the microstructure from the silicon substrate. According to the micromechanical system fabrication method of the present invention, the side surfaces of microstructures can be formed to be vertical by employing the RIE technique. Furthermore, the microstructures can be readily separated from the silicon substrate by employing the selective release-etching technique using slow etching {111} planes as the etch stop in an aqueous alkaline solution. In addition, etched depths can be adjusted during the RIE step, thereby adjusting the thickness of the microstructure and the spacing between the microstructure and the silicon substrate.

Abstract: A method of manufacturing a semiconductor device includes the steps of: a) forming a wiring layer on a semiconductor substrate, the wiring layer being an Al or Al alloy layer, or a laminated wiring layer including an Al or Al alloy layer and a Ti or Ti alloy layer formed thereon; b) coating a resist layer on the wringing layer and patterning the resist layer to form a wiring resist pattern; c) patterning the wiring layer to form a wiring pattern 3 by using the wiring resist pattern as a mask; d) forming an interlayer insulating film 5 on the semiconductor substrate to cover the wiring pattern; e) coating a resist layer on the interlayer insulating film and patterning the resist layer to form a connection hole resist pattern 6; f) dry-etching the interlayer insulating film with an etching gas containing fluorine to form a connection hole reaching the wiring pattern 3, by using the connection hole resist pattern as a mask; g) after the step f), rinsing the semiconductor substrate in a liquid 10 made of a materi

Abstract: A process for forming a nanoporous dielectric silica coating on a surface of a substrate. The process includes spin-depositing alkoxysilane composition onto a surface of a substrate; spin depositing a surface hydrophobizing agent or a solvent onto an edge portion of the substrate to thereby remove the alkoxysilane composition from that area; and then curing the alkoxysilane composition to form a nanoporous dielectric silica coating. In another embodiment, an alkoxysilane composition layer is deposited onto a surface of a substrate. Then a solvent for the alkoxysilane substantially removes a portion of the alkoxysilane layer on the edge portion of the surface. This results in a transfer or cascading of a quantity of the alkoxysilane from a region adjacent to the edge portion to form a relatively thinner layer of the alkoxysilane onto the edge portion of the substrate surface. Then the relatively thinner alkoxysilane layer is removed prior to curing the alkoxysilane.

Abstract: A layer of silicon dioxide is formed conformably over a substrate having a surface with non-planar topography. The layer of silicon dioxide is then implanted with a species that affects the etch rate of the silicon dioxide when etched in an HF based etchant. The implant energy, dose, and direction are chosen such that only a selected portion of the layer of silicon dioxide is implanted with the implant species. The layer of silicon dioxide is then etched in an HF based etchant. The HF etchant etches both doped and undoped silicon dioxide, but the implanted silicon dioxide is removed at a faster rate or slower rate, depending on the implant species, than the unimplanted silicon dioxide. This allows the formation of specialized silicon dioxide structures due to the selectivity of the etch as between the implanted and unimplanted portions of the layer of silicon dioxide, without any damage to silicon.

Abstract: The present invention is directed to wet processing methods for the manufacture of electronic component precursors, such as semiconductor wafers used in integrated circuits. More specifically, this invention relates to methods, for example, prediffusion cleaning, stripping, and etching of electronic component precursors using sequential chemical processing techniques.