Abstract: A manufacturing method of the present invention comprises the steps of patterning to form a gate electrode pattern as well as an oxide film pattern by applying dry etching to a layered film which is formed, on a semiconductor substrate, of an oxide film and a SiGe film, being laid in this order; a first cleaning wherein, after the step of the patterning, the semiconductor substrate is cleaned with a first cleaning solution containing hydrofluoric acid; and a second cleaning wherein, after the step of the first cleaning, the semiconductor substrate is cleaned with a second cleaning solution containing ammonia and hydrogen peroxide.

Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

Abstract: The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.

Abstract: The invention relates to a process for treating semiconductor substrates in which metal layers are exposed by removing one or more layers of the surface of a semiconductor substrate which have been applied to the metal layer, in which exposure takes place in a time sequence to a first part of the layer by a dry etching step and to a second part of the layer by a wet etching step.

Abstract: A composition for removing side wall which includes an aqueous solution containing both nitric acid and at least one of carboxylic acids selected from the group consisting of polycarboxylic acid, aminocarboxylic acid, and salts thereof; a method of removing side wall; and a process for producing a semiconductor device. Use of the composition is effective in removing side wall at a low temperature in a short time in semiconductor device production without corroding the wiring material, e.g., an aluminium alloy. Thus, a semiconductor device having an aluminium alloy wiring which has undergone substantially no corrosion can be efficiently produced.

Abstract: A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by the method. The method includes formation and patterning of a mask on a silicon substrate followed by anisotropic etching of the silicon to provide a dense array of deep holes. Isotropic etching may be used to form a cavity beneath the dense array of holes and coupling to bottoms of the holes. Sides of the holes are then thermally oxidized. A conventional dielectric is then formed, sealing tops of the holes. The conventional dielectric is optionally densified. Conventional chemical-mechanical polishing then planarizes the dielectric and further conventional processing may be carried out on the wafer to form active circuitry together with passive components such as high Q inductors.

Abstract: A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a desired gate length and etching the etch-control layer and the hardmask layer; the portion of the circuit that has the correct gate length is covered with a blocking mask and the hardmask in the remainder is wet-etched to reduce its dimension, after which the gate stack is etched using both gate lengths of hardmask to produce different gate lengths in different areas.

Abstract: A method of manufacturing a semiconductor device provided with a first insulating film and a barrier film on a conductive region and an opening portion in the first insulating film and the barrier film, the method comprising the steps of: forming a first opening portion in the barrier film reaching the first insulating film; forming a second insulating film at least on the first insulating film in the first opening portion; and forming a second opening portion smaller than the first opening portion and reaching the conductive region by simultaneously boring a hole into the first insulating film and the second insulating film in the first opening portion.

Abstract: Organic etch residues are often left within vias formed by etching through resist masks. Since the etch is designed to expose an underlying metal layer and is directional in order to produce vertical via sidewalls, the residue often incorporates metal. The present invention discloses a method of removing such etch residues while passivating exposed metal, including exposing the residue to ammonia. In the disclosed embodiment, ammonia and oxygen are mixed in a plasma step, such that the resist can be burned off at the same time as the residue treatment. The residue can thus be easily rinsed away.

Abstract: A method for increasing area of a trench capacitor. First, a first oxide layer and a first nitride layer are sequentially formed on a substrate. An opening is formed through the first oxide layer and the first nitride layer into the substrate. A part of the first oxide layer exposed in the opening is removed to form a first recess, and then a second nitride layer is formed therein. A second oxide layer is formed in the lower portion of the opening. After a third nitride layer is formed in the upper portion of the opening, the second oxide layer is removed. The substrate in the opening is etched using the first nitride layer, the second nitride layer and the third nitride layer as a mask to form a second recess in the lower portion of the opening. The second nitride layer and the third nitride layer are then removed.

Abstract: A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process; isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process; and, anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.

Abstract: An improved pre-clean chamber of a semiconductor processing system minimizes the generation of particulates during processing, thereby decreasing contamination levels that can adversely affect plasma vapor deposition film properties while also decreasing operational costs. The pre-clean chamber comprises an insulator collar that insulates the outside diameter surface of a wafer pedestal, thereby mitigating the etching of the wafer pedestal during etching. The pre-clean chamber further comprises a gas trench cover that directs a suitable etching gas from a gas inlet trench into streams that are focused up and towards the center of the chamber to reduce the extent to which gas bombards the chamber cover. The pre-clean chamber also comprises a bellows cover which protects the bellows of a wafer lift during etching, further reducing the dislodgment of particulates during etching.

Abstract: The invention utilizes introductions of oxygen and hydroxyl to perform an in situ steam generated (ISSG) process to anneal and reoxidize a conventional sidewall oxide layer in a shallow trench isolation. The ISSG annealing process renders the conventional sidewall oxide layer much less stress. The electrical property of the active regions and the isolation quality between the active regions can be assured.

Abstract: A chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, the flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate. A method of etching a contact opening over a node location on a semiconductor substrate is disclosed.

Abstract: A method is provided for manufacturing a semiconductor memory device, particularly ferroelectric devices, in which an interlayer dielectric (ILD) layer formed on an upper part of a semiconductor substrate containing a capacitor structure is etched under conditions in which the plasma electron temperature is maintained in a range between 2.0 eV and 4.0 eV to open contact holes to expose the capacitor structure and thereby avoid degradation of the device characteristics.

Abstract: A semiconductor deposition system in accordance with the present invention includes a CMP apparatus operative to planarize an active surface of a semiconductor wafer, and a wafer cleaner for cleaning wafer after the CMP process. The wafer cleaner preferably.includes a wafer rotating mechanism, a steam inlet for applying steam to the active surface of the wafer as it is rotated and a liquid inlet for simultaneously applying a liquid to the back side surface of the wafer. A method for manufacturing an integrated circuit in accordance with the present invention includes subjecting an active surface of the wafer to a plurality of processes selected from a group including deposition, patterning, doping, planarization, ashing and etching, and steam cleaning the active surface at least once before, during, and after the plurality of processes. Preferably, an aqueous vapor phase is applied to the first surface of the wafer as an aqueous liquid phase is applied to the other surface of the wafer.

Abstract: The invention includes a method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising NO3−, F− and one or more organic acid anions having carboxylate groups. The invention also includes a semiconductor processing method of forming an opening to a copper-containing material. A mass is formed over a copper-containing material within an opening in a substrate. The mass contains at least one of an oxide barrier material and a dielectric material. A second opening is etched through the mass into the copper-containing material to form a base surface of the copper-containing material that is at least partially covered by particles comprising at least one of a copper oxide, a silicon oxide or a copper fluoride. The base surface is cleaned with a solution comprising nitric acid, hydrofluoric acid and one or more organic acids to remove at least some of the particles.

Abstract: A method of fabricating a semiconductor device causing no pattern shifting of a peripheral oxide film etc. in removal of both of an antireflection film and a mask pattern and having a fine structure not implementable solely by photolithography and the semiconductor device are obtained. The method of fabricating a semiconductor device comprises steps of forming a base film of either a silicon film or a silicon compound film on a semiconductor substrate, forming a hard film of either a metal film or a metal compound film on the base film, forming a resist pattern on the hard film, dryly etching the hard film through the resist pattern serving as a mask for forming a hard pattern, dryly etching the base film through the hard pattern serving as a mask and removing the hard pattern by wet etching with a chemical solution not etching at least the base film.

Abstract: First of all, a semiconductor substrate that has a memory array and a periphery region thereon is provided, wherein the memory array and the periphery region have a conducted layer, individually. Then an oxide layer or an oxide-nitride-oxide layer is formed on the conducted layer. Afterward, forming a photoresist layer on the oxide layer and defining the photoresist layer of the periphery region. The oxide layer and the conducted layer of the periphery region are etched until exposing the substrate surface of the periphery region by way of using a dry etching process and the photoresist layer as an etching mask. After the dry etching process is finished, a protected layer of the polymer will be formed on the etched sidewalls, so as to keep the etched profile. A wet etching process having a ultra dilute hydrofluoric acid (UDHF)or a mixed-acid solution SC1 is then performed to strip the protected layer of the polymer, so as to avoid the oxide loss.

Abstract: A trench is etched through the layers of pad oxide and silicon nitride that have been deposited on a substrate, the patterned layer of photoresist is left in place. A tilt angle nitrogen implant is performed into the surface of the substrate, a deep shallow STI trench is etched into the surface of the substrate. An oxygen implant of moderate intensity is performed in the created STI trench, the photoresist is removed. An anneal is performed on the implanted oxygen. A liner oxide is grown within the opening, High Density Plasma (HDP) oxide is deposited inside the opening and the top surface of the remaining silicon oxide. CMP is performed to the surface of the HDP oxide down to the surface of the pad oxide that completes the formation of the STI region under the first embodiment of the invention. The invention can be further extended by creating a LOCOS layer at the bottom of the STI opening or by further etching the bottom of the STI opening.

Abstract: A method for plasma etching a semiconductor feature to improve an etching profile including providing a semiconductor wafer comprising a first feature opening anisotropically etched though a thickness portion of at least one dielectric insulating layer; anisotropically etching a second feature opening overlying and at least partially encompassing the first feature opening according to a reactive ion etch (RIE) process to leave an unetched portion surrounding a first feature opening portion at about a bottom portion level of the second feature opening; and, plasma treating the first and second openings with a plasma formed of a mixture of oxygen and nitrogen plasma source gases including an applying an independently variable RF bias power source to the semiconductor wafer to remove the unetched portion.

Abstract: An inter-level metallization structure and the method of forming it, preferably based on copper dual damascene in which the lower-metal level is formed with a exposed metallization and an adjacent, embedded stop layer, both the metallization and embedded stop layer have exposed surfaces approximately level with each other with a lower dielectric layer. The upper-metal level includes a second stop layer deposited over the embedded stop layer and the first metallization and a second dielectric layer. An inter-level via is etched through the second dielectric layer and through the second stop layer and metal is filled into the via to contact the metallization. If the inter-level via is offset over the edge of the metallization, the metal in the via contacts the embedded stop layer and not the first dielectric layer, whereby the embedded stop layer acts as a copper diffusion barrier.

Abstract: Problems caused by a nonuniform processing profile are avoided by altering the area to be processed so as to compensate for the processing profile. More specifically, with regard to etching, problems caused by a nonuniform etch profile can be avoided by altering the mask employed in specifying the etch area so as to compensate for the etch profile. Nonuniform parameters of interest of structures which result from a nonuniform etch profile during the etching of a mask in which all the structures were identical can be avoided for by altering the mask employed in specifying the etch area so as to compensate for the etch profile. The mask is changed in a manner that is inversely proportional to the etch profile for each particular structure characteristic that determines the parameter of interest for which uniformity is desired.

Abstract: A method for removing a silicide poly on an integrated circuit (IC) chip. Specifically, one embodiment of the present invention discloses a method for exposing a gate oxide layer with a fluorine based reactive ion etching (F-based RIE) process and immersion in a sodium hydroxide based solution. The F-based RIE damages a silicide layer that covers a polysilicon gate layer. Damage to the silicide layer allows for penetration of chemicals to a polysilicon gate layer. Immersion of the IC chip in the sodium hydroxide based solution etches away the polysilicon gate layer and lifts off the silicide layer without altering an underlying gate oxide layer. Also, another embodiment uses a solution including sodium hydroxide and sodium chloride. As such, failure analysis of the gate oxide layer can proceed without concern for damage due to the removal process.

Abstract: A method for removing a hard mask during a semiconductor fabrication process is disclosed in which a hard mask material is used to pattern a first material. The method includes a two-step removal process that includes performing a major wet etch to remove a majority of the hard mask material, followed by performing a minor dry etch that removes a remainder of the hard mask material.

Abstract: An electromechanical device includes a first frame having a first aperture therein, a second frame suspended in the first frame wherein the second frame has a second aperture therein, and a plate suspended in the second aperture. A first pair of beams support the second frame along a first axis relative to the first frame so that the second frame rotates about the first axis. A second pair of beams supports the plate along a second axis relative to the second frame so that the plate rotates about the second axis relative to the frame. The first and second axes preferably intersect at a 90° angle. A first actuator provides mechanical force for rotating the second frame relative to the first frame about the first axis. A second actuator provides mechanical force for rotating the plate relative to the second frame about the second axis. Accordingly, the plate can be independently rotated relative to the first axis and the second axis. Related methods are also disclosed.

Abstract: A method for removing fluorine-containing etching residues during dual damascene process comprises providing a dual damascene structure having a copper conductor structure therein, a cap layer formed on the copper conductor structure and the dual damascene structure, and a low dielectric constant dielectric layer on the cap layer. The low dielectric constant dielectric layer formed by spin-on polymer method has at least an opening above the copper conductor structure. The cap layer is etched by fluorine-containing plasma to expose the copper conductor structure. The dual damascene structure is cleaned with a solvent and then the fluorine-containing etching residues are removed by plasma sputtering treatment or baking, or by a combination of both. The addition of baking and plasma sputtering treatment can prevent poor adhesion between the subsequent metal diffusion barrier layer and the low dielectric constant dielectric layer.

Abstract: The present invention generally provides a method for preventing surface corrosion in an edge bead removal process. The method includes rinsing the substrate surface with a rinsing solution containing a rinsing agent and an inhibiting agent prior to removing the edge bead. The inhibiting agent bonds to the substrate surface and operates to prevent corrosion of the substrate surface after the rinsing process.

Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

Abstract: A method of etching a metal or metal oxide, including a platinum family metal or a platinum family metal oxide. A wafer is first provided which comprises: (a) a semiconductor substrate, (b) a metal or metal oxide layer over the semiconductor substrate, and (c) a titanium containing patterned mask layer having one or more apertures formed therein positioned over the metal or metal oxide layer. The metal or metal oxide is then etched through the apertures in the mask layer by a plasma etching step that uses plasma source gases comprising the following: (a) a gas that comprises one or more carbon-oxygen bonds (for example, CO gas or CO2 gas) and (b) a gas that comprises one or more chlorine atoms (for example, Cl2 gas, carbon tetrachloride gas, silicon tetrachloride gas or boron trichloride gas).

Abstract: A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF3 molecules and the like contained in an etching gas, and compounds thus formed adhere to a surface of a silicon dioxide layer at side walls and a bottom portion of a via hole. As a result, once the material layer is exposed during etching for forming a hole, thereafter, the etching rate decreases. Accordingly even if there is misalignment of a via hole pattern with respect to a first wiring pattern when the via hole pattern is formed by lithography, etching of the silicon dioxide layer does not proceed to an underlying silicon substrate. Thus, short circuits are not formed between the first wiring and the silicon substrate via a second wiring layer which is deposited later.

Abstract: A method for manufacturing an SOI wafer. The method includes forming an oxide film on a surface of at least one silicon wafer of two silicon wafers. The method also includes bonding the silicon wafers through the oxide film at room temperature to form a room temperature bond end, one of the two silicon wafers being a bond wafer. The method further includes heat treating the wafers in an oxidizing atmosphere to form a heat treatment bond end. Thereafter, an outer periphery of the bond wafer is removed from an outer peripheral edge of the bond wafer up to a region between the room temperature bond end and the heat treatment bond end. The thickness of the bond wafer is reduced to form an SOI layer.

Abstract: A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as self-aligned metal silicide (or salicide) electrical contacts may be fabricated, with improved properties and with attenuated degradation. There is first provided a substrate with employed within a microelectronics fabrication having formed thereon patterned microelectronics layers with closely spaced features. There is then formed a salicide block layer employing silicon oxide dielectric material which may be selectively doped. There is then formed over the substrate a patterned photoresist etch mask layer. There is then etched the pattern of the patterned photoresist etch mask layer employing dry plasma reactive ion etching. An anhydrous etching environment is then employed to completely remove the silicon oxide dielectric salicide block layer with attenuated degradation of the microelectronics fabrication.

Abstract: A chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, the flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate. A method of etching a contact opening over a node location on a semiconductor substrate is disclosed.

Abstract: A method of forming a pattern in which production of reaction products in the interface between an organic anti-reflective coating and a radiation sensitive material coating is suppressed, the number of residues of an etchable layer formed after etching is decreased, and which provides a etched pattern having high resolution and good dimensional accuracy. According to the method, an etchable layer (11) composed of polysilicon coating an organic anti-reflective coating (12), and a radiation sensitive material coating (13) composed of a chemically amplified resist material containing as acid generators both (a) onium salt compound and (b) at least one of a sulfone compound and a sulfonate compound are formed on a semiconductor substrate (10), the radiation sensitive material coating (13) is imagewise exposed through the mask (14) and developed to form a patterned radiation sensitive material coating (13b).

Abstract: After forming a resist pattern on an insulating film deposited on a semiconductor substrate, the insulating film is subjected to plasma etching using an etching gas including carbon and fluorine with the resist pattern used as a mask. A polymer film having been deposited on the resist pattern during the plasma etching is subjected to a first stage of ashing with a relatively low chamber pressure and relatively low plasma generation power by using an oxygen gas or a gas including oxygen as a principal constituent. A residual polymer present on the insulating film in completing the first stage of the ashing is subjected to a second stage of the ashing with a relatively high chamber pressure and relatively high plasma generation power by using an oxygen gas or a gas including oxygen as a principal constituent.

Abstract: A method for removing contaminants from an integrated circuit substrate include treating the substrate with a hydrogen peroxide cleaning solution containing a chelating agent, and treating the substrate with hydrogen gas and fluorine-containing gas, and annealing the substrate. Cleaning solutions includes ammonium, hydrogen peroxide, deionized water, and chelating agent. The chelating agent includes one to three compounds selected from the group consisting of carboxylic acid compounds, phosphonic acid compounds, and hydroxyl aromatic compounds. The fluorine-containing gas is a gas selected from the group consisting of nitrogen trifluoride (NF3), hexafluorosulphur (SF6), and trifluorochlorine (ClF3).

Abstract: In a method of fabricating a microstructure for micro-fluidics applications, a mechanically stable support layer is formed over a layer of etchable material. An anisotropic etch is preformed through a mask to form a pattern of holes extending through the support layer into said etchable material. An isotropic etch is performed through each said hole to form a corresponding cavity in the etchable material under each hole and extending under the support layer. A further layer of depositable material is formed over the support layer until portions of the depositable layer overhanging each said hole meet and thereby close the cavity formed under each hole. The invention permits the formation of micro-channels and filters of varying configuration.

Abstract: In pre-treating a surface of a substrate in a process of forming a narrowed thin film pattern on the surface of the substrate from a solution such as a plating liquid, a mask with an opening corresponding to the thin film pattern to be formed later is formed on the surface of the substrate. Then, by micronizing a pre-treating liquid such as a water, a plating liquid, an acidic liquid ad an alkaline liquid, an atmosphere containing microparticles having diameters smaller than the minimum distance of the opening of the mask is produced. The substrate is positioned into the atmosphere, and the microparticles of the pre-treating liquid are stuck on the surface of the substrate exposing to the lower part of the opening of the mask. In using a water as the pre-treating liquid, the substrate is positioned into an atmosphere containing moisture vapor and the water particles are stuck on the surface of the substrate through their condensation.

Abstract: A low k dielectric layer is formed on a surface of a substrate of a semiconductor wafer. Then, a surface treatment is performed to the low k dielectric layer to form a passivation layer on a surface of the low k dielectric layer. A patterned photoresist layer is formed over the surface of the semiconductor wafer. The patterned photoresist layer is then used as a hard mask to perform an etching process on the low k dielectric layer. Finally, a stripping process is performed to remove the patterned photoresist layer. The passivation layer is used to prevent deterioration of the dielectric characteristic of the low k dielectric layer during the stripping process.

Abstract: A low dielectric constant (low k) material layer is positioned on a semiconductor wafer. A first hydrogen-containing plasma treatment is performed to reinforce a surface of the low k material layer against corrosion caused by a photoresist stripper. A photoresist layer, having an opening in the photoresist layer to expose portions of the low k material layer, is then coated on the low k material layer. By dry etching the low k material layer through the opening, a pattern in the photoresist layer is transferred to the low k material layer. An ashing process with an oxygen plasma supply is then performed to ash the photoresist layer. Finally, the semiconductor wafer is dipped in a wet stripper to completely remove the photoresist layer.

Abstract: A method of fabricating a semiconductor device causing no pattern shifting of a peripheral oxide film etc. in removal of both of an antireflection film and a mask pattern and having a fine structure not implementable solely by photolithography and the semiconductor device are obtained. The method of fabricating a semiconductor device comprises steps of forming a base film of either a silicon film or a silicon compound film on a semiconductor substrate, forming a hard film of either a metal film or a metal compound film on the base film, forming a resist pattern on the hard film, dryly etching the hard film through the resist pattern serving as a mask for forming a hard pattern, dryly etching the base film through the hard pattern serving as a mask and removing the hard pattern by wet etching with a chemical solution not etching at least the base film.

Abstract: A post-cleaning method of a via etching process for cleaning a wafer, the wafer having a tungsten (W) layer, an oxide layer covered on the tungsten layer, a photoresist layer patterned on the oxide layer, and a via passing through the photoresist layer and the oxide layer until a predetermined area of the tungsten layer is exposed, the cleaning method has the steps of: (a) performing a photoresist strip process to remove the photoresist layer; (b) performing a dry cleaning process which uses CF4 and N2H2 as the main reactive gas; and (c) performing a water-rinsing process.

Abstract: A recording head pole production process, and a pole made by the process, in which a combination of wet and dry etching steps are utilized to advantageously provide an undercut in the relatively high magnetic moment material beneath a photoresist area used to define the pole such that any re-deposited layer of material which occurs on the sides of the pole and photoresist area during the dry etching operation is advantageously rendered substantially discontinuous, or weakly linked, and the re-deposited material remaining on the pole itself following a photoresist strip can then be removed by being subjected to a stream of gaseous particles and ultimately carried away by the accompanying gas stream itself. In a particular embodiment disclosed herein the relatively high magnetic moment material may comprise a sputter deposited layer of cobalt-zirconium-tantalum (CoZrTa), iron-aluminum-nitride (FeAlN), iron-tantalum-nitride (FeTaN), iron-nitride (FeN) or similar materials.

Abstract: An undesirable side effect of some processes that are used for forming dual gate devices is the formation of defects at the interface between the two oxide layers of different thickness. This problem has been solved by preceding the HF wet dip (that is used to thin out a selected area of oxide) with exposure of the photoresist to a low power plasma that includes some oxygen. This treatment removes unsaturated chemical bonds from the resist surface and prevents the formation of SiC based defects. Such defects could cause polysilicon lines to short or open, depending on their size.

Abstract: A method of fabricating a trench isolation structure in a high-density semiconductor device that provides an isolation characteristic that is independent of the properties of adjacent MOS transistor devices, wherein a first trench in a first isolation area and a second trench implanted are formed on a semiconductor substrate, a nitrogen (N)-rich silicon layer is formed on the sidewall in a second isolation area, a subsequent oxidation process may be employed to fabricate oxide layers, each having a different thickness, on the sidewall surfaces of the first and second trenches. When the first and second oxide-layered trenches are filled with a stress relief liner and a dielectric material, the different thicknesses of the oxides prevent leakage currents from flowing to an adjacent semiconductor device, regardless of the doping properties of each device.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A method for fabricating a polycide self aligned contact for MOSFET devices in which the electrical isolation between the source/drain contact and gate structure is improved. In the method a gate insulator layer, a polysilicon layer, a metal silicide layer and an insulating layer are deposited on a semiconductor substrate. The insulator layer is patterned and anisotropically etched to expose the underlying metal silicide layer. The metal silicide layer is then dip etched to form an undercut beneath the insulating layer. The metal silicide and polysilicon layers are patterned with an anisotropic etch, dopants introduced into the opening to form lightly doped source/drain regions, and sidewall spacers formed on the sidewalls of the etched layers. After a dopant is introduced to form heavily doped source/drain regions, a contact structure is formed in the opening defined by the sidewall spacers.

Abstract: The present invention provides a method of forming a gate structure of a floating gate MOS field effect transistor.

Abstract: An apparatus and method for cleaning of disc-shaped objects, such as semiconductor wafers, employing a rotational fluid track. The cleaning may take place in a vertical cleaning chamber or optionally a horizontal cleaning chamber. Rotation of wafers is obtained without direct contact by motorized driver rollers that may have the potential of damaging the wafer. In preferred embodiments of the invention, a viscous shearing force is tangentially directed upon the surface of a wafer as the wafer rests upon support rollers within a cleaning chamber. Pressurized cleaning solutions are directed toward the wafer surface at an angle sufficient to impart a rotational force upon the wafer. In one embodiment of the invention, as the wafer spins within the cleaning chamber, a megasonic cleaning transducer is employed to enhance the surface cleaning process.