Abstract: A subcritical or supercritical water is used to selectively etch a silicon nitride film against a silicon dioxide film or to selectively etch a silicon dioxide film against a crystalline silicon region. This method is applicable to a process of forming a MISFET or a charge emitting device.

Abstract: Trenches are made in an integrated circuit by a process that incrementally increases the amount of oxygen during a trench etch. The trench may be an isolation trench or a gate trench for a QVDMOS device.

Abstract: A method of etching a dielectric layer employs steps of: providing a silicon substrate with a surface covered by the dielectric layer; polymer-rich plasma etching to remove part of the dielectric layer and form a polymer film on the exposed regions of the dielectric layer and the silicon substrate; performing an oxygen plasma treatment on the polymer film; and wet etching to completely remove the polymer film.

Abstract: Aspects for more reliable particle removal from a semiconductor processing chamber following a chamber wet clean are described. With the present invention, an improved particle removal following wet cleans of semiconductor processing chambers occurs. The present invention creates a turbulent gas flow in a chamber in order to more thoroughly remove particles from the chamber, including those that the wet clean procedures cannot reach. In a straightforward and efficient manner, the turbulent gas flow is created by providing gas in both an upper and lower portion of the chamber substantially simultaneously, including the advantageous use of the backside helium available to chamber processing.

Abstract: A method of forming an electrical contact to semiconductive material includes forming an insulative layer over a contact area of semiconductive material. A contact opening is etched through the insulative layer to the semiconductive material contact area. Such etching changes an outer portion of the semiconductive material exposed by the etching. The change is typically in the form of modifying crystalline structure of only an outer portion from that existing prior to the etch. The changed outer portion of the semiconductive material is etched substantially selective relative to semiconductive material therebeneath which is unchanged. The preferred etching chemistry is a tetramethyl ammonium hydroxidde solution. A conductive material within the contact opening is formed in electrical connection with the semiconductive material.

Abstract: A method and system for etching gate oxide during transistor fabrication is disclosed. The method and system begin by depositing a gate oxide on a substrate, followed by a deposition of a tunnel oxide mask over a portion of the gate oxide. The method and system further include performing a combination dry/wet-etch to remove the gate oxide uncovered by the tunnel oxide mask, which minimizes tunnel oxide undercut.

Abstract: Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly damascene and dual damascene metallization, the method advantageously lines insulating surfaces with a barrier material. The selective formation allows the deposition to be “bottomless,” thus leaving the conductive material at a via bottom exposed for direct metal-to-metal contact when further conductive material is deposited into the opening after barrier formation on the insulating surfaces. Desirably, the selective deposition is accomplished by atomic layer deposition (ALD), resulting in highly conformal coverage of the insulating sidewalls in the opening.

Abstract: A method for forming an improved RPO layer by using a composite layer and a two-step etching process in a salicide process in the fabrication of integrated circuits is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas wherein at least one device area is to be silicided and wherein at least one device area is not to be silicided. A composite resist protective oxide layer is formed overlying device areas comprising a first layer of oxide and a second layer of silicon oxynitride. The silicon oxynitride layer is dry etched away overlying the device area to be silicided. Thereafter, the oxide layer is wet etched away overlying the device area to be silicided. Silicidation is performed to complete fabrication of the integrated circuit device.

Abstract: A method of cleaning polycide gates after an etching step. A gate oxide layer, a polysilicon layer, a titanium nitride layer, a silicide layer, an anti-reflection layer and a patterned photoresist layer are sequentially formed over a substrate. An etching operation is next carried out to form a gate structure. The gate structure is formed by patterning the polysilicon layer, the titanium nitride layer and the silicide layer. The gate structure is subsequently cleaned in a three-step cleaning operation. In the first cleaning step, minute amount of fluoride-containing compound, hydrogen and inert gas are used as gaseous reactants in a plasma-cleaning operation. The fluoride-containing compound is capable of initiating a free radical chain reaction. In the second cleaning step, a solvent containing ammonium ions is applied to the gate structure. In the third cleaning step, a solution formed by dissolving oxidizing agent in de-ionized water is applied.

Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.

Abstract: A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O2, HBr and NF3. An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O2, HBr and SF6 or F2.

Abstract: There is described a method of manufacturing a semiconductor device for accurately and anisotropically etching desired locations on a semiconductor wafer at high selectivity. A polysilicon layer which is to act as a floating gate is embedded in the surface of an oxide film insulating layer. Control gates are formed in a direction orthogonal to the polysilicon layer. Exposed portions of the polysilicon layer are subjected to dry-etching, thereby forming a floating gate. Residues remaining in the channels formed in the oxide film insulating layer are removed by means of wet etching.

Abstract: A method for determining the AB etch endpoint during an silicon trench isolation fabrication process requires the introduction into the STI design a sufficient quantity of “dummy” diffusion structures that provide a strong endpoint signal during normal STI fabrication and, that which endpoint signal may be controlled by adjustment of the planarization shapes associated with the dummy diffusion structures.

Abstract: A method of forming a trench isolation in a semiconductor substrate is described, which comprises the steps of forming a trench on the substrate, forming a diffusion barrier insulating layer, forming a thermal oxide layer both sidewall and bottom of the trench contacted with the diffusion barrier insulating layer, forming a nitride liner, and forming trench isolation material to fill the trench. A multi-structure of the barrier layer and the thermal oxide layer is provided between the nitride liner and the trench, resulting in minimization of transistor characteristic deterioration. A thin thermal oxide layer is formed to achieve improved trench etching profile.

Abstract: In an improved method for etching a groove n the uppermost layer of a semiconductor wafer, a conventional anisotropic etch is performed to achieve a narrow groove and an isotropic etch is performed to widen the groove at the device surface and thereby round the edges where the walls of the groove meet the surface of the wafer. During a later step of applying a protective tape to the device side of the wafer to protect it during a step of grinding the back of the wafer, the rounded edges of the groove are unlikely to cut through the adhesive layer of the tape and thereby cause particles of adhesive to remain on the wafer surface when the tape is removes.

Abstract: An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.

Abstract: A method of forming a shallow trench isolation structure comprising the following steps. A substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers.

Abstract: A method of fabricating a thin film transistor (TFT) assembly having a plurality of array lines, a plurality of pads, a plurality of link lines connecting the pads to the array lines, an insulating layer, and an electrode pattern formed on a substrate, and further having short-preventing structures for preventing electrical shorts between the pads and the link lines. The method includes the steps of forming the plurality of pads on the substrate, depositing the insulating layer on the substrate including over the pads, etching the insulating layer to form contact holes, and etching the insulating layer between the adjacent pads to expose a surface of the substrate to prevent a short between the adjacent pads from occurring, and forming the electrode pattern on the insulating layer by depositing and patterning an electrode layer such that the electrode pattern contacts the pads through the contact holes formed in the insulating layer.

Abstract: A method for forming a protection device with slope laterals is provided. Firstly, providing a semiconductor substrate having a plurality of alternative first sacrificial layers and second sacrificial layers formed thereon. A first etching step is performed to remove one portion of each of the first sacrificial layers and thereby expose one portion of each lateral of each of the second sacrificial layers. Subsequently, performing a second etching step to remove one portion of the lateral of the second sacrificial layer. Then, repeatedly and alternately performing the first etching step and the second etching step until completely removing the first sacrificial layers and then obtaining a plurality of protection devices formed of the second sacrificial layers each of which having slope laterals.

Abstract: In manufacturing a semiconductor device, a metal polymer film and photoresist film are removed with an amine-based organic solvent subsequent to anisotropic etching of an insulating film on a bonding pad, an organic polymer film is removed with the oxygen plasma, and a wire is bonded to the bonding pad. In removal with the amine-based organic solvent, no aluminum oxide film is formed on the surface of the bonding pad. Pores are formed in the surface of the bonding pad upon removal, and the material of a wire bond enters these holes. As a result, a semiconductor device in which the wire bonded to the bonding pad hardly peels off can be manufactured.

Abstract: In semiconductor dynamic random access memory circuits using stacked capacitor storage elements formed using high permittivity dielectric material, it is typical to form the stacked capacitors using noble metal electrodes. Typically, the etching process for the noble metal electrodes requires the use of a hard mask patterning material such as silicon oxide. Removal of this hard mask frequently results in damage to the dielectric surface surrounding the patterned noble metal electrode.

Abstract: A process for reducing dishing in damascene structures formed in low k organic dielectrics is described. A key feature is the insertion of a liner layer between the low k dielectric layer and the etch stop layer. The only requirement for the liner material is that it should have different etching characteristics from the etch stop material so that when trenches are etched in the dielectric they extend as far as the etch stop layer, in the normal way. When this is done it is found that dishing, after CMP, is significantly reduced, particularly for trench structures made up of multiple narrow trenches spaced close together.

Abstract: A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired.

Abstract: The present invention provides a method of preventing the dishing phenomenon occurring atop a dual damascene structure on a semiconductor wafer. The semiconductor has a substrate, a first dielectric layer positioned on the substrate, a dual damascene hole positioned in the first dielectric layer through to the surface of the substrate, a barrier layer covering the surface of the first dielectric layer and both the surface of the walls and bottom of the dual damascene hole, and a copper layer positioned on the barrier layer and filling the dual damascene hole to form the dual damascene structure. The method first involves performing a first chemical mechanical polishing (CMP) process to remove portions of the copper layer down to the surface of the barrier layer. A photoresist layer is then formed atop the dual damascene structure to remove portions of the barrier layer uncovered by the photoresist layer.

Abstract: A method and apparatus for processing a wafer is described. According to the present invention a wafer is placed on a substrate support. A liquid is then fed through a conduit having an output opening over the wafer. A gas is dissolved in the liquid prior to the liquid reaching the output over the wafer by flowing a gas into the conduit through a venturi opening formed in the conduit. The liquid with dissolved gas is then fed through the opening and onto the wafer where it can be used to etch, clean, or rinse a wafer.

Abstract: Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly damascene and dual damascene metallization, the method advantageously lines insulating surfaces with a barrier material. The selective formation allows the deposition to be “bottomless,” thus leaving the conductive material at a via bottom exposed for direct metal-to-metal contact when further conductive material is deposited into the opening after barrier formation on the insulating surfaces. Desirably, the selective deposition is accomplished by atomic layer deposition (ALD), resulting in highly conformal coverage of the insulating sidewalls in the opening.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: An SOI layer is thinned without a thermal oxidation process. An SOI substrate (10) is immersed in an etching bath filled with an NH3—H2O2—H2O solution to be isotropically etched. This produces a 100-nm thick SOI layer (3) with no crystal defect.

Abstract: An SOI layer is thinned without a thermal oxidation process. An SOI substrate (10) is immersed in an etching bath filled with an NH3—H2O2—H2O solution to be isotropically etched. This produces a 100-mn thick SOI layer (3) with no crystal defect.

Abstract: A method of cleaning a substrate is provided which can remove contamination after treatment of a substrate surface by use of chemicals etc. prior to film formation. The method of cleaning the substrate surface uses of a vapor of chlorosulfonic acid (SO2Cl(OH)).

Abstract: An interlayer dielectric film is formed over a semiconductor substrate that may have a device element formed thereon. The interlayer dielectric film includes at least a first silicon oxide film and a second silicon oxide film as a cap layer being formed on the first silicon oxide film. The first silicon oxide film is formed by reacting SiH4 and H2O2 by a CVD method. The first silicon oxide film and the second silicon oxide film may be isotropically etched to form a through hole. The isotropic etching speed for the first silicon oxide film is the same as or generally the same as the etching speed for the second silicon oxide film (the cap layer). As a result, both the first silicon oxide film and the second silicon oxide film can be isotropically etched without causing excessive etching on the first silicon oxide film Therefore, the degree of freedom in isotropic etching is improved in isotropically etching multiple layers.

Abstract: A method for cleaning bonding pads on a semiconductor device, as disclosed herein, includes treating the bonding pads with a CF4 and water vapor combination. In the process, the water vapor breaks up and the hydrogen from the water vapor couples to fluorine residue on the bonding pad surface creating a volatile HF vapor. In addition, fluorine from the CF4 exchanges with the titanium in the metallic polymer residue making the polymer more soluble for the organic strip operation which follows. Next, the resist is ashed and then an organic resist stripper is applied to the bonding pad area, thereby creating a clean bonding pad surface. Thereafter, a reliable bond wire connection can be made to the bonding pad.

Abstract: Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.

Abstract: A cleaning method for a copper dual damascene process, applicable for cleaning a structure having a dual damascene opening. The method begins with preparing a first chemical solution and a second chemical solution. The first chemical solution includes a deionized water, a hydrogen peroxide, and a surfactant, whereas the second chemical solution includes a deionized water, a hydrogen fluoride, and a hydrogen chloride. A first cleaning step is performed using the first chemical solution to remove particles and polymers that remain on a surface of a copper layer and the dual damascene opening. This is followed by performing a second cleaning step using the second chemical solution to remove a copper oxide layer on the copper layer.

Abstract: A method for forming dielectric protection in different regions of a semiconductor device, in accordance with the present invention, includes forming structures in a first region and a second region. A dielectric layer is grown on surfaces of the structures and in between the structures in the first region and the second region. The dielectric layer is damaged in the second region to provide an altered layer which is etchable at a faster rate than the dielectric layer in the first region. The dielectric layer in the first region and the altered layer in the second region are etched to provide a dielectric protection layer having a first thickness in the first region and a second thickness in the second region.

Abstract: Spacers are formed on a semiconductor device by depositing a spacer layer on the semiconductor device. The semiconductor device is subjected to an anisotropic etching process to leave at least a portion of the spacer layer covering the semiconductor device. The semiconductor device is then subjected to an isotropic etching process to form the spacers on the semiconductor device.

Abstract: A method of preparing a TEM sample. A focused ion beam is used to deposit a mask on the material to be sampled. Reactive ion etching removes material not protected by the mask, leaving a wall thin enough to be imaged by TEM.

Abstract: A film forming method includes forming a metal or silicide film by a deposition apparatus which is cleaned by passing a cleaning gas therethrough and subjected to an idle deposition using a material for the metal or silicide film intended to be formed within 24 hours after cleaning. Thereby the content of a halogen element in the formed film is reduced.

Abstract: A method of cleaning a substrate is provided which can remove contamination after working a surface of a substrate by use of chemicals etc. or treat the surface of a substrate by use of the chemicals, etc. prior to film formation. The method of cleaning the substrate can clean the surface of the substrate 30 by use of a vapor of chlorosulfonic acid (SO2Cl(OH)).

Abstract: A dielectric layer is formed by depositing a first dielectric layer above a semiconductor substrate including recessed regions, etching the first dielectric layer to remove any voids and to lower the aspect ratio of the recessed regions, and depositing a second dielectric layer on the first dielectric layer in the recessed regions. The method is particularly useful when the aspect ratios are high for recessed regions formed between patterns.

Abstract: A method of cleanly etching an organic polymer layer disposed over a substrate is disclosed. The invention is particularly useful in damascene processing where openings are etched in the organic polymer layer to form interconnects. The method includes lowering the temperature of the substrate. The method also includes flowing H2O vapor over the organic polymer layer and condensing (or freezing) the H2O vapor on the organic polymer layer. The method additionally includes etching through the organic polymer layer and the condensed H2O vapor to form an opening having a side wall. The condensed (or frozen) H2O vapor is arranged to form a passivating film (of ice) along the side wall of the opening to protect the side wall from etching.

Abstract: There is described a method of manufacturing a semiconductor device for accurately and anisotropically etching desired locations on a semiconductor wafer at high selectivity. A polysilicon layer which is to act as a floating gate is embedded in the surface of an oxide film insulating layer. Control gates are formed in a direction orthogonal to the polysilicon layer. Exposed portions of the polysilicon layer are subjected to dry-etching, thereby forming a floating gate. Residues remaining in the channels formed in the oxide film insulating layer are removed by means of wet etching.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A metallization process for manufacturing semiconductor devices and a system that uses the same that minimizes corrosion failures in aluminum patterns. The process for the metal pattern formation is carried out by loading a semiconductor wafer into an etching chamber, the semiconductor wafer having a photoresist pattern formed over a metal material layer, stabilizing the environment in the etching chamber, main-etching the metal material layer to the etch-end point by using the photoresist pattern as an etch mask while supplying etching gas containing chlorine (Cl2) into the etching chamber, over-etching the metal material layer for a certain period of time over the etch-end point so as to form metal patterns, purging the etching chamber after the over-etching step, and unloading the wafer from the etching chamber. The pressure in the transfer module is optimized, and the load lock chamber is continuously purged.

Abstract: Adherent matrix layers such as post-etch and other post-process residues are removed from a substrate by exposing them to a vapor phase solvent to allow penetration of the vapor phase solvent into the adherent matrix layers and condensing the vapor phase solvent into the adherent matrix layers and revaporized to promote fragmentation of the matrix and facilitate removal. Megasonic energy may be transmitted via a transmission member to the adherent matrix through the solvent condensed thereon to loosen fragments and particles. The substrate is typically rotated to improve contact between the megasonic energy transmission member and the condensed solvent and achieve more uniform cleaning. A co-solvent which is soluble in the vapor phase solvent may be added to enhance removal of specific adherent matrix materials.

Abstract: The high Q inductor process for reducing substrate interaction of integrated inductors includes etching away some of the silicon substrate after the inductor has been formed on the substrate. A first etch process is performed to form an opening in the center of the inductor exposing the silicon substrate. A second etch process is performed to etch the exposed silicon substrate to form a trench in the silicon substrate. A third etch process is performed to etch the trench into an inverted pyramidal cavity within the substrate and extending beneath the inductor. The pyramidal cavity is then filled with a solution, such as spin-on-glass thereby providing mechanical support for the inductor.

Abstract: The selectivity of an etchant to a capping layer in a Cu or Cu alloy interconnect member is significantly enhanced by providing a dielectric layer thereon with a faster etch rate. Embodiments include forming the dielectric layer with a faster etch rate by PECVD: (a) at a low frequency bias of about 0.1 kW or greater; (b) at a temperature of about 250° C. or greater; or (c) at a pressure greater than about 2.6 Torr.

Abstract: An HSQ film 4 is formed on a silicon oxide film 1 and the film 4 is subject to B2H6 plasma irradiation, to form a boron-implanted region 5. After forming a plasma TEOS film 6 on the region, a concave 8 is formed with a hydrofluoric acid-containing etchant, while wet-etching is stopped on the boron-implanted region 5. Then, the exposed HSQ film 4 in the bottom of the concave 8 is dry-etched to form a contact hole 9 reaching an Al interconnection 2. Then, the contact hole 9 is filled with an upper interconnection material to provide a multilayered interconnection structure.

Abstract: A method for forming an IPO between two polysilicon layers that produces an oxide of superior uniformity and eliminates undercutting, stringer formation, fringe electric fields and plasma damage. The method modifies the prior art by using a densified TEOS mask to allow etching away of the substrate oxide and allow the selective etch of a subsequent non-densified TEOS layer. A high temperature thermal oxide (HTO) then covers the resulting formation. The thickness of the second TEOS layer can be controlled to prevent field fringing and the underlying HTO layer prevents undercutting and stringer formation.

Abstract: A process for etching a dielectric layer, including the steps of forming, over the dielectric layer, a layer of polysilicon, forming over the layer of polysilicon a photoresist mask layer, etching the layer of polysilicon using the photoresist mask layer as an etching mask for selectively removing the layer of polysilicon, removing the photoresist mask layer from over the layer of polysilicon, etching the dielectric layer using the layer of polysilicon as a mask. Subsequently, the layer of polysilicon is converted into a layer of a transition metal silicide, and the layer of transition metal silicide is etched for selectively removing the latter from over the dielectric layer.